1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Workertarget datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 3*9880d681SAndroid Build Coastguard Workertarget triple = "x86_64-unknown-linux-gnu" 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Workerdefine void @test(i256* %a, i256* %b, i256* %out) #0 { 6*9880d681SAndroid Build Coastguard Workerentry: 7*9880d681SAndroid Build Coastguard Worker %av = load i256, i256* %a 8*9880d681SAndroid Build Coastguard Worker %bv = load i256, i256* %b 9*9880d681SAndroid Build Coastguard Worker %r = mul i256 %av, %bv 10*9880d681SAndroid Build Coastguard Worker store i256 %r, i256* %out 11*9880d681SAndroid Build Coastguard Worker ret void 12*9880d681SAndroid Build Coastguard Worker} 13*9880d681SAndroid Build Coastguard Worker 14*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: @test 15*9880d681SAndroid Build Coastguard Worker; There is a lot of inter-register motion, and so matching the instruction 16*9880d681SAndroid Build Coastguard Worker; sequence will be fragile. There should be 6 underlying multiplications. 17*9880d681SAndroid Build Coastguard Worker; CHECK: imulq 18*9880d681SAndroid Build Coastguard Worker; CHECK: imulq 19*9880d681SAndroid Build Coastguard Worker; CHECK: imulq 20*9880d681SAndroid Build Coastguard Worker; CHECK: imulq 21*9880d681SAndroid Build Coastguard Worker; CHECK: imulq 22*9880d681SAndroid Build Coastguard Worker; CHECK: imulq 23*9880d681SAndroid Build Coastguard Worker; CHECK-NOT: imulq 24*9880d681SAndroid Build Coastguard Worker; CHECK: retq 25*9880d681SAndroid Build Coastguard Worker 26*9880d681SAndroid Build Coastguard Workerattributes #0 = { norecurse nounwind uwtable "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" } 27*9880d681SAndroid Build Coastguard Worker 28