xref: /aosp_15_r20/external/llvm/test/CodeGen/X86/mul-i256.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1; RUN: llc < %s | FileCheck %s
2target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
3target triple = "x86_64-unknown-linux-gnu"
4
5define void @test(i256* %a, i256* %b, i256* %out) #0 {
6entry:
7  %av = load i256, i256* %a
8  %bv = load i256, i256* %b
9  %r = mul i256 %av, %bv
10  store i256 %r, i256* %out
11  ret void
12}
13
14; CHECK-LABEL: @test
15; There is a lot of inter-register motion, and so matching the instruction
16; sequence will be fragile. There should be 6 underlying multiplications.
17; CHECK: imulq
18; CHECK: imulq
19; CHECK: imulq
20; CHECK: imulq
21; CHECK: imulq
22; CHECK: imulq
23; CHECK-NOT: imulq
24; CHECK: retq
25
26attributes #0 = { norecurse nounwind uwtable "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" }
27
28