1; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hsdr < %s | FileCheck %s 2; Check that the combine/stxw instructions are being generated. 3; In case of combine one of the operand should be 0 and another should be 4; the output of absolute addressing load instruction. 5 6@a = external global i16 7@b = external global i16 8@c = external global i16 9@char_a = external global i8 10@char_b = external global i8 11@char_c = external global i8 12@int_a = external global i32 13@int_b = external global i32 14@int_c = external global i32 15 16; Function Attrs: nounwind 17define i64 @short_test1() #0 { 18; CHECK: [[VAR:r[0-9]+]]{{ *}}={{ *}}memuh(## 19; CHECK: combine(#0, [[VAR]]) 20entry: 21 store i16 0, i16* @a, align 2 22 %0 = load i16, i16* @b, align 2 23 %conv2 = zext i16 %0 to i64 24 ret i64 %conv2 25} 26 27; Function Attrs: nounwind 28define i64 @short_test2() #0 { 29; CHECK: [[VAR1:r[0-9]+]]{{ *}}={{ *}}memh(## 30; CHECK: sxtw([[VAR1]]) 31entry: 32 store i16 0, i16* @a, align 2 33 %0 = load i16, i16* @c, align 2 34 %conv2 = sext i16 %0 to i64 35 ret i64 %conv2 36} 37 38; Function Attrs: nounwind 39define i64 @char_test1() #0 { 40; CHECK: [[VAR2:r[0-9]+]]{{ *}}={{ *}}memub(## 41; CHECK: combine(#0, [[VAR2]]) 42entry: 43 store i8 0, i8* @char_a, align 1 44 %0 = load i8, i8* @char_b, align 1 45 %conv2 = zext i8 %0 to i64 46 ret i64 %conv2 47} 48 49; Function Attrs: nounwind 50define i64 @char_test2() #0 { 51; CHECK: [[VAR3:r[0-9]+]]{{ *}}={{ *}}memb(## 52; CHECK: sxtw([[VAR3]]) 53entry: 54 store i8 0, i8* @char_a, align 1 55 %0 = load i8, i8* @char_c, align 1 56 %conv2 = sext i8 %0 to i64 57 ret i64 %conv2 58} 59 60; Function Attrs: nounwind 61define i64 @int_test1() #0 { 62; CHECK: [[VAR4:r[0-9]+]]{{ *}}={{ *}}memw(## 63; CHECK: combine(#0, [[VAR4]]) 64entry: 65 store i32 0, i32* @int_a, align 4 66 %0 = load i32, i32* @int_b, align 4 67 %conv = zext i32 %0 to i64 68 ret i64 %conv 69} 70 71; Function Attrs: nounwind 72define i64 @int_test2() #0 { 73; CHECK: [[VAR5:r[0-9]+]]{{ *}}={{ *}}memw(## 74; CHECK: sxtw([[VAR5]]) 75entry: 76 store i32 0, i32* @int_a, align 4 77 %0 = load i32, i32* @int_c, align 4 78 %conv = sext i32 %0 to i64 79 ret i64 %conv 80} 81