xref: /aosp_15_r20/external/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir (revision 9880d6810fe72a1726cb53787c6711e909410d58) 
1# RUN: llc -march=amdgcn -run-pass rename-independent-subregs -o - %s | FileCheck %s
2--- |
3  define void @test0() { ret void }
4...
5---
6# In the test below we have two independent def+use pairs of subregister1 which
7# can be moved to a new virtual register. The third def of sub1 however is used
8# in combination with sub0 and needs to stay with the original vreg.
9# CHECK-LABEL: name: test0
10# CHECK: S_NOP 0, implicit-def undef %0:sub0
11# CHECK: S_NOP 0, implicit-def undef %2:sub1
12# CHECK: S_NOP 0, implicit %2:sub1
13# CHECK: S_NOP 0, implicit-def undef %1:sub1
14# CHECK: S_NOP 0, implicit %1:sub1
15# CHECK: S_NOP 0, implicit-def %0:sub1
16# CHECK: S_NOP 0, implicit %0
17name: test0
18isSSA: true
19registers:
20  - { id: 0, class: sreg_128 }
21body: |
22  bb.0:
23    S_NOP 0, implicit-def undef %0:sub0
24    S_NOP 0, implicit-def %0:sub1
25    S_NOP 0, implicit %0:sub1
26    S_NOP 0, implicit-def %0:sub1
27    S_NOP 0, implicit %0:sub1
28    S_NOP 0, implicit-def %0:sub1
29    S_NOP 0, implicit %0
30...
31