xref: /aosp_15_r20/external/llvm/test/CodeGen/AMDGPU/multilevel-break.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck %s
2
3; CHECK-LABEL: {{^}}define amdgpu_vs void @main
4; CHECK: main_body:
5; CHECK: LOOP.outer:
6; CHECK: LOOP:
7; CHECK:     [[if:%[0-9]+]] = call { i1, i64 } @llvm.amdgcn.if(
8; CHECK:     [[if_exec:%[0-9]+]] = extractvalue { i1, i64 } [[if]], 1
9;
10; CHECK: Flow:
11;
12; Ensure two else.break calls, for both the inner and outer loops
13;
14; CHECK:        call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
15; CHECK-NEXT:   call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
16; CHECK-NEXT:   call void @llvm.amdgcn.end.cf
17;
18; CHECK: Flow1:
19define amdgpu_vs void @main(<4 x float> %vec, i32 %ub, i32 %cont) {
20main_body:
21  br label %LOOP.outer
22
23LOOP.outer:                                       ; preds = %ENDIF, %main_body
24  %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
25  br label %LOOP
26
27LOOP:                                             ; preds = %ENDIF, %LOOP.outer
28  %tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
29  %tmp47 = add i32 %tmp45, 1
30  %tmp48 = icmp slt i32 %tmp45, %ub
31  br i1 %tmp48, label %ENDIF, label %IF
32
33IF:                                               ; preds = %LOOP
34  ret void
35
36ENDIF:                                            ; preds = %LOOP
37  %tmp51 = icmp eq i32 %tmp47, %cont
38  br i1 %tmp51, label %LOOP, label %LOOP.outer
39}
40
41attributes #0 = { nounwind readnone }
42