xref: /aosp_15_r20/external/llvm/test/CodeGen/AArch64/arm64-vcvtxd_f32_f64.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58) 
1; RUN: llc < %s -march=arm64 | FileCheck %s
2
3define float @fcvtxn(double %a) {
4; CHECK-LABEL: fcvtxn:
5; CHECK: fcvtxn s0, d0
6; CHECK-NEXT: ret
7  %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
8  ret float %vcvtxd.i
9}
10
11declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone
12