xref: /aosp_15_r20/external/llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1# RUN: rm -f %S/arm64-regress-opt-cmp.s
2# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s 2>&1 | FileCheck %s
3# CHECK: %1 = ANDWri {{.*}}
4# CHECK-NEXT: %wzr = SUBSWri {{.*}}
5--- |
6  define i32 @test01() nounwind {
7  entry:
8    %0 = select i1 true, i32 1, i32 0
9    %1 = and i32 %0, 65535
10    %2 = icmp ugt i32 %1, 0
11    br i1 %2, label %if.then, label %if.end
12
13  if.then:                                      ; preds = %entry
14    ret i32 1
15
16  if.end:                                       ; preds = %entry
17    ret i32 0
18  }
19...
20---
21name:            test01
22registers:
23  - { id: 0, class: gpr32 }
24  - { id: 1, class: gpr32common }
25body:             |
26  bb.0.entry:
27    successors: %bb.2.if.end, %bb.1.if.then
28
29    %0 = MOVi32imm 1
30    %1 = ANDWri killed %1, 15
31    %wzr = SUBSWri killed %1, 0, 0, implicit-def %nzcv
32    Bcc 9, %bb.2.if.end, implicit %nzcv
33
34  bb.1.if.then:
35    %w0 = MOVi32imm 1
36    RET_ReallyLR implicit %w0
37
38  bb.2.if.end:
39    %w0 = MOVi32imm 0
40    RET_ReallyLR implicit %w0
41
42...
43