1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Helper classes. 21// 22 23class ProcNoItin<string Name, list<SubtargetFeature> Features> 24 : Processor<Name, NoItineraries, Features>; 25 26class Architecture<string fname, string aname, list<SubtargetFeature> features > 27 : SubtargetFeature<fname, "ARMArch", aname, 28 !strconcat(aname, " architecture"), features>; 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget state. 32// 33 34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 35 "Thumb mode">; 36 37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 38 "Use software floating point features.">; 39 40//===----------------------------------------------------------------------===// 41// ARM Subtarget features. 42// 43 44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 45 "Enable VFP2 instructions">; 46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 47 "Enable VFP3 instructions", 48 [FeatureVFP2]>; 49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 50 "Enable NEON instructions", 51 [FeatureVFP3]>; 52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 53 "Enable Thumb2 instructions">; 54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 55 "Does not support ARM mode execution", 56 [ModeThumb]>; 57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 58 "Enable half-precision floating point">; 59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 60 "Enable VFP4 instructions", 61 [FeatureVFP3, FeatureFP16]>; 62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 63 "true", "Enable ARMv8 FP", 64 [FeatureVFP4]>; 65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 66 "Enable full half-precision floating point", 67 [FeatureFPARMv8]>; 68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 69 "Restrict FP to 16 double registers">; 70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 71 "Enable divide instructions">; 72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 73 "HasHardwareDivideInARM", "true", 74 "Enable divide instructions in ARM mode">; 75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 76 "Enable Thumb2 extract and pack instructions">; 77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 78 "Has data barrier (dmb / dsb) instructions">; 79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 80 "Has v7 clrex instruction">; 81def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 82 "HasAcquireRelease", "true", 83 "Has v8 acquire/release (lda/ldaex etc) instructions">; 84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 85 "FP compare + branch is slow">; 86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 87 "Floating point unit supports single precision only">; 88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 89 "Enable support for Performance Monitor extensions">; 90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 91 "Enable support for TrustZone security extensions">; 92def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 93 "Enable support for ARMv8-M Security Extensions">; 94def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 95 "Enable support for Cryptography extensions", 96 [FeatureNEON]>; 97def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 98 "Enable support for CRC instructions">; 99// Not to be confused with FeatureHasRetAddrStack (return address stack) 100def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 101 "Enable Reliability, Availability and Serviceability extensions">; 102 103 104// Cyclone has preferred instructions for zeroing VFP registers, which can 105// execute in 0 cycles. 106def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 107 "Has zero-cycle zeroing instructions">; 108 109// Whether or not it may be profitable to unpredicate certain instructions 110// during if conversion. 111def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 112 "IsProfitableToUnpredicate", 113 "true", 114 "Is profitable to unpredicate">; 115 116// Some targets (e.g. Swift) have microcoded VGETLNi32. 117def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 118 "HasSlowVGETLNi32", "true", 119 "Has slow VGETLNi32 - prefer VMOV">; 120 121// Some targets (e.g. Swift) have microcoded VDUP32. 122def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true", 123 "Has slow VDUP32 - prefer VMOV">; 124 125// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 126// for scalar FP, as this allows more effective execution domain optimization. 127def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 128 "true", "Prefer VMOVSR">; 129 130// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 131// than ISH 132def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 133 "true", "Prefer ISHST barriers">; 134 135// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 136def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true", 137 "Has muxed AGU and NEON/FPU">; 138 139// On some targets, a VLDM/VSTM starting with an odd register number needs more 140// microops than single VLDRS. 141def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 142 "true", "VLDM/VSTM starting with an odd register is slow">; 143 144// Some targets have a renaming dependency when loading into D subregisters. 145def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 146 "SlowLoadDSubregister", "true", 147 "Loading into D subregs is slow">; 148// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 149def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 150 "DontWidenVMOVS", "true", 151 "Don't widen VMOVS to VMOVD">; 152 153// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 154def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true", 155 "Expand VFP/NEON MLA/MLS instructions">; 156 157// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 158def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 159 "true", "Has VMLx hazards">; 160 161// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 162// VFP to NEON, as an execution domain optimization. 163def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs", 164 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">; 165 166// Some processors benefit from using NEON instructions for scalar 167// single-precision FP operations. This affects instruction selection and should 168// only be enabled if the handling of denormals is not important. 169def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 170 "true", 171 "Use NEON for single precision FP">; 172 173// On some processors, VLDn instructions that access unaligned data take one 174// extra cycle. Take that into account when computing operand latencies. 175def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 176 "true", 177 "Check for VLDn unaligned access">; 178 179// Some processors have a nonpipelined VFP coprocessor. 180def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 181 "NonpipelinedVFP", "true", 182 "VFP instructions are not pipelined">; 183 184// Some processors have FP multiply-accumulate instructions that don't 185// play nicely with other VFP / NEON instructions, and it's generally better 186// to just not use them. 187def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 188 "Disable VFP / NEON MAC instructions">; 189 190// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 191def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 192 "HasVMLxForwarding", "true", 193 "Has multiplier accumulator forwarding">; 194 195// Disable 32-bit to 16-bit narrowing for experimentation. 196def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 197 "Prefer 32-bit Thumb instrs">; 198 199/// Some instructions update CPSR partially, which can add false dependency for 200/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 201/// mapped to a separate physical register. Avoid partial CPSR update for these 202/// processors. 203def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 204 "AvoidCPSRPartialUpdate", "true", 205 "Avoid CPSR partial update for OOO execution">; 206 207def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 208 "AvoidMOVsShifterOperand", "true", 209 "Avoid movs instructions with shifter operand">; 210 211// Some processors perform return stack prediction. CodeGen should avoid issue 212// "normal" call instructions to callees which do not return. 213def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true", 214 "Has return address stack">; 215 216/// DSP extension. 217def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 218 "Supports DSP instructions in ARM and/or Thumb2">; 219 220// Multiprocessing extension. 221def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 222 "Supports Multiprocessing extension">; 223 224// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 225def FeatureVirtualization : SubtargetFeature<"virtualization", 226 "HasVirtualization", "true", 227 "Supports Virtualization extension", 228 [FeatureHWDiv, FeatureHWDivARM]>; 229 230// M-series ISA 231def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 232 "Is microcontroller profile ('M' series)">; 233 234// R-series ISA 235def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 236 "Is realtime profile ('R' series)">; 237 238// A-series ISA 239def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 240 "Is application profile ('A' series)">; 241 242// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 243// See ARMInstrInfo.td for details. 244def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 245 "NaCl trap">; 246 247def FeatureStrictAlign : SubtargetFeature<"strict-align", 248 "StrictAlign", "true", 249 "Disallow all unaligned memory " 250 "access">; 251 252def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 253 "Generate calls via indirect call " 254 "instructions">; 255 256def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 257 "Reserve R9, making it unavailable as " 258 "GPR">; 259 260def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 261 "Don't use movt/movw pairs for 32-bit " 262 "imms">; 263 264 265//===----------------------------------------------------------------------===// 266// ARM ISAa. 267// 268 269def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 270 "Support ARM v4T instructions">; 271def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 272 "Support ARM v5T instructions", 273 [HasV4TOps]>; 274def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 275 "Support ARM v5TE, v5TEj, and v5TExp instructions", 276 [HasV5TOps]>; 277def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 278 "Support ARM v6 instructions", 279 [HasV5TEOps]>; 280def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 281 "Support ARM v6M instructions", 282 [HasV6Ops]>; 283def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 284 "Support ARM v8M Baseline instructions", 285 [HasV6MOps]>; 286def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 287 "Support ARM v6k instructions", 288 [HasV6Ops]>; 289def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 290 "Support ARM v6t2 instructions", 291 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 292def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 293 "Support ARM v7 instructions", 294 [HasV6T2Ops, FeaturePerfMon, 295 FeatureV7Clrex]>; 296def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 297 "Support ARM v8 instructions", 298 [HasV7Ops, FeatureAcquireRelease]>; 299def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 300 "Support ARM v8.1a instructions", 301 [HasV8Ops]>; 302def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 303 "Support ARM v8.2a instructions", 304 [HasV8_1aOps]>; 305def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 306 "Support ARM v8M Mainline instructions", 307 [HasV7Ops]>; 308 309 310//===----------------------------------------------------------------------===// 311// ARM Processor subtarget features. 312// 313 314def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 315 "Cortex-A5 ARM processors", []>; 316def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 317 "Cortex-A7 ARM processors", []>; 318def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 319 "Cortex-A8 ARM processors", []>; 320def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 321 "Cortex-A9 ARM processors", []>; 322def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 323 "Cortex-A12 ARM processors", []>; 324def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 325 "Cortex-A15 ARM processors", []>; 326def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 327 "Cortex-A17 ARM processors", []>; 328def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 329 "Cortex-A32 ARM processors", []>; 330def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 331 "Cortex-A35 ARM processors", []>; 332def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 333 "Cortex-A53 ARM processors", []>; 334def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 335 "Cortex-A57 ARM processors", []>; 336def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 337 "Cortex-A72 ARM processors", []>; 338def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 339 "Cortex-A73 ARM processors", []>; 340 341def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 342 "Qualcomm ARM processors", []>; 343def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 344 "Swift ARM processors", []>; 345 346def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 347 "Samsung Exynos-M1 processors", []>; 348 349def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 350 "Cortex-R4 ARM processors", []>; 351def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 352 "Cortex-R5 ARM processors", []>; 353def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 354 "Cortex-R7 ARM processors", []>; 355 356def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 357 "Cortex-M3 ARM processors", []>; 358 359//===----------------------------------------------------------------------===// 360// ARM schedules. 361// 362 363include "ARMSchedule.td" 364 365 366//===----------------------------------------------------------------------===// 367// ARM architectures 368// 369 370def ARMv2 : Architecture<"armv2", "ARMv2", []>; 371 372def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 373 374def ARMv3 : Architecture<"armv3", "ARMv3", []>; 375 376def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 377 378def ARMv4 : Architecture<"armv4", "ARMv4", []>; 379 380def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 381 382def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 383 384def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 385 386def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 387 388def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>; 389 390def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 391 FeatureDSP]>; 392 393def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 394 395def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 396 FeatureTrustZone]>; 397 398def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 399 FeatureNoARM, 400 FeatureDB, 401 FeatureMClass]>; 402 403def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 404 FeatureNoARM, 405 FeatureDB, 406 FeatureMClass]>; 407 408def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 409 FeatureNEON, 410 FeatureDB, 411 FeatureDSP, 412 FeatureAClass]>; 413 414def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 415 FeatureDB, 416 FeatureDSP, 417 FeatureHWDiv, 418 FeatureRClass]>; 419 420def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 421 FeatureThumb2, 422 FeatureNoARM, 423 FeatureDB, 424 FeatureHWDiv, 425 FeatureMClass]>; 426 427def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 428 FeatureThumb2, 429 FeatureNoARM, 430 FeatureDB, 431 FeatureHWDiv, 432 FeatureMClass, 433 FeatureDSP, 434 FeatureT2XtPk]>; 435 436def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 437 FeatureAClass, 438 FeatureDB, 439 FeatureFPARMv8, 440 FeatureNEON, 441 FeatureDSP, 442 FeatureTrustZone, 443 FeatureMP, 444 FeatureVirtualization, 445 FeatureCrypto, 446 FeatureCRC]>; 447 448def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 449 FeatureAClass, 450 FeatureDB, 451 FeatureFPARMv8, 452 FeatureNEON, 453 FeatureDSP, 454 FeatureTrustZone, 455 FeatureMP, 456 FeatureVirtualization, 457 FeatureCrypto, 458 FeatureCRC]>; 459 460def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 461 FeatureAClass, 462 FeatureDB, 463 FeatureFPARMv8, 464 FeatureNEON, 465 FeatureDSP, 466 FeatureTrustZone, 467 FeatureMP, 468 FeatureVirtualization, 469 FeatureCrypto, 470 FeatureCRC, 471 FeatureRAS]>; 472 473def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 474 [HasV8MBaselineOps, 475 FeatureNoARM, 476 FeatureDB, 477 FeatureHWDiv, 478 FeatureV7Clrex, 479 Feature8MSecExt, 480 FeatureAcquireRelease, 481 FeatureMClass]>; 482 483def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 484 [HasV8MMainlineOps, 485 FeatureNoARM, 486 FeatureDB, 487 FeatureHWDiv, 488 Feature8MSecExt, 489 FeatureAcquireRelease, 490 FeatureMClass]>; 491 492// Aliases 493def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 494def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 495def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 496def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 497def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 498def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 499 500 501//===----------------------------------------------------------------------===// 502// ARM processors 503// 504 505// Dummy CPU, used to target architectures 506def : ProcNoItin<"generic", []>; 507 508def : ProcNoItin<"arm8", [ARMv4]>; 509def : ProcNoItin<"arm810", [ARMv4]>; 510def : ProcNoItin<"strongarm", [ARMv4]>; 511def : ProcNoItin<"strongarm110", [ARMv4]>; 512def : ProcNoItin<"strongarm1100", [ARMv4]>; 513def : ProcNoItin<"strongarm1110", [ARMv4]>; 514 515def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 516def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 517def : ProcNoItin<"arm710t", [ARMv4t]>; 518def : ProcNoItin<"arm720t", [ARMv4t]>; 519def : ProcNoItin<"arm9", [ARMv4t]>; 520def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 521def : ProcNoItin<"arm920", [ARMv4t]>; 522def : ProcNoItin<"arm920t", [ARMv4t]>; 523def : ProcNoItin<"arm922t", [ARMv4t]>; 524def : ProcNoItin<"arm940t", [ARMv4t]>; 525def : ProcNoItin<"ep9312", [ARMv4t]>; 526 527def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 528def : ProcNoItin<"arm1020t", [ARMv5t]>; 529 530def : ProcNoItin<"arm9e", [ARMv5te]>; 531def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 532def : ProcNoItin<"arm946e-s", [ARMv5te]>; 533def : ProcNoItin<"arm966e-s", [ARMv5te]>; 534def : ProcNoItin<"arm968e-s", [ARMv5te]>; 535def : ProcNoItin<"arm10e", [ARMv5te]>; 536def : ProcNoItin<"arm1020e", [ARMv5te]>; 537def : ProcNoItin<"arm1022e", [ARMv5te]>; 538def : ProcNoItin<"xscale", [ARMv5te]>; 539def : ProcNoItin<"iwmmxt", [ARMv5te]>; 540 541def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 542def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 543 FeatureVFP2, 544 FeatureHasSlowFPVMLx]>; 545 546def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 547def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 548def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 549def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 550 551def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 552def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 553 FeatureVFP2, 554 FeatureHasSlowFPVMLx]>; 555 556def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 557def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 558 FeatureVFP2, 559 FeatureHasSlowFPVMLx]>; 560 561def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 562def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 563 FeatureVFP2, 564 FeatureHasSlowFPVMLx]>; 565 566// FIXME: A5 has currently the same Schedule model as A8 567def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 568 FeatureHasRetAddrStack, 569 FeatureTrustZone, 570 FeatureSlowFPBrcc, 571 FeatureHasSlowFPVMLx, 572 FeatureVMLxForwarding, 573 FeatureT2XtPk, 574 FeatureMP, 575 FeatureVFP4]>; 576 577def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 578 FeatureHasRetAddrStack, 579 FeatureTrustZone, 580 FeatureSlowFPBrcc, 581 FeatureHasVMLxHazards, 582 FeatureHasSlowFPVMLx, 583 FeatureVMLxForwarding, 584 FeatureT2XtPk, 585 FeatureMP, 586 FeatureVFP4, 587 FeatureHWDiv, 588 FeatureHWDivARM, 589 FeatureVirtualization]>; 590 591def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 592 FeatureHasRetAddrStack, 593 FeatureNonpipelinedVFP, 594 FeatureTrustZone, 595 FeatureSlowFPBrcc, 596 FeatureHasVMLxHazards, 597 FeatureHasSlowFPVMLx, 598 FeatureVMLxForwarding, 599 FeatureT2XtPk]>; 600 601def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 602 FeatureHasRetAddrStack, 603 FeatureTrustZone, 604 FeatureHasVMLxHazards, 605 FeatureVMLxForwarding, 606 FeatureT2XtPk, 607 FeatureFP16, 608 FeatureAvoidPartialCPSR, 609 FeatureExpandMLx, 610 FeaturePreferVMOVSR, 611 FeatureMuxedUnits, 612 FeatureNEONForFPMovs, 613 FeatureCheckVLDnAlign, 614 FeatureMP]>; 615 616// FIXME: A12 has currently the same Schedule model as A9 617def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 618 FeatureHasRetAddrStack, 619 FeatureTrustZone, 620 FeatureVMLxForwarding, 621 FeatureT2XtPk, 622 FeatureVFP4, 623 FeatureHWDiv, 624 FeatureHWDivARM, 625 FeatureAvoidPartialCPSR, 626 FeatureVirtualization, 627 FeatureMP]>; 628 629// FIXME: A15 has currently the same Schedule model as A9. 630def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 631 FeatureDontWidenVMOVS, 632 FeatureHasRetAddrStack, 633 FeatureMuxedUnits, 634 FeatureTrustZone, 635 FeatureT2XtPk, 636 FeatureVFP4, 637 FeatureMP, 638 FeatureCheckVLDnAlign, 639 FeatureHWDiv, 640 FeatureHWDivARM, 641 FeatureAvoidPartialCPSR, 642 FeatureVirtualization]>; 643 644// FIXME: A17 has currently the same Schedule model as A9 645def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 646 FeatureHasRetAddrStack, 647 FeatureTrustZone, 648 FeatureMP, 649 FeatureVMLxForwarding, 650 FeatureT2XtPk, 651 FeatureVFP4, 652 FeatureHWDiv, 653 FeatureHWDivARM, 654 FeatureAvoidPartialCPSR, 655 FeatureVirtualization]>; 656 657// FIXME: krait has currently the same Schedule model as A9 658// FIXME: krait has currently the same features as A9 plus VFP4 and hardware 659// division features. 660def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 661 FeatureHasRetAddrStack, 662 FeatureMuxedUnits, 663 FeatureCheckVLDnAlign, 664 FeatureVMLxForwarding, 665 FeatureT2XtPk, 666 FeatureFP16, 667 FeatureAvoidPartialCPSR, 668 FeatureVFP4, 669 FeatureHWDiv, 670 FeatureHWDivARM]>; 671 672def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 673 FeatureHasRetAddrStack, 674 FeatureNEONForFP, 675 FeatureT2XtPk, 676 FeatureVFP4, 677 FeatureMP, 678 FeatureHWDiv, 679 FeatureHWDivARM, 680 FeatureAvoidPartialCPSR, 681 FeatureAvoidMOVsShOp, 682 FeatureHasSlowFPVMLx, 683 FeatureHasVMLxHazards, 684 FeatureProfUnpredicate, 685 FeaturePrefISHSTBarrier, 686 FeatureSlowOddRegister, 687 FeatureSlowLoadDSubreg, 688 FeatureSlowVGETLNi32, 689 FeatureSlowVDUP32]>; 690 691// FIXME: R4 has currently the same ProcessorModel as A8. 692def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 693 FeatureHasRetAddrStack, 694 FeatureAvoidPartialCPSR, 695 FeatureT2XtPk]>; 696 697// FIXME: R4F has currently the same ProcessorModel as A8. 698def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 699 FeatureHasRetAddrStack, 700 FeatureSlowFPBrcc, 701 FeatureHasSlowFPVMLx, 702 FeatureVFP3, 703 FeatureD16, 704 FeatureAvoidPartialCPSR, 705 FeatureT2XtPk]>; 706 707// FIXME: R5 has currently the same ProcessorModel as A8. 708def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 709 FeatureHasRetAddrStack, 710 FeatureVFP3, 711 FeatureD16, 712 FeatureSlowFPBrcc, 713 FeatureHWDivARM, 714 FeatureHasSlowFPVMLx, 715 FeatureAvoidPartialCPSR, 716 FeatureT2XtPk]>; 717 718// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5. 719def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 720 FeatureHasRetAddrStack, 721 FeatureVFP3, 722 FeatureD16, 723 FeatureFP16, 724 FeatureMP, 725 FeatureSlowFPBrcc, 726 FeatureHWDivARM, 727 FeatureHasSlowFPVMLx, 728 FeatureAvoidPartialCPSR, 729 FeatureT2XtPk]>; 730 731def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 732 FeatureHasRetAddrStack, 733 FeatureVFP3, 734 FeatureD16, 735 FeatureFP16, 736 FeatureMP, 737 FeatureSlowFPBrcc, 738 FeatureHWDivARM, 739 FeatureHasSlowFPVMLx, 740 FeatureAvoidPartialCPSR, 741 FeatureT2XtPk]>; 742 743def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>; 744def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>; 745 746def : ProcNoItin<"cortex-m4", [ARMv7em, 747 FeatureVFP4, 748 FeatureVFPOnlySP, 749 FeatureD16]>; 750 751def : ProcNoItin<"cortex-m7", [ARMv7em, 752 FeatureFPARMv8, 753 FeatureD16]>; 754 755def : ProcNoItin<"cortex-a32", [ARMv8a, 756 FeatureHWDiv, 757 FeatureHWDivARM, 758 FeatureT2XtPk, 759 FeatureCrypto, 760 FeatureCRC]>; 761 762def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 763 FeatureHWDiv, 764 FeatureHWDivARM, 765 FeatureT2XtPk, 766 FeatureCrypto, 767 FeatureCRC]>; 768 769def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 770 FeatureHWDiv, 771 FeatureHWDivARM, 772 FeatureT2XtPk, 773 FeatureCrypto, 774 FeatureCRC]>; 775 776def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57, 777 FeatureHWDiv, 778 FeatureHWDivARM, 779 FeatureT2XtPk, 780 FeatureCrypto, 781 FeatureCRC]>; 782 783def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, 784 FeatureHWDiv, 785 FeatureHWDivARM, 786 FeatureT2XtPk, 787 FeatureCrypto, 788 FeatureCRC]>; 789 790def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 791 FeatureHWDiv, 792 FeatureHWDivARM, 793 FeatureT2XtPk, 794 FeatureCrypto, 795 FeatureCRC]>; 796 797// Cyclone is very similar to swift 798def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 799 FeatureHasRetAddrStack, 800 FeatureNEONForFP, 801 FeatureT2XtPk, 802 FeatureVFP4, 803 FeatureMP, 804 FeatureHWDiv, 805 FeatureHWDivARM, 806 FeatureAvoidPartialCPSR, 807 FeatureAvoidMOVsShOp, 808 FeatureHasSlowFPVMLx, 809 FeatureCrypto, 810 FeatureZCZeroing]>; 811 812def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, 813 FeatureHWDiv, 814 FeatureHWDivARM, 815 FeatureT2XtPk, 816 FeatureCrypto, 817 FeatureCRC]>; 818 819//===----------------------------------------------------------------------===// 820// Register File Description 821//===----------------------------------------------------------------------===// 822 823include "ARMRegisterInfo.td" 824 825include "ARMCallingConv.td" 826 827//===----------------------------------------------------------------------===// 828// Instruction Descriptions 829//===----------------------------------------------------------------------===// 830 831include "ARMInstrInfo.td" 832 833def ARMInstrInfo : InstrInfo; 834 835//===----------------------------------------------------------------------===// 836// Declare the target which we are implementing 837//===----------------------------------------------------------------------===// 838 839def ARMAsmWriter : AsmWriter { 840 string AsmWriterClassName = "InstPrinter"; 841 int PassSubtarget = 1; 842 int Variant = 0; 843 bit isMCAsmWriter = 1; 844} 845 846def ARMAsmParserVariant : AsmParserVariant { 847 int Variant = 0; 848 string Name = "ARM"; 849 string BreakCharacters = "."; 850} 851 852def ARM : Target { 853 // Pull in Instruction Info: 854 let InstructionSet = ARMInstrInfo; 855 let AssemblyWriters = [ARMAsmWriter]; 856 let AssemblyParserVariants = [ARMAsmParserVariant]; 857} 858