1This file is a partial list of people who have contributed to the LLVM 2project. If you have contributed a patch or made some other contribution to 3LLVM, please submit a patch to this file to add yourself, and it will be 4done! 5 6The list is sorted by surname and formatted to allow easy grepping and 7beautification by scripts. The fields are: name (N), email (E), web-address 8(W), PGP key ID and fingerprint (P), description (D), snail-mail address 9(S), and (I) IRC handle. 10 11 12N: Vikram Adve 13E: [email protected] 14W: http://www.cs.uiuc.edu/~vadve/ 15D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM 16 17N: Owen Anderson 18E: [email protected] 19D: LCSSA pass and related LoopUnswitch work 20D: GVNPRE pass, DataLayout refactoring, random improvements 21 22N: Henrik Bach 23D: MingW Win32 API portability layer 24 25N: Aaron Ballman 26E: [email protected] 27D: __declspec attributes, Windows support, general bug fixing 28 29N: Nate Begeman 30E: [email protected] 31D: PowerPC backend developer 32D: Target-independent code generator and analysis improvements 33 34N: Daniel Berlin 35E: [email protected] 36D: ET-Forest implementation. 37D: Sparse bitmap 38 39N: David Blaikie 40E: [email protected] 41D: General bug fixing/fit & finish, mostly in Clang 42 43N: Neil Booth 44E: [email protected] 45D: APFloat implementation. 46 47N: Misha Brukman 48E: [email protected] 49W: http://misha.brukman.net 50D: Portions of X86 and Sparc JIT compilers, PowerPC backend 51D: Incremental bitcode loader 52 53N: Cameron Buschardt 54E: [email protected] 55D: The `mem2reg' pass - promotes values stored in memory to registers 56 57N: Brendon Cahoon 58E: [email protected] 59D: Loop unrolling with run-time trip counts. 60 61N: Chandler Carruth 62E: [email protected] 63E: [email protected] 64D: Hashing algorithms and interfaces 65D: Inline cost analysis 66D: Machine block placement pass 67D: SROA 68 69N: Casey Carter 70E: [email protected] 71D: Fixes to the Reassociation pass, various improvement patches 72 73N: Evan Cheng 74E: [email protected] 75D: ARM and X86 backends 76D: Instruction scheduler improvements 77D: Register allocator improvements 78D: Loop optimizer improvements 79D: Target-independent code generator improvements 80 81N: Dan Villiom Podlaski Christiansen 82E: [email protected] 83E: [email protected] 84W: http://villiom.dk 85D: LLVM Makefile improvements 86D: Clang diagnostic & driver tweaks 87S: Aarhus, Denmark 88 89N: Jeff Cohen 90E: [email protected] 91W: http://jolt-lang.org 92D: Native Win32 API portability layer 93 94N: John T. Criswell 95E: [email protected] 96D: Original Autoconf support, documentation improvements, bug fixes 97 98N: Anshuman Dasgupta 99E: [email protected] 100D: Deterministic finite automaton based infrastructure for VLIW packetization 101 102N: Stefanus Du Toit 103E: [email protected] 104D: Bug fixes and minor improvements 105 106N: Rafael Avila de Espindola 107E: [email protected] 108D: The ARM backend 109 110N: Dave Estes 111E: [email protected] 112D: AArch64 machine description for Cortex-A53 113 114N: Alkis Evlogimenos 115E: [email protected] 116D: Linear scan register allocator, many codegen improvements, Java frontend 117 118N: Hal Finkel 119E: [email protected] 120D: Basic-block autovectorization, PowerPC backend improvements 121 122N: Eric Fiselier 123E: [email protected] 124D: LIT patches and documentation. 125 126N: Ryan Flynn 127E: [email protected] 128D: Miscellaneous bug fixes 129 130N: Brian Gaeke 131E: [email protected] 132W: http://www.students.uiuc.edu/~gaeke/ 133D: Portions of X86 static and JIT compilers; initial SparcV8 backend 134D: Dynamic trace optimizer 135D: FreeBSD/X86 compatibility fixes, the llvm-nm tool 136 137N: Nicolas Geoffray 138E: [email protected] 139W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/ 140D: PPC backend fixes for Linux 141 142N: Louis Gerbarg 143E: [email protected] 144D: Portions of the PowerPC backend 145 146N: Saem Ghani 147E: [email protected] 148D: Callgraph class cleanups 149 150N: Mikhail Glushenkov 151E: [email protected] 152D: Author of llvmc2 153 154N: Dan Gohman 155E: [email protected] 156D: Miscellaneous bug fixes 157D: WebAssembly Backend 158 159N: David Goodwin 160E: [email protected] 161D: Thumb-2 code generator 162 163N: David Greene 164E: [email protected] 165D: Miscellaneous bug fixes 166D: Register allocation refactoring 167 168N: Gabor Greif 169E: [email protected] 170D: Improvements for space efficiency 171 172N: James Grosbach 173E: [email protected] 174I: grosbach 175D: SjLj exception handling support 176D: General fixes and improvements for the ARM back-end 177D: MCJIT 178D: ARM integrated assembler and assembly parser 179D: Led effort for the backend formerly known as ARM64 180 181N: Lang Hames 182E: [email protected] 183D: PBQP-based register allocator 184 185N: Gordon Henriksen 186E: [email protected] 187D: Pluggable GC support 188D: C interface 189D: Ocaml bindings 190 191N: Raul Fernandes Herbster 192E: [email protected] 193D: JIT support for ARM 194 195N: Paolo Invernizzi 196E: [email protected] 197D: Visual C++ compatibility fixes 198 199N: Patrick Jenkins 200E: [email protected] 201D: Nightly Tester 202 203N: Dale Johannesen 204E: [email protected] 205D: ARM constant islands improvements 206D: Tail merging improvements 207D: Rewrite X87 back end 208D: Use APFloat for floating point constants widely throughout compiler 209D: Implement X87 long double 210 211N: Brad Jones 212E: [email protected] 213D: Support for packed types 214 215N: Rod Kay 216E: [email protected] 217D: Author of LLVM Ada bindings 218 219N: Eric Kidd 220W: http://randomhacks.net/ 221D: llvm-config script 222 223N: Anton Korobeynikov 224E: [email protected] 225D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv. 226D: x86/linux PIC codegen, aliases, regparm/visibility attributes 227D: Switch lowering refactoring 228 229N: Sumant Kowshik 230E: [email protected] 231D: Author of the original C backend 232 233N: Benjamin Kramer 234E: [email protected] 235D: Miscellaneous bug fixes 236 237N: Sundeep Kushwaha 238E: [email protected] 239D: Implemented DFA-based target independent VLIW packetizer 240 241N: Christopher Lamb 242E: [email protected] 243D: aligned load/store support, parts of noalias and restrict support 244D: vreg subreg infrastructure, X86 codegen improvements based on subregs 245D: address spaces 246 247N: Jim Laskey 248E: [email protected] 249D: Improvements to the PPC backend, instruction scheduling 250D: Debug and Dwarf implementation 251D: Auto upgrade mangler 252D: llvm-gcc4 svn wrangler 253 254N: Chris Lattner 255E: [email protected] 256W: http://nondot.org/~sabre/ 257D: Primary architect of LLVM 258 259N: Tanya Lattner (Tanya Brethour) 260E: [email protected] 261W: http://nondot.org/~tonic/ 262D: The initial llvm-ar tool, converted regression testsuite to dejagnu 263D: Modulo scheduling in the SparcV9 backend 264D: Release manager (1.7+) 265 266N: Sylvestre Ledru 267E: [email protected] 268W: http://sylvestre.ledru.info/ 269W: http://llvm.org/apt/ 270D: Debian and Ubuntu packaging 271D: Continuous integration with jenkins 272 273N: Andrew Lenharth 274E: [email protected] 275W: http://www.lenharth.org/~andrewl/ 276D: Alpha backend 277D: Sampling based profiling 278 279N: Nick Lewycky 280E: [email protected] 281D: PredicateSimplifier pass 282 283N: Tony Linthicum, et. al. 284E: [email protected] 285D: Backend for Qualcomm's Hexagon VLIW processor. 286 287N: Bruno Cardoso Lopes 288E: [email protected] 289I: bruno 290W: http://brunocardoso.cc 291D: Mips backend 292D: Random ARM integrated assembler and assembly parser improvements 293D: General X86 AVX1 support 294 295N: Duraid Madina 296E: [email protected] 297W: http://kinoko.c.u-tokyo.ac.jp/~duraid/ 298D: IA64 backend, BigBlock register allocator 299 300N: John McCall 301E: [email protected] 302D: Clang semantic analysis and IR generation 303 304N: Michael McCracken 305E: [email protected] 306D: Line number support for llvmgcc 307 308N: Vladimir Merzliakov 309E: [email protected] 310D: Test suite fixes for FreeBSD 311 312N: Scott Michel 313E: [email protected] 314D: Added STI Cell SPU backend. 315 316N: Kai Nacke 317E: [email protected] 318D: Support for implicit TLS model used with MS VC runtime 319D: Dumping of Win64 EH structures 320 321N: Takumi Nakamura 322E: [email protected] 323E: [email protected] 324D: Cygwin and MinGW support. 325D: Win32 tweaks. 326S: Yokohama, Japan 327 328N: Edward O'Callaghan 329E: [email protected] 330W: http://www.auroraux.org 331D: Add Clang support with various other improvements to utils/NewNightlyTest.pl 332D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings 333D: and error clean ups. 334 335N: Morten Ofstad 336E: [email protected] 337D: Visual C++ compatibility fixes 338 339N: Jakob Stoklund Olesen 340E: [email protected] 341D: Machine code verifier 342D: Blackfin backend 343D: Fast register allocator 344D: Greedy register allocator 345 346N: Richard Osborne 347E: [email protected] 348D: XCore backend 349 350N: Piotr Padlewski 351E: [email protected] 352D: !invariant.group metadata and other intrinsics for devirtualization in clang 353 354N: Devang Patel 355E: [email protected] 356D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate 357D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements 358D: Optimizer improvements, Loop Index Split 359 360N: Ana Pazos 361E: [email protected] 362D: Fixes and improvements to the AArch64 backend 363 364N: Wesley Peck 365E: [email protected] 366W: http://wesleypeck.com/ 367D: MicroBlaze backend 368 369N: Francois Pichet 370E: [email protected] 371D: MSVC support 372 373N: Vladimir Prus 374W: http://vladimir_prus.blogspot.com 375E: [email protected] 376D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass 377 378N: Kalle Raiskila 379E: [email protected] 380D: Some bugfixes to CellSPU 381 382N: Xerxes Ranby 383E: [email protected] 384D: Cmake dependency chain and various bug fixes 385 386N: Alex Rosenberg 387E: [email protected] 388I: arosenberg 389D: ARM calling conventions rewrite, hard float support 390 391N: Chad Rosier 392E: [email protected] 393I: mcrosier 394D: AArch64 fast instruction selection pass 395D: Fixes and improvements to the ARM fast-isel pass 396D: Fixes and improvements to the AArch64 backend 397 398N: Nadav Rotem 399E: [email protected] 400D: X86 code generation improvements, Loop Vectorizer. 401 402N: Roman Samoilov 403E: [email protected] 404D: MSIL backend 405 406N: Duncan Sands 407E: [email protected] 408I: baldrick 409D: Ada support in llvm-gcc 410D: Dragonegg plugin 411D: Exception handling improvements 412D: Type legalizer rewrite 413 414N: Ruchira Sasanka 415E: [email protected] 416D: Graph coloring register allocator for the Sparc64 backend 417 418N: Arnold Schwaighofer 419E: [email protected] 420D: Tail call optimization for the x86 backend 421 422N: Shantonu Sen 423E: [email protected] 424D: Miscellaneous bug fixes 425 426N: Anand Shukla 427E: [email protected] 428D: The `paths' pass 429 430N: Michael J. Spencer 431E: [email protected] 432D: Shepherding Windows COFF support into MC. 433D: Lots of Windows stuff. 434 435N: Reid Spencer 436E: [email protected] 437W: http://reidspencer.com/ 438D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid 439 440N: Alp Toker 441E: [email protected] 442W: http://atoker.com/ 443D: C++ frontend next generation standards implementation 444 445N: Craig Topper 446E: [email protected] 447D: X86 codegen and disassembler improvements. AVX2 support. 448 449N: Edwin Torok 450E: [email protected] 451D: Miscellaneous bug fixes 452 453N: Adam Treat 454E: [email protected] 455D: C++ bugs filed, and C++ front-end bug fixes. 456 457N: Lauro Ramos Venancio 458E: [email protected] 459D: ARM backend improvements 460D: Thread Local Storage implementation 461 462N: Bill Wendling 463I: wendling 464E: [email protected] 465D: Release manager, IR Linker, LTO 466D: Bunches of stuff 467 468N: Bob Wilson 469E: [email protected] 470D: Advanced SIMD (NEON) support in the ARM backend. 471 472