1 /******************************************************************************
2 * *
3 * Copyright (C) 2018 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 #include "ixheaac_type_def.h"
21 #include "ixheaac_constants.h"
22 #include "ixheaac_error_standards.h"
23
24 #include "ixheaacd_bitbuffer.h"
25 #include "ixheaacd_config.h"
26
27 #include <assert.h>
28
29 #ifndef sign
30 #define sign(a) (((a) > 0) ? 1 : ((a) < 0) ? -1 : 0)
31 #endif
32
33 typedef struct {
34 WORD32 num_input_chan;
35 WORD32 num_output_chan;
36 WORD32 num_ott_boxes;
37 WORD32 num_ttt_boxes;
38 WORD32 ott_mode_lfe[MAX_NUM_OTT];
39 } ia_ld_mps_dec_tree_properties_struct;
40
41 static WORD32 ixheaacd_freq_res_table[] = {0, 23, 15, 12, 9, 7, 5, 4};
42
43 static WORD32 ixheaacd_hrtf_freq_res_table[][8] = {{0, 28, 20, 14, 10, 7, 5, 4},
44 {0, 13, 13, 8, 7, 4, 3, 3}};
45
46 static ia_ld_mps_dec_tree_properties_struct ixheaacd_tree_property_table[] = {
47 {1, 6, 5, 0, {0, 0, 0, 0, 1}}, {1, 6, 5, 0, {0, 0, 1, 0, 0}}, {2, 6, 3, 1, {1, 0, 0, 0, 0}},
48 {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {6, 8, 2, 0, {0, 0, 0, 0, 0}},
49 {6, 8, 2, 0, {0, 0, 0, 0, 0}}, {1, 2, 1, 0, {0, 0, 0, 0, 0}}};
50
ixheaacd_ld_spatial_extension_config(ia_bit_buf_struct * it_bit_buff,ia_usac_dec_mps_config_struct * config,WORD32 bits_available)51 static IA_ERRORCODE ixheaacd_ld_spatial_extension_config(
52 ia_bit_buf_struct *it_bit_buff, ia_usac_dec_mps_config_struct *config,
53 WORD32 bits_available) {
54 WORD32 j, ch, idx, tmp, tmp_open, sac_ext_len, bits_read, n_fill_bits;
55 UWORD32 i;
56 WORD32 ba = bits_available;
57
58 config->sac_ext_cnt = 0;
59
60 tmp = it_bit_buff->cnt_bits;
61
62 while (ba >= 8) {
63 if (config->sac_ext_cnt >= MAX_NUM_EXT_TYPES) return IA_FATAL_ERROR;
64
65 config->bs_sac_ext_type[config->sac_ext_cnt] =
66 ixheaacd_read_bits_buf(it_bit_buff, 4);
67 ba -= 4;
68
69 sac_ext_len = ixheaacd_read_bits_buf(it_bit_buff, 4);
70 ba -= 4;
71
72 if ((ba >= 6) && (sac_ext_len > 0)) {
73 if (sac_ext_len == 15) {
74 sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 8);
75 ba -= 8;
76 if (sac_ext_len == 15 + 255) {
77 sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 16);
78 ba -= 16;
79 }
80 }
81
82 switch (config->bs_sac_ext_type[config->sac_ext_cnt]) {
83 case 0:
84 config->bs_residual_coding = 1;
85
86 config->bs_residual_sampling_freq_index =
87 ixheaacd_read_bits_buf(it_bit_buff, 4);
88 if (config->bs_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
89 return IA_FATAL_ERROR;
90 }
91 config->bs_residual_frames_per_spatial_frame =
92 ixheaacd_read_bits_buf(it_bit_buff, 2);
93
94 if ((config->num_ott_boxes + config->num_ttt_boxes) >
95 MAX_RESIDUAL_CHANNELS)
96 return IA_FATAL_ERROR;
97 for (j = 0; j < config->num_ott_boxes + config->num_ttt_boxes; j++) {
98 config->bs_residual_present[j] =
99 ixheaacd_read_bits_buf(it_bit_buff, 1);
100 if (config->bs_residual_present[j]) {
101 config->bs_residual_bands_ld_mps[j] =
102 ixheaacd_read_bits_buf(it_bit_buff, 5);
103 if (config->bs_residual_bands_ld_mps[j] > MAX_PARAMETER_BANDS)
104 {
105 return IA_FATAL_ERROR;
106 }
107 }
108 }
109 break;
110
111 case 1:
112 config->bs_arbitrary_downmix = 2;
113
114 config->bs_arbitrary_downmix_residual_sampling_freq_index =
115 ixheaacd_read_bits_buf(it_bit_buff, 4);
116 if (config->bs_arbitrary_downmix_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
117 return IA_FATAL_ERROR;
118 }
119 config->bs_arbitrary_downmix_residual_frames_per_spatial_frame =
120 ixheaacd_read_bits_buf(it_bit_buff, 2);
121 config->bs_arbitrary_downmix_residual_bands =
122 ixheaacd_read_bits_buf(it_bit_buff, 5);
123 if (config->bs_arbitrary_downmix_residual_bands >=
124 ixheaacd_freq_res_table[config->bs_freq_res]) {
125 return IA_FATAL_ERROR;
126 }
127
128 break;
129
130 case 2:
131 config->num_out_chan_AT = 0;
132 config->num_ott_boxes_AT = 0;
133 if (config->num_output_channels > MAX_OUTPUT_CHANNELS)
134 return IA_FATAL_ERROR;
135 for (ch = 0; ch < config->num_output_channels; ch++) {
136 tmp_open = 1;
137 idx = 0;
138 while ((tmp_open > 0) && (idx < MAX_ARBITRARY_TREE_INDEX)) {
139 config->bs_ott_box_present_AT[ch][idx] =
140 ixheaacd_read_bits_buf(it_bit_buff, 1);
141 if (config->bs_ott_box_present_AT[ch][idx]) {
142 config->num_ott_boxes_AT++;
143 tmp_open++;
144 } else {
145 config->num_out_chan_AT++;
146 tmp_open--;
147 }
148 idx++;
149 }
150 }
151
152 for (i = 0; i < config->num_ott_boxes_AT; i++) {
153 config->bs_ott_default_cld_AT[i] =
154 ixheaacd_read_bits_buf(it_bit_buff, 1);
155 config->bs_ott_mode_lfe_AT[i] =
156 ixheaacd_read_bits_buf(it_bit_buff, 1);
157 if (config->bs_ott_mode_lfe_AT[i]) {
158 config->bs_ott_bands_AT[i] =
159 ixheaacd_read_bits_buf(it_bit_buff, 5);
160 } else {
161 config->bs_ott_bands_AT[i] = ixheaacd_freq_res_table[config->bs_freq_res];
162 }
163 }
164
165 for (i = 0; i < config->num_out_chan_AT; i++) {
166 config->bs_output_channel_pos_AT[i] =
167 ixheaacd_read_bits_buf(it_bit_buff, 5);
168 }
169
170 break;
171
172 default:;
173 }
174 }
175
176 bits_read = tmp - it_bit_buff->cnt_bits;
177 n_fill_bits = 8 * sac_ext_len - bits_read;
178
179 while (n_fill_bits > 7) {
180 ixheaacd_read_bits_buf(it_bit_buff, 8);
181 n_fill_bits -= 8;
182 }
183 if (n_fill_bits > 0) {
184 ixheaacd_read_bits_buf(it_bit_buff, n_fill_bits);
185 }
186
187 ba -= 8 * sac_ext_len;
188 config->sac_ext_cnt++;
189 }
190 return IA_NO_ERROR;
191 }
192
ixheaacd_ld_spatial_specific_config(ia_usac_dec_mps_config_struct * config,ia_bit_buf_struct * it_bit_buff)193 IA_ERRORCODE ixheaacd_ld_spatial_specific_config(
194 ia_usac_dec_mps_config_struct *config, ia_bit_buf_struct *it_bit_buff) {
195 WORD32 i, num_header_bits;
196 UWORD32 hc, hb;
197 WORD32 sac_header_len;
198 WORD32 bits_available;
199 WORD32 tmp = it_bit_buff->cnt_bits;
200 WORD32 err = 0;
201
202 sac_header_len = tmp;
203
204 bits_available = sac_header_len;
205 config->bs_sampling_freq_index = ixheaacd_read_bits_buf(it_bit_buff, 4);
206 if (config->bs_sampling_freq_index == 15) {
207 config->bs_fampling_frequency = ixheaacd_read_bits_buf(it_bit_buff, 24);
208 }
209
210 config->bs_frame_length = ixheaacd_read_bits_buf(it_bit_buff, 5);
211 config->bs_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
212 config->bs_tree_config = ixheaacd_read_bits_buf(it_bit_buff, 4);
213
214 if (config->bs_tree_config > 7) return IA_FATAL_ERROR;
215
216 if (config->bs_tree_config != 15) {
217 config->num_ott_boxes =
218 ixheaacd_tree_property_table[config->bs_tree_config].num_ott_boxes;
219 config->num_ttt_boxes =
220 ixheaacd_tree_property_table[config->bs_tree_config].num_ttt_boxes;
221 config->num_input_channels =
222 ixheaacd_tree_property_table[config->bs_tree_config].num_input_chan;
223 config->num_output_channels =
224 ixheaacd_tree_property_table[config->bs_tree_config].num_output_chan;
225 for (i = 0; i < MAX_NUM_OTT; i++) {
226 config->ott_mode_lfe[i] =
227 ixheaacd_tree_property_table[config->bs_tree_config].ott_mode_lfe[i];
228 }
229 }
230 config->bs_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 2);
231 if (config->bs_tree_config != 7) {
232 config->bs_one_icc = ixheaacd_read_bits_buf(it_bit_buff, 1);
233 }
234 config->bs_arbitrary_downmix = ixheaacd_read_bits_buf(it_bit_buff, 1);
235 if (config->bs_tree_config != 7) {
236 config->bs_fixed_gain_sur = ixheaacd_read_bits_buf(it_bit_buff, 3);
237 config->bs_fixed_gain_LFE = ixheaacd_read_bits_buf(it_bit_buff, 3);
238 }
239 config->bs_fixed_gain_dmx = ixheaacd_read_bits_buf(it_bit_buff, 3);
240 if (config->bs_tree_config != 7) {
241 config->bs_matrix_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
242 }
243 config->bs_temp_shape_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
244 config->bs_decorr_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
245 if (config->bs_tree_config != 7) {
246 config->bs_3D_audio_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
247 } else {
248 config->bs_3D_audio_mode = 0;
249 }
250
251 // ott_config
252 for (i = 0; i < config->num_ott_boxes; i++) {
253 if (config->ott_mode_lfe[i]) {
254 config->bs_ott_bands[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
255 } else {
256 config->bs_ott_bands[i] = ixheaacd_freq_res_table[config->bs_freq_res];
257 }
258 }
259
260 // ttt_config
261 for (i = 0; i < config->num_ttt_boxes; i++) {
262 config->bs_ttt_dual_mode[i] = ixheaacd_read_bits_buf(it_bit_buff, 1);
263 config->bs_ttt_mode_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
264 if (config->bs_ttt_dual_mode[i]) {
265 config->bs_ttt_mode_high[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
266 config->bs_ttt_bands_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
267 config->bs_ttt_bands_high[i] = ixheaacd_freq_res_table[config->bs_freq_res];
268 } else {
269 config->bs_ttt_bands_low[i] = ixheaacd_freq_res_table[config->bs_freq_res];
270 }
271 }
272
273 if (config->bs_temp_shape_config == 2) {
274 config->bs_env_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
275 }
276
277 if (config->bs_3D_audio_mode) {
278 config->bs_3D_audio_HRTF_set = ixheaacd_read_bits_buf(it_bit_buff, 2);
279 // param_HRTF_set
280 if (config->bs_3D_audio_HRTF_set == 0) {
281 config->bs_HRTF_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
282 config->bs_HRTF_num_chan = 5;
283 config->bs_HRTF_asymmetric = ixheaacd_read_bits_buf(it_bit_buff, 1);
284
285 config->HRTF_num_band = ixheaacd_hrtf_freq_res_table[0][config->bs_HRTF_freq_res];
286 config->HRTF_num_phase = ixheaacd_hrtf_freq_res_table[1][config->bs_HRTF_freq_res];
287
288 for (hc = 0; hc < config->bs_HRTF_num_chan; hc++) {
289 for (hb = 0; hb < config->HRTF_num_band; hb++) {
290 config->bs_HRTF_level_left[hc][hb] =
291 ixheaacd_read_bits_buf(it_bit_buff, 6);
292 }
293 for (hb = 0; hb < config->HRTF_num_band; hb++) {
294 config->bs_HRTF_level_right[hc][hb] =
295 config->bs_HRTF_asymmetric
296 ? ixheaacd_read_bits_buf(it_bit_buff, 6)
297 : config->bs_HRTF_level_left[hc][hb];
298 }
299 config->bs_HRTF_phase[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
300 for (hb = 0; hb < config->HRTF_num_phase; hb++) {
301 config->bs_HRTF_phase_LR[hc][hb] =
302 config->bs_HRTF_phase[hc] ? ixheaacd_read_bits_buf(it_bit_buff, 6)
303 : 0;
304 }
305 config->bs_HRTF_icc[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
306 if (config->bs_HRTF_icc[hc]) {
307 for (hb = 0; hb < config->HRTF_num_band; hb++)
308 config->bs_HRTF_icc_LR[hc][hb] =
309 ixheaacd_read_bits_buf(it_bit_buff, 3);
310 }
311 }
312 }
313 }
314
315 // byte_align
316 i = (it_bit_buff->cnt_bits & 0x7);
317 ixheaacd_read_bits_buf(it_bit_buff, i);
318
319 num_header_bits = tmp - (it_bit_buff->cnt_bits);
320 bits_available -= num_header_bits;
321
322 err =
323 ixheaacd_ld_spatial_extension_config(it_bit_buff, config, bits_available);
324 return err;
325 }
326