1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71 #include "impeg2d_deinterlace.h"
72
73 #define NUM_FRAMES_LIMIT_ENABLED 0
74
75 #ifdef LOGO_EN
76 #include "impeg2_ittiam_logo.h"
77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
78 #else
79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
80 #endif
81
82 #if NUM_FRAMES_LIMIT_ENABLED
83 #define NUM_FRAMES_LIMIT 10000
84 #else
85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
86 #endif
87
88 #define CODEC_NAME "MPEG2VDEC"
89 #define CODEC_RELEASE_TYPE "eval"
90 #define CODEC_RELEASE_VER "01.00"
91 #define CODEC_VENDOR "ITTIAM"
92
93 #ifdef ANDROID
94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
95 strcpy(version_string,"@(#)Id:"); \
96 strcat(version_string,codec_name); \
97 strcat(version_string,"_"); \
98 strcat(version_string,codec_release_type); \
99 strcat(version_string," Ver:"); \
100 strcat(version_string,codec_release_ver); \
101 strcat(version_string," Released by "); \
102 strcat(version_string,codec_vendor);
103 #else
104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
105 strcpy(version_string,"@(#)Id:"); \
106 strcat(version_string,codec_name); \
107 strcat(version_string,"_"); \
108 strcat(version_string,codec_release_type); \
109 strcat(version_string," Ver:"); \
110 strcat(version_string,codec_release_ver); \
111 strcat(version_string," Released by "); \
112 strcat(version_string,codec_vendor); \
113 strcat(version_string," Build: "); \
114 strcat(version_string,__DATE__); \
115 strcat(version_string," @ "); \
116 strcat(version_string,__TIME__);
117 #endif
118
119
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125
126 void impeg2d_init_arch(void *pv_codec);
127 void impeg2d_init_function_ptr(void *pv_codec);
128 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size);
129
130 /*****************************************************************************/
131 /* */
132 /* Function Name : impeg2d_api_rel_display_frame */
133 /* */
134 /* Description : Release displ buffers that will be shared between decoder */
135 /* and application */
136 /* Inputs : Error message */
137 /* Globals : None */
138 /* Processing : Just prints error message to console */
139 /* Outputs : Error mesage to the console */
140 /* Returns : None */
141 /* */
142 /* Issues : <List any issues or problems with this function> */
143 /* */
144 /* Revision History: */
145 /* */
146 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
147 /* 27 05 2006 Sankar Creation */
148 /* */
149 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)150 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
151 void *pv_api_ip,
152 void *pv_api_op)
153 {
154
155 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
156 ivd_rel_display_frame_op_t *dec_rel_disp_op;
157
158 dec_state_t *ps_dec_state;
159 dec_state_multi_core_t *ps_dec_state_multi_core;
160
161
162 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
163 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
164
165 dec_rel_disp_op->u4_error_code = 0;
166 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
167 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
168
169
170 /* If not in shared disp buf mode, return */
171 if(0 == ps_dec_state->u4_share_disp_buf)
172 return IV_SUCCESS;
173
174 if(NULL == ps_dec_state->pv_pic_buf_mg)
175 return IV_SUCCESS;
176
177
178 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
179
180 return IV_SUCCESS;
181 }
182
183 /*****************************************************************************/
184 /* */
185 /* Function Name : impeg2d_api_set_display_frame */
186 /* */
187 /* Description : Sets display buffers that will be shared between decoder */
188 /* and application */
189 /* Inputs : Error message */
190 /* Globals : None */
191 /* Processing : Just prints error message to console */
192 /* Outputs : Error mesage to the console */
193 /* Returns : None */
194 /* */
195 /* Issues : <List any issues or problems with this function> */
196 /* */
197 /* Revision History: */
198 /* */
199 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
200 /* 27 05 2006 Sankar Creation */
201 /* */
202 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)203 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
204 void *pv_api_ip,
205 void *pv_api_op)
206 {
207
208 ivd_set_display_frame_ip_t *dec_disp_ip;
209 ivd_set_display_frame_op_t *dec_disp_op;
210
211 UWORD32 i;
212 dec_state_t *ps_dec_state;
213 dec_state_multi_core_t *ps_dec_state_multi_core;
214 UWORD32 u4_num_disp_bufs;
215 UWORD32 u4_disp_buf_size[3];
216 UWORD32 num_bufs;
217
218
219 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
220 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
221 dec_disp_op->u4_error_code = 0;
222
223 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
224 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
225 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
226
227 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
228 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
229
230 num_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
231
232 if(ps_dec_state->u4_share_disp_buf)
233 {
234 pic_buf_t *ps_pic_buf;
235 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
236
237 /* Get the sizes of the first buffer structure. Compare this with the
238 * rest to make sure all the buffers are of the same size.
239 */
240 u4_disp_buf_size[0] =
241 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
242 u4_disp_buf_size[1] =
243 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
244 u4_disp_buf_size[2] =
245 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
246 for(i = 0; i < u4_num_disp_bufs; i++)
247 {
248 /* Verify all buffer structures have the same sized buffers as the
249 * first buffer structure*/
250 if ((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
251 != u4_disp_buf_size[0])
252 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
253 != u4_disp_buf_size[1])
254 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
255 != u4_disp_buf_size[2]))
256 {
257 return IV_FAIL;
258 }
259 /* Verify all buffer structures have the same number of
260 * buffers (e.g. y, u, v) */
261 if (dec_disp_ip->s_disp_buffer[i].u4_num_bufs != num_bufs)
262 {
263 return IV_FAIL;
264 }
265
266 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
267 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
268 {
269 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
270 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
271 }
272 else
273 {
274 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
275 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
276 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
277 }
278
279 ps_pic_buf->i4_buf_id = i;
280
281 ps_pic_buf->u1_used_as_ref = 0;
282
283 ps_pic_buf->u4_ts = 0;
284
285 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
286 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
287 ps_pic_buf++;
288
289 }
290 }
291 memcpy(&(ps_dec_state->as_disp_buffers[0]),
292 &(dec_disp_ip->s_disp_buffer),
293 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
294
295 return IV_SUCCESS;
296
297 }
298
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)299 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
300 void *pv_api_ip,
301 void *pv_api_op)
302 {
303 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
304 impeg2d_ctl_set_num_cores_op_t *ps_op;
305 dec_state_t *ps_dec_state;
306 dec_state_multi_core_t *ps_dec_state_multi_core;
307
308 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
309 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
310
311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
312 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
313
314 if(ps_ip->u4_num_cores > 0)
315 {
316
317
318 WORD32 i;
319 for(i = 0; i < MAX_THREADS; i++)
320 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
321 }
322 else
323 {
324 ps_dec_state->i4_num_cores = 1;
325 }
326 ps_op->u4_error_code = IV_SUCCESS;
327
328 return IV_SUCCESS;
329 }
330
impeg2d_api_get_seq_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)331 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl,
332 void *pv_api_ip,
333 void *pv_api_op)
334 {
335 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
336 impeg2d_ctl_get_seq_info_op_t *ps_op;
337 dec_state_t *ps_codec;
338 dec_state_multi_core_t *ps_dec_state_multi_core;
339
340 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
341 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
342
343 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
344 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
345 UNUSED(ps_ip);
346 if(ps_codec->u2_header_done == 1)
347 {
348 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info;
349 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code;
350 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n;
351 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d;
352 if(ps_codec->u1_seq_disp_extn_present == 1)
353 {
354 ps_op->u1_video_format = ps_codec->u1_video_format;
355 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries;
356 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics;
357 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients;
358 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size;
359 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size;
360 }
361 else
362 {
363 ps_op->u1_video_format = 5;
364 ps_op->u1_colour_primaries = 2;
365 ps_op->u1_transfer_characteristics = 2;
366 ps_op->u1_matrix_coefficients = 2;
367 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size;
368 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size;
369 }
370 ps_op->u4_error_code = IV_SUCCESS;
371 return IV_SUCCESS;
372 }
373 else
374 {
375 ps_op->u4_error_code = IV_FAIL;
376 return IV_FAIL;
377 }
378 }
379
380 /**
381 *******************************************************************************
382 *
383 * @brief
384 * Sets Processor type
385 *
386 * @par Description:
387 * Sets Processor type
388 *
389 * @param[in] ps_codec_obj
390 * Pointer to codec object at API level
391 *
392 * @param[in] pv_api_ip
393 * Pointer to input argument structure
394 *
395 * @param[out] pv_api_op
396 * Pointer to output argument structure
397 *
398 * @returns Status
399 *
400 * @remarks
401 *
402 *
403 *******************************************************************************
404 */
405
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)406 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
407 void *pv_api_ip,
408 void *pv_api_op)
409 {
410 impeg2d_ctl_set_processor_ip_t *ps_ip;
411 impeg2d_ctl_set_processor_op_t *ps_op;
412 dec_state_t *ps_codec;
413 dec_state_multi_core_t *ps_dec_state_multi_core;
414
415 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
416 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
417
418 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
419 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
420
421 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
422 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
423
424 impeg2d_init_function_ptr(ps_codec);
425
426
427 ps_op->u4_error_code = 0;
428 return IV_SUCCESS;
429 }
430 /*****************************************************************************/
431 /* */
432 /* Function Name : impeg2d_fill_mem_rec */
433 /* */
434 /* Description : */
435 /* Inputs : */
436 /* Globals : */
437 /* Processing : */
438 /* Outputs : */
439 /* Returns : */
440 /* */
441 /* Issues : */
442 /* */
443 /* Revision History: */
444 /* */
445 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
446 /* 17 09 2007 Rajendra C Y Draft */
447 /* */
448 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)449 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
450 impeg2d_fill_mem_rec_op_t *ps_op)
451 {
452 UWORD32 u4_i;
453
454 UWORD8 u1_no_rec = 0;
455 UWORD32 max_frm_width,max_frm_height,max_frm_size;
456 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
457 WORD32 i4_num_threads;
458 WORD32 i4_share_disp_buf, i4_chroma_format;
459 WORD32 i4_chroma_size;
460 UWORD32 u4_deinterlace;
461 UNUSED(u4_deinterlace);
462 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
463 /* In error clips with field prediction, the mv may incorrectly refer to
464 * the last MB row, causing an out of bounds read access. Allocating 8 extra
465 * rows to handle this. Adding another extra row to handle half_y prediction.
466 */
467 max_frm_height = ALIGN32(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht) + 9;
468
469 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
470
471 i4_chroma_size = max_frm_width * max_frm_height / 4;
472
473 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
474 {
475 #ifndef LOGO_EN
476 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
477 #else
478 i4_share_disp_buf = 0;
479 #endif
480 }
481 else
482 {
483 i4_share_disp_buf = 0;
484 }
485 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
486 {
487 i4_chroma_format = ps_ip->e_output_format;
488 }
489 else
490 {
491 i4_chroma_format = -1;
492 }
493
494 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace))
495 {
496 u4_deinterlace = ps_ip->u4_deinterlace;
497 }
498 else
499 {
500 u4_deinterlace = 0;
501 }
502
503
504 if( (i4_chroma_format != IV_YUV_420P) &&
505 (i4_chroma_format != IV_YUV_420SP_UV) &&
506 (i4_chroma_format != IV_YUV_420SP_VU))
507 {
508 i4_share_disp_buf = 0;
509 }
510
511 /* Disable deinterlacer in shared mode */
512 if(i4_share_disp_buf)
513 {
514 u4_deinterlace = 0;
515 }
516
517 /*************************************************************************/
518 /* Fill the memory requirement XDM Handle */
519 /*************************************************************************/
520 /* ! */
521 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
522 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
523 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
524
525 ps_mem_rec++;
526 u1_no_rec++;
527
528 {
529 /*************************************************************************/
530 /* Fill the memory requirement for threads context */
531 /*************************************************************************/
532 /* ! */
533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
535 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
536
537 ps_mem_rec++;
538 u1_no_rec++;
539 }
540
541 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
542 {
543 /*************************************************************************/
544 /* Fill the memory requirement for MPEG2 Decoder Context */
545 /*************************************************************************/
546 /* ! */
547 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
548 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
549 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
550
551 ps_mem_rec++;
552 u1_no_rec++;
553
554 /* To store thread handle */
555 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
556 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
557 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
558
559 ps_mem_rec++;
560 u1_no_rec++;
561
562 /* To store start/done mutex */
563 ps_mem_rec->u4_mem_alignment = 8 /* 8 byte alignment*/;
564 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
565 /* Request memory to hold mutex (start/done) */
566 WORD32 size = 2 * ithread_get_mutex_lock_size();
567 ps_mem_rec->u4_mem_size = size;
568
569 ps_mem_rec++;
570 u1_no_rec++;
571
572 /* To store start/done condition variables */
573 ps_mem_rec->u4_mem_alignment = 8 /* 8 byte alignment*/;
574 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
575 /* Request memory to hold condition variables */
576 size = 2 * ithread_get_cond_struct_size();
577 ps_mem_rec->u4_mem_size = size;
578
579 ps_mem_rec++;
580 u1_no_rec++;
581
582 /*************************************************************************/
583 /* Fill the memory requirement for Motion Compensation Buffers */
584 /*************************************************************************/
585 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
586 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
587
588 /* for mc_fw_buf.pu1_y */
589 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
590
591 /* for mc_fw_buf.pu1_u */
592 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
593
594 /* for mc_fw_buf.pu1_v */
595 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
596
597 /* for mc_bk_buf.pu1_y */
598 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
599
600 /* for mc_bk_buf.pu1_u */
601 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
602
603 /* for mc_bk_buf.pu1_v */
604 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
605
606 /* for mc_buf.pu1_y */
607 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
608
609 /* for mc_buf.pu1_u */
610 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
611
612 /* for mc_buf.pu1_v */
613 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
614
615 ps_mem_rec++;
616 u1_no_rec++;
617
618
619 /*************************************************************************/
620 /* Fill the memory requirement Stack Context */
621 /*************************************************************************/
622 /* ! */
623 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
624 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
625 ps_mem_rec->u4_mem_size = 392;
626
627 ps_mem_rec++;
628 u1_no_rec++;
629 }
630
631
632
633 {
634 /*************************************************************************/
635 /* Fill the memory requirement for Picture Buffer Manager */
636 /*************************************************************************/
637 /* ! */
638 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
639 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
640 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
641
642 ps_mem_rec++;
643 u1_no_rec++;
644 }
645 /*************************************************************************/
646 /* Internal Frame Buffers */
647 /*************************************************************************/
648 /* ! */
649
650 {
651 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
652 {
653 /* ! */
654 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
655 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
656 if(0 == i4_share_disp_buf)
657 ps_mem_rec->u4_mem_size = max_frm_size;
658 else if(IV_YUV_420P != i4_chroma_format)
659 {
660 /* If color format is not 420P and it is shared, then allocate for chroma */
661 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
662 }
663 else
664 ps_mem_rec->u4_mem_size = 64;
665 ps_mem_rec++;
666 u1_no_rec++;
667 }
668 }
669
670 ps_mem_rec->u4_mem_alignment = 128;
671 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
672 ps_mem_rec->u4_mem_size = MAX_BITSTREAM_BUFFER_SIZE + MIN_BUFFER_BYTES_AT_EOS;
673 ps_mem_rec++;
674 u1_no_rec++;
675
676 {
677 WORD32 i4_job_queue_size;
678 WORD32 i4_num_jobs;
679
680 /* One job per row of MBs */
681 i4_num_jobs = max_frm_height >> 4;
682
683 /* One format convert/frame copy job per row of MBs for non-shared mode*/
684 i4_num_jobs += max_frm_height >> 4;
685
686
687 i4_job_queue_size = impeg2_jobq_ctxt_size();
688 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
689 ps_mem_rec->u4_mem_size = i4_job_queue_size;
690 ps_mem_rec->u4_mem_alignment = 128;
691 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
692
693 ps_mem_rec++;
694 u1_no_rec++;
695
696 }
697
698 ps_mem_rec->u4_mem_alignment = 128;
699 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
700 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size();
701 ps_mem_rec++;
702 u1_no_rec++;
703
704 ps_mem_rec->u4_mem_alignment = 128;
705 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
706
707 if(IV_YUV_420P != i4_chroma_format)
708 ps_mem_rec->u4_mem_size = max_frm_size;
709 else
710 ps_mem_rec->u4_mem_size = 64;
711
712 ps_mem_rec++;
713 u1_no_rec++;
714
715 ps_mem_rec->u4_mem_alignment = 128;
716 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
717 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
718 ps_mem_rec++;
719 u1_no_rec++;
720
721 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
722 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
723 }
724
725
726 /*****************************************************************************/
727 /* */
728 /* Function Name : impeg2d_api_get_version */
729 /* */
730 /* Description : */
731 /* */
732 /* Inputs : */
733 /* Globals : <Does it use any global variables?> */
734 /* Outputs : */
735 /* Returns : void */
736 /* */
737 /* Issues : none */
738 /* */
739 /* Revision History: */
740 /* */
741 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
742 /* 22 10 2008 100356 Draft */
743 /* */
744 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)745 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
746 void *pv_api_ip,
747 void *pv_api_op)
748 {
749 char au1_version_string[512];
750
751 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
752 impeg2d_ctl_getversioninfo_op_t *ps_op;
753
754 UNUSED(ps_dechdl);
755
756 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
757 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
758
759 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
760
761 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
762 CODEC_VENDOR);
763
764 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
765 {
766 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
767 return (IV_FAIL);
768 }
769
770 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
771 >= (strlen(au1_version_string) + 1))
772 {
773 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
774 au1_version_string, (strlen(au1_version_string) + 1));
775 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
776 }
777 else
778 {
779 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
780 }
781
782 return (IV_SUCCESS);
783 }
784
impeg2d_join_threads(dec_state_multi_core_t * ps_dec_state_multi_core)785 WORD32 impeg2d_join_threads(dec_state_multi_core_t *ps_dec_state_multi_core)
786 {
787 dec_state_t *ps_dec_thd, *ps_dec_state;
788
789 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
790
791 if(ps_dec_state->i4_threads_active)
792 {
793 int i;
794 for(i = 0; i < MAX_THREADS; i++)
795 {
796 WORD32 ret;
797 ps_dec_thd = ps_dec_state_multi_core->ps_dec_state[i];
798 if(ps_dec_state_multi_core->au4_thread_launched[i])
799 {
800 ret = ithread_mutex_lock(ps_dec_thd->pv_proc_start_mutex);
801 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret) return(IV_FAIL);
802
803 // set process start for the threads waiting on the start condition
804 // in the decode routine so as to break them
805 ps_dec_thd->ai4_process_start = 1;
806 ps_dec_state_multi_core->i4_break_threads = 1;
807
808 ret = ithread_cond_signal(ps_dec_thd->pv_proc_start_condition);
809 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret) return(IV_FAIL);
810
811 ret = ithread_mutex_unlock(ps_dec_thd->pv_proc_start_mutex);
812 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret) return(IV_FAIL);
813
814 ithread_join(ps_dec_thd->pv_codec_thread_handle, NULL);
815 ps_dec_state_multi_core->au4_thread_launched[i] = 0;
816 ps_dec_state_multi_core->i4_break_threads = 0;
817 }
818 }
819 }
820
821 return IV_SUCCESS;
822 }
823
824 /*****************************************************************************/
825 /* */
826 /* Function Name : impeg2d_api_get_buf_info */
827 /* */
828 /* Description : */
829 /* */
830 /* Inputs : */
831 /* Globals : <Does it use any global variables?> */
832 /* Outputs : */
833 /* Returns : void */
834 /* */
835 /* Issues : none */
836 /* */
837 /* Revision History: */
838 /* */
839 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
840 /* 22 10 2008 100356 Draft */
841 /* */
842 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)843 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
844 void *pv_api_ip,
845 void *pv_api_op)
846 {
847 dec_state_t *ps_dec_state;
848 dec_state_multi_core_t *ps_dec_state_multi_core;
849 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
850 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
851 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
852 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
853 UWORD32 u4_i, u4_stride, u4_height;
854 UNUSED(ps_ctl_bufinfo_ip);
855
856 ps_dec_state_multi_core =
857 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
858 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
859
860 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
861 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
862
863 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
864 {
865 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
866 0;
867 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
868 0;
869 }
870
871 for(u4_i = 0;
872 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
873 u4_i++)
874 {
875 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
876 MAX_BITSTREAM_BUFFER_SIZE;
877 }
878
879 if (0 == ps_dec_state->u4_frm_buf_stride)
880 {
881 if (1 == ps_dec_state->u2_header_done)
882 {
883 u4_stride = ps_dec_state->u2_horizontal_size;
884 }
885 else
886 {
887 u4_stride = ps_dec_state->u2_create_max_width;
888 }
889 }
890 else
891 {
892 u4_stride = ps_dec_state->u4_frm_buf_stride;
893 }
894 u4_stride = ALIGN16(u4_stride);
895 u4_height = ALIGN32(ps_dec_state->u2_frame_height) + 9;
896
897 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
898 impeg2d_get_outbuf_size(
899 u4_stride,
900 u4_height,
901 ps_dec_state->i4_chromaFormat,
902 &ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0]);
903
904 if (0 == ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs)
905 {
906 //Invalid chroma format; Error code may be updated, verify in testing if needed
907 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
908 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
909 return IV_FAIL;
910 }
911
912 /* Adding initialization for 2 uninitialized values */
913 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
914 if(ps_dec_state->u4_share_disp_buf)
915 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
916 NUM_INT_FRAME_BUFFERS;
917 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
918
919 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
920
921 return (IV_SUCCESS);
922 }
923
924 /*****************************************************************************/
925 /* */
926 /* Function Name : impeg2d_api_set_flush_mode */
927 /* */
928 /* Description : */
929 /* */
930 /* Inputs : */
931 /* Globals : <Does it use any global variables?> */
932 /* Outputs : */
933 /* Returns : void */
934 /* */
935 /* Issues : none */
936 /* */
937 /* Revision History: */
938 /* */
939 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
940 /* 08 06 2009 100356 RAVI */
941 /* */
942 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)943 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
944 void *pv_api_ip,
945 void *pv_api_op)
946 {
947 dec_state_t *ps_dec_state;
948 dec_state_multi_core_t *ps_dec_state_multi_core;
949 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
950 (impeg2d_ctl_flush_op_t*)pv_api_op;
951
952 UNUSED(pv_api_ip);
953
954 ps_dec_state_multi_core =
955 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
956 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
957 impeg2d_join_threads(ps_dec_state_multi_core);
958
959 ps_dec_state->u1_flushfrm = 1;
960
961 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
962 sizeof(impeg2d_ctl_flush_op_t);
963 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
964
965 return (IV_SUCCESS);
966 }
967
968 /*****************************************************************************/
969 /* */
970 /* Function Name : impeg2d_api_set_default */
971 /* */
972 /* Description : */
973 /* */
974 /* Inputs : */
975 /* Globals : <Does it use any global variables?> */
976 /* Outputs : */
977 /* Returns : void */
978 /* */
979 /* Issues : none */
980 /* */
981 /* Revision History: */
982 /* */
983 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
984 /* 08 06 2009 100356 RAVI */
985 /* */
986 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)987 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
988 void *pv_api_ip,
989 void *pv_api_op)
990 {
991 dec_state_t *ps_dec_state;
992 dec_state_multi_core_t *ps_dec_state_multi_core;
993 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
994 (impeg2d_ctl_set_config_op_t *)pv_api_op;
995
996 UNUSED(pv_api_ip);
997
998 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
999 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
1000 sizeof(impeg2d_ctl_set_config_op_t);
1001
1002 ps_dec_state_multi_core =
1003 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
1004 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1005
1006 ps_dec_state->u1_flushfrm = 0;
1007 ps_dec_state->u2_decode_header = 1;
1008
1009 if (1 == ps_dec_state->u2_header_done)
1010 {
1011 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1012 }
1013
1014 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1015
1016 return (IV_SUCCESS);
1017
1018 }
1019
1020
1021 /*****************************************************************************/
1022 /* */
1023 /* Function Name : impeg2d_api_reset */
1024 /* */
1025 /* Description : */
1026 /* */
1027 /* Inputs : */
1028 /* Globals : <Does it use any global variables?> */
1029 /* Outputs : */
1030 /* Returns : void */
1031 /* */
1032 /* Issues : none */
1033 /* */
1034 /* Revision History: */
1035 /* */
1036 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1037 /* 08 06 2009 100356 RAVI */
1038 /* */
1039 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1040 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
1041 void *pv_api_ip,
1042 void *pv_api_op)
1043 {
1044 dec_state_t *ps_dec_state;
1045 dec_state_multi_core_t *ps_dec_state_multi_core;
1046 UNUSED(pv_api_ip);
1047 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
1048
1049 WORD32 i4_num_threads;
1050
1051 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1052 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1053
1054 if(ps_dec_state_multi_core != NULL)
1055 {
1056 impeg2d_join_threads(ps_dec_state_multi_core);
1057 impeg2_buf_mgr_reset(ps_dec_state->pv_pic_buf_mg);
1058 /* Display buffer manager init behaves like a reset
1059 * as it doesn't need to preserve picture buffer addresses
1060 * like buffer manager */
1061 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1062
1063 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1064 {
1065 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1066
1067
1068 /* --------------------------------------------------------------------- */
1069 /* Initializations */
1070
1071 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1072 ps_dec_state->u4_frm_buf_stride = 0;
1073 ps_dec_state->i4_pic_count = 0;
1074 ps_dec_state->u2_is_mpeg2 = 0;
1075 ps_dec_state->aps_ref_pics[0] = NULL;
1076 ps_dec_state->aps_ref_pics[1] = NULL;
1077 ps_dec_state->ps_deint_pic = NULL;
1078 }
1079 }
1080 else
1081 {
1082 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
1083 IMPEG2D_INIT_NOT_DONE;
1084 }
1085
1086 return(IV_SUCCESS);
1087 }
1088
1089 /*****************************************************************************/
1090 /* */
1091 /* Function Name : impeg2d_api_set_params */
1092 /* */
1093 /* Description : */
1094 /* */
1095 /* Inputs : */
1096 /* Globals : <Does it use any global variables?> */
1097 /* Outputs : */
1098 /* Returns : void */
1099 /* */
1100 /* Issues : none */
1101 /* */
1102 /* Revision History: */
1103 /* */
1104 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1105 /* 08 06 2009 100356 RAVI */
1106 /* */
1107 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1108 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
1109 {
1110 dec_state_t *ps_dec_state;
1111 dec_state_multi_core_t *ps_dec_state_multi_core;
1112 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
1113 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
1114
1115 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1116 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1117
1118 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
1119 {
1120 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1121 return(IV_FAIL);
1122 }
1123
1124 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
1125 {
1126 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1127 return(IV_FAIL);
1128 }
1129
1130 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
1131 {
1132 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1133 return(IV_FAIL);
1134 }
1135
1136 if(ps_dec_state->u2_header_done == 1)
1137 {
1138 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
1139 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
1140 {
1141 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1142 return(IV_FAIL);
1143 }
1144
1145 }
1146
1147
1148 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1149
1150 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1151 {
1152 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1153 }
1154 else
1155 {
1156
1157 if(ps_dec_state->u2_header_done == 1)
1158 {
1159 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1160 }
1161 else
1162 {
1163 ps_dec_state->u4_frm_buf_stride = 0;
1164 }
1165 }
1166
1167
1168 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1169 {
1170 ps_dec_state->u1_flushfrm = 0;
1171 }
1172
1173
1174 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1175 return(IV_SUCCESS);
1176
1177 }
1178
1179 /*****************************************************************************/
1180 /* */
1181 /* Function Name : impeg2d_api_get_status */
1182 /* */
1183 /* Description : */
1184 /* */
1185 /* Inputs : */
1186 /* Globals : <Does it use any global variables?> */
1187 /* Outputs : */
1188 /* Returns : void */
1189 /* */
1190 /* Issues : none */
1191 /* */
1192 /* Revision History: */
1193 /* */
1194 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1195 /* 08 06 2009 100356 RAVI */
1196 /* */
1197 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1198 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1199 void *pv_api_ip,
1200 void *pv_api_op)
1201 {
1202 dec_state_t *ps_dec_state;
1203 dec_state_multi_core_t *ps_dec_state_multi_core;
1204 UWORD32 u4_i,u4_stride,u4_height;
1205 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1206 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1207 UNUSED(ps_ctl_dec_ip);
1208
1209 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1210 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1211
1212 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1213 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1214 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1215 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1216 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1217
1218
1219 if(ps_dec_state->u2_progressive_sequence == 1)
1220 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1221 else
1222 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1223
1224
1225 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1226 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1227 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1228
1229
1230 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1231 {
1232 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1233 }
1234 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1235 {
1236 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1237 }
1238 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1239 {
1240 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1241 }
1242 else
1243 {
1244 //Invalid chroma format; Error code may be updated, verify in testing if needed
1245 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1246 return IV_FAIL;
1247 }
1248
1249 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1250 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1251
1252 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1253 {
1254 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1255 }
1256
1257 u4_stride = ps_dec_state->u4_frm_buf_stride;
1258 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1259
1260 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1261 {
1262 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1263 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1264 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1265 }
1266 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1267 {
1268 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1269 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1270 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1271 }
1272 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1273 {
1274 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1275 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1276 }
1277
1278 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1279
1280 return(IV_SUCCESS);
1281
1282 }
1283
1284 /**
1285 *******************************************************************************
1286 *
1287 * @brief
1288 * Gets frame dimensions/offsets
1289 *
1290 * @par Description:
1291 * Gets frame buffer chararacteristics such a x & y offsets display and
1292 * buffer dimensions
1293 *
1294 * @param[in] ps_codec_obj
1295 * Pointer to codec object at API level
1296 *
1297 * @param[in] pv_api_ip
1298 * Pointer to input argument structure
1299 *
1300 * @param[out] pv_api_op
1301 * Pointer to output argument structure
1302 *
1303 * @returns Status
1304 *
1305 * @remarks
1306 *
1307 *
1308 *******************************************************************************
1309 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1310 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1311 void *pv_api_ip,
1312 void *pv_api_op)
1313 {
1314 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1315 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1316 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1317 dec_state_t *ps_codec;
1318 dec_state_multi_core_t *ps_dec_state_multi_core;
1319
1320 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1321 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1322
1323
1324 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1325 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1326 UNUSED(ps_ip);
1327 if(ps_codec->u2_header_done)
1328 {
1329 disp_wd = ps_codec->u2_horizontal_size;
1330 disp_ht = ps_codec->u2_vertical_size;
1331
1332 if(0 == ps_codec->u4_share_disp_buf)
1333 {
1334 buffer_wd = disp_wd;
1335 buffer_ht = disp_ht;
1336 }
1337 else
1338 {
1339 buffer_wd = ps_codec->u2_frame_width;
1340 buffer_ht = ps_codec->u2_frame_height;
1341 }
1342 }
1343 else
1344 {
1345
1346 disp_wd = ps_codec->u2_create_max_width;
1347 disp_ht = ps_codec->u2_create_max_height;
1348
1349 if(0 == ps_codec->u4_share_disp_buf)
1350 {
1351 buffer_wd = disp_wd;
1352 buffer_ht = disp_ht;
1353 }
1354 else
1355 {
1356 buffer_wd = ALIGN16(disp_wd);
1357 buffer_ht = ALIGN16(disp_ht);
1358
1359 }
1360 }
1361 if(ps_codec->u2_frame_width > buffer_wd)
1362 buffer_wd = ps_codec->u2_frame_width;
1363
1364 x_offset = 0;
1365 y_offset = 0;
1366
1367
1368 ps_op->u4_disp_wd[0] = disp_wd;
1369 ps_op->u4_disp_ht[0] = disp_ht;
1370 ps_op->u4_buffer_wd[0] = buffer_wd;
1371 ps_op->u4_buffer_ht[0] = buffer_ht;
1372 ps_op->u4_x_offset[0] = x_offset;
1373 ps_op->u4_y_offset[0] = y_offset;
1374
1375 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1376 >> 1);
1377 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1378 >> 1);
1379 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1380 >> 1);
1381 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1382 >> 1);
1383 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1384 >> 1);
1385 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1386 >> 1);
1387
1388 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1389 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1390 {
1391 ps_op->u4_disp_wd[2] = 0;
1392 ps_op->u4_disp_ht[2] = 0;
1393 ps_op->u4_buffer_wd[2] = 0;
1394 ps_op->u4_buffer_ht[2] = 0;
1395 ps_op->u4_x_offset[2] = 0;
1396 ps_op->u4_y_offset[2] = 0;
1397
1398 ps_op->u4_disp_wd[1] <<= 1;
1399 ps_op->u4_buffer_wd[1] <<= 1;
1400 ps_op->u4_x_offset[1] <<= 1;
1401 }
1402
1403 return IV_SUCCESS;
1404
1405 }
1406
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1407 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1408 {
1409 WORD32 i4_cmd;
1410 IV_API_CALL_STATUS_T u4_error_code;
1411 UWORD32 *pu4_api_ip;
1412
1413 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1414 if(IV_SUCCESS != u4_error_code)
1415 {
1416 return u4_error_code;
1417 }
1418
1419
1420 pu4_api_ip = (UWORD32 *)pv_api_ip;
1421 i4_cmd = *(pu4_api_ip + 1);
1422
1423 switch(i4_cmd)
1424 {
1425
1426 case IV_CMD_GET_NUM_MEM_REC:
1427 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1428 break;
1429
1430 case IV_CMD_FILL_NUM_MEM_REC:
1431 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1432 break;
1433
1434 case IV_CMD_INIT:
1435 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1436 break;
1437
1438 case IVD_CMD_SET_DISPLAY_FRAME:
1439 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1440 break;
1441
1442 case IVD_CMD_REL_DISPLAY_FRAME:
1443 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1444 break;
1445
1446 case IVD_CMD_VIDEO_DECODE:
1447 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1448 break;
1449
1450 case IV_CMD_RETRIEVE_MEMREC:
1451 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1452 break;
1453
1454 case IVD_CMD_VIDEO_CTL:
1455 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1456 break;
1457
1458 default:
1459 break;
1460 }
1461
1462 return(u4_error_code);
1463
1464 }
1465
1466 /*****************************************************************************/
1467 /* */
1468 /* Function Name : impeg2d_api_num_mem_rec */
1469 /* */
1470 /* Description : The function get the number mem records library needs */
1471 /* Inputs : Error message */
1472 /* Globals : None */
1473 /* Processing : Just prints error message to console */
1474 /* Outputs : Error mesage to the console */
1475 /* Returns : None */
1476 /* */
1477 /* Issues : <List any issues or problems with this function> */
1478 /* */
1479 /* Revision History: */
1480 /* */
1481 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1482 /* 23 09 2010 Hamsalekha Creation */
1483 /* */
1484 /*****************************************************************************/
1485
1486
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1487 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1488 {
1489 /* To Query No of Memory Records */
1490 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1491 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1492
1493 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1494 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1495
1496 UNUSED(ps_query_mem_rec_ip);
1497 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1498
1499 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1500
1501 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1502
1503
1504 return(IV_SUCCESS);
1505
1506 }
1507
1508
1509 /*****************************************************************************/
1510 /* */
1511 /* Function Name : impeg2d_api_fill_mem_rec */
1512 /* */
1513 /* Description : Thsi functions fills details of each mem record lib needs*/
1514 /* Inputs : Error message */
1515 /* Globals : None */
1516 /* Processing : Just prints error message to console */
1517 /* Outputs : Error mesage to the console */
1518 /* Returns : None */
1519 /* */
1520 /* Issues : <List any issues or problems with this function> */
1521 /* */
1522 /* Revision History: */
1523 /* */
1524 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1525 /* 23 09 2010 Hamsalekha Creation */
1526 /* */
1527 /*****************************************************************************/
1528
1529
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1530 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1531 {
1532
1533 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1534 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1535
1536
1537 ps_mem_q_ip = pv_api_ip;
1538 ps_mem_q_op = pv_api_op;
1539
1540
1541 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1542 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1543
1544
1545 return(IV_SUCCESS);
1546
1547 }
1548
impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,WORD32 u1_chroma_format,UWORD32 * p_buf_size)1549 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size)
1550 {
1551 UWORD32 u4_min_num_out_bufs = 0;
1552 if(u1_chroma_format == IV_YUV_420P)
1553 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1554 else if(u1_chroma_format == IV_YUV_422ILE)
1555 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1556 else if(u1_chroma_format == IV_RGB_565)
1557 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1558 else if((u1_chroma_format == IV_YUV_420SP_UV)
1559 || (u1_chroma_format == IV_YUV_420SP_VU))
1560 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
1561
1562 if(u1_chroma_format == IV_YUV_420P)
1563 {
1564 p_buf_size[0] = (pic_wd * pic_ht);
1565 p_buf_size[1] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1);
1566 p_buf_size[2] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1);
1567 }
1568 else if(u1_chroma_format == IV_YUV_422ILE)
1569 {
1570 p_buf_size[0] = (pic_wd * pic_ht)
1571 * 2;
1572 p_buf_size[1] =
1573 p_buf_size[2] = 0;
1574 }
1575 else if(u1_chroma_format == IV_RGB_565)
1576 {
1577 p_buf_size[0] = (pic_wd * pic_ht)
1578 * 2;
1579 p_buf_size[1] =
1580 p_buf_size[2] = 0;
1581 }
1582 else if((u1_chroma_format == IV_YUV_420SP_UV)
1583 || (u1_chroma_format == IV_YUV_420SP_VU))
1584 {
1585 p_buf_size[0] = (pic_wd * pic_ht);
1586 p_buf_size[1] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1) * 2;
1587 p_buf_size[2] = 0;
1588 }
1589 return u4_min_num_out_bufs;
1590 }
1591
check_app_out_buf_size(dec_state_t * ps_dec)1592 WORD32 check_app_out_buf_size(dec_state_t *ps_dec)
1593 {
1594 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1595 UWORD32 u4_min_num_out_bufs, i;
1596 UWORD32 pic_wd, pic_ht;
1597
1598 pic_wd = ps_dec->u2_horizontal_size;
1599 pic_ht = ps_dec->u2_vertical_size;
1600
1601 if(ps_dec->u4_frm_buf_stride > pic_wd)
1602 pic_wd = ps_dec->u4_frm_buf_stride;
1603
1604 u4_min_num_out_bufs = impeg2d_get_outbuf_size(pic_wd, pic_ht, ps_dec->i4_chromaFormat, &au4_min_out_buf_size[0]);
1605
1606 if (0 == ps_dec->u4_share_disp_buf)
1607 {
1608 if(ps_dec->ps_out_buf->u4_num_bufs < u4_min_num_out_bufs)
1609 {
1610 return IV_FAIL;
1611 }
1612
1613 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1614 {
1615 if(ps_dec->ps_out_buf->u4_min_out_buf_size[i] < au4_min_out_buf_size[i])
1616 return (IV_FAIL);
1617 }
1618 }
1619 else
1620 {
1621 if(ps_dec->as_disp_buffers[0].u4_num_bufs < u4_min_num_out_bufs)
1622 return IV_FAIL;
1623
1624 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1625 {
1626 /* We need to check only with the disp_buffer[0], because we have
1627 * already ensured that all the buffers are of the same size in
1628 * impeg2d_api_set_display_frame.
1629 */
1630 if(ps_dec->as_disp_buffers[0].u4_min_out_buf_size[i] <
1631 au4_min_out_buf_size[i])
1632 return (IV_FAIL);
1633 }
1634 }
1635
1636 return(IV_SUCCESS);
1637 }
1638
1639
1640
1641 /*****************************************************************************/
1642 /* */
1643 /* Function Name : impeg2d_api_init */
1644 /* */
1645 /* Description : */
1646 /* Inputs : */
1647 /* Globals : */
1648 /* Processing : */
1649 /* Outputs : */
1650 /* Returns : */
1651 /* */
1652 /* Issues : */
1653 /* */
1654 /* Revision History: */
1655 /* */
1656 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1657 /* 17 09 2007 Rajendra C Y Draft */
1658 /* */
1659 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1660 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1661 void *ps_ip,
1662 void *ps_op)
1663 {
1664 UWORD32 i;
1665
1666 void *pv;
1667 UWORD32 u4_size;
1668
1669 dec_state_t *ps_dec_state;
1670 dec_state_multi_core_t *ps_dec_state_multi_core;
1671 UWORD32 u4_num_mem_rec;
1672 iv_mem_rec_t *ps_mem_rec ;
1673 iv_mem_rec_t *ps_frm_buf;
1674 iv_obj_t *ps_dec_handle;
1675 WORD32 i4_max_wd, i4_max_ht;
1676
1677 impeg2d_init_ip_t *ps_dec_init_ip;
1678 impeg2d_init_op_t *ps_dec_init_op;
1679 WORD32 i4_num_threads;
1680 UWORD32 u4_share_disp_buf, u4_chroma_format;
1681 UWORD32 u4_deinterlace;
1682 WORD32 i4_threads_active;
1683
1684 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1685 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1686
1687 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1688 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1689
1690 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1691 {
1692 #ifndef LOGO_EN
1693 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1694 #else
1695 u4_share_disp_buf = 0;
1696 #endif
1697 }
1698 else
1699 {
1700 u4_share_disp_buf = 0;
1701 }
1702
1703 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1704
1705 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace))
1706 {
1707 u4_deinterlace = ps_dec_init_ip->u4_deinterlace;
1708 }
1709 else
1710 {
1711 u4_deinterlace = 0;
1712 }
1713
1714 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_keep_threads_active))
1715 {
1716 i4_threads_active = ps_dec_init_ip->u4_keep_threads_active;
1717 }
1718 else
1719 {
1720 i4_threads_active = 0;
1721 }
1722
1723 if( (u4_chroma_format != IV_YUV_420P) &&
1724 (u4_chroma_format != IV_YUV_420SP_UV) &&
1725 (u4_chroma_format != IV_YUV_420SP_VU))
1726 {
1727 u4_share_disp_buf = 0;
1728 }
1729
1730 /* Disable deinterlacer in shared mode */
1731 if(u4_share_disp_buf)
1732 {
1733 u4_deinterlace = 0;
1734 }
1735
1736 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1737 ps_mem_rec ++;
1738
1739
1740 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1741
1742
1743 /* Except memTab[0], all other memTabs are initialized to zero */
1744 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1745 {
1746 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1747 ps_mem_rec++;
1748 }
1749
1750 /* Reinitializing memTab[0] memory base address */
1751 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1752
1753
1754 /* memTab[0] is for codec Handle,redundant currently not being used */
1755 ps_dec_handle = ps_mem_rec->pv_base;
1756 u4_num_mem_rec = 1;
1757 ps_mem_rec++;
1758
1759
1760
1761
1762
1763 /* decoder handle */
1764 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1765 u4_num_mem_rec++;
1766 ps_mem_rec++;
1767
1768
1769 {
1770 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1771
1772 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1773 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1774 }
1775
1776
1777 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1778 {
1779 WORD32 ret;
1780 UWORD8 *pv_buf;
1781 WORD32 mutex_size = ithread_get_mutex_lock_size();
1782 WORD32 cond_size = ithread_get_cond_struct_size();
1783 /*************************************************************************/
1784 /* For MPEG2 Decoder Context */
1785 /*************************************************************************/
1786 ps_dec_state = ps_mem_rec->pv_base;
1787
1788 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1789
1790 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1791
1792 ps_dec_state->i4_num_cores = 1;
1793 /* @ */ /* Used for storing MemRecords */
1794 u4_num_mem_rec++;
1795 ps_mem_rec++;
1796
1797 /* Thread handle */
1798 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1799 u4_num_mem_rec++;
1800 ps_mem_rec++;
1801
1802 pv_buf = ps_mem_rec->pv_base;
1803 if (ps_mem_rec->u4_mem_size < 2 * mutex_size)
1804 {
1805 ps_dec_init_op->s_ivd_init_op_t.u4_error_code =
1806 IMPEG2D_INIT_DEC_PER_MEM_INSUFFICIENT;
1807 return(IV_FAIL);
1808 }
1809
1810 ps_dec_state->pv_proc_start_mutex = (UWORD8 *)pv_buf;
1811 ps_dec_state->pv_proc_done_mutex = (UWORD8 *)pv_buf + mutex_size;
1812
1813 ret = ithread_mutex_init(ps_dec_state->pv_proc_start_mutex);
1814 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1815
1816 ret = ithread_mutex_init(ps_dec_state->pv_proc_done_mutex);
1817 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1818
1819 u4_num_mem_rec++;
1820 ps_mem_rec++;
1821
1822 pv_buf = ps_mem_rec->pv_base;
1823 if (ps_mem_rec->u4_mem_size < 2 * cond_size)
1824 {
1825 ps_dec_init_op->s_ivd_init_op_t.u4_error_code =
1826 IMPEG2D_INIT_DEC_PER_MEM_INSUFFICIENT;
1827 return(IV_FAIL);
1828 }
1829 ps_dec_state->pv_proc_start_condition = (UWORD8 *)pv_buf;
1830 ps_dec_state->pv_proc_done_condition = (UWORD8 *)pv_buf + cond_size;
1831
1832 ret = ithread_cond_init(ps_dec_state->pv_proc_start_condition);
1833 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1834
1835 ret = ithread_cond_init(ps_dec_state->pv_proc_done_condition);
1836 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1837
1838 u4_num_mem_rec++;
1839 ps_mem_rec++;
1840
1841 /*************************************************************************/
1842 /* For Motion Compensation Buffers */
1843 /*************************************************************************/
1844 pv = ps_mem_rec->pv_base;
1845
1846 /* for mc_fw_buf.pu1_y */
1847
1848 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1849 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1850
1851 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1852 /* for mc_fw_buf.pu1_u */
1853
1854 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1855 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1856
1857 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1858
1859 /* for mc_fw_buf.pu1_v */
1860
1861 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1862 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1863
1864 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1865
1866 /* for mc_bk_buf.pu1_y */
1867
1868 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1869 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1870
1871 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1872
1873 /* for mc_bk_buf.pu1_u */
1874
1875 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1876 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1877
1878 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1879
1880 /* for mc_bk_buf.pu1_v */
1881
1882 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1883 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1884
1885 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1886
1887 /* for mc_buf.pu1_y */
1888
1889 ps_dec_state->s_mc_buf.pu1_y = pv;
1890 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1891
1892 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1893
1894 /* for mc_buf.pu1_u */
1895
1896 ps_dec_state->s_mc_buf.pu1_u = pv;
1897 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1898
1899 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1900
1901 /* for mc_buf.pu1_v */
1902
1903 ps_dec_state->s_mc_buf.pu1_v = pv;
1904
1905 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1906
1907 u4_num_mem_rec++;
1908 ps_mem_rec++;
1909
1910
1911
1912 ps_dec_state->pv_pic_buf_mg = 0;
1913
1914 /*************************************************************************/
1915 /* For saving stack context to support global error handling */
1916 /*************************************************************************/
1917 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1918 u4_num_mem_rec++;
1919 ps_mem_rec++;
1920
1921 }
1922
1923
1924
1925
1926
1927 /*************************************************************************/
1928 /* For Picture Buffer Manager */
1929 /*************************************************************************/
1930 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1931
1932 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1933 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1934
1935 u4_num_mem_rec++;
1936 ps_mem_rec++;
1937
1938
1939
1940 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1941 {
1942
1943 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1944
1945
1946 /* --------------------------------------------------------------------- */
1947 /* Initializations */
1948
1949 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1950
1951
1952 {
1953 UWORD32 u4_max_frm_width,u4_max_frm_height;
1954
1955 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1956 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1957
1958 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1959 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1960
1961 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1962 ps_dec_state->u4_frm_buf_stride = 0 ;
1963 ps_dec_state->u2_frame_width = u4_max_frm_width;
1964 ps_dec_state->u2_picture_width = u4_max_frm_width;
1965 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1966
1967 ps_dec_state->u2_frame_height = u4_max_frm_height;
1968 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1969 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1970 ps_dec_state->u4_deinterlace = u4_deinterlace;
1971 ps_dec_state->i4_threads_active = i4_threads_active;
1972 ps_dec_state->ps_deint_pic = NULL;
1973 }
1974 }
1975
1976 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1977
1978 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1979 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1980 {
1981 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1982 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1983 return(IV_FAIL);
1984
1985
1986 }
1987
1988 /* --------------------------------------------------------------------- */
1989
1990
1991 /* ! */
1992 // picture buffer manager initialization will be done only for first thread
1993 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1994 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1995
1996 /*************************************************************************/
1997 /* Internal Frame Buffers */
1998 /*************************************************************************/
1999
2000
2001 /* Set first frame to grey */
2002 {
2003 ps_frm_buf = ps_mem_rec;
2004 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
2005 ps_frm_buf++;
2006 }
2007
2008 if(0 == ps_dec_state->u4_share_disp_buf)
2009 {
2010 pic_buf_t *ps_pic_buf;
2011 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
2012 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
2013 {
2014 UWORD8 *pu1_buf;
2015 pu1_buf = ps_mem_rec->pv_base;
2016
2017 ps_pic_buf->pu1_y = pu1_buf;
2018 pu1_buf += i4_max_ht * i4_max_wd;
2019
2020 ps_pic_buf->pu1_u = pu1_buf;
2021 pu1_buf += i4_max_ht * i4_max_wd >> 2;
2022
2023 ps_pic_buf->pu1_v = pu1_buf;
2024 pu1_buf += i4_max_ht * i4_max_wd >> 2;
2025
2026 ps_pic_buf->i4_buf_id = i;
2027
2028 ps_pic_buf->u1_used_as_ref = 0;
2029
2030 ps_pic_buf->u4_ts = 0;
2031
2032 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
2033 ps_mem_rec++;
2034 ps_pic_buf++;
2035 }
2036 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
2037 }
2038 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
2039 {
2040 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
2041 {
2042 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
2043 ps_mem_rec++;
2044 }
2045
2046 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
2047 }
2048 else
2049 {
2050 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
2051 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
2052 }
2053
2054
2055 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
2056
2057 ps_dec_state->pu1_input_buffer = ps_mem_rec->pv_base;
2058 u4_num_mem_rec++;
2059 ps_mem_rec++;
2060
2061 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
2062 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
2063 u4_num_mem_rec++;
2064 ps_mem_rec++;
2065
2066 ps_dec_state->u1_flushfrm = 0;
2067 ps_dec_state->u1_flushcnt = 0;
2068 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
2069
2070
2071 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base;
2072 u4_num_mem_rec++;
2073 ps_mem_rec++;
2074
2075 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base;
2076 u4_num_mem_rec++;
2077 ps_mem_rec++;
2078
2079
2080 /*************************************************************************/
2081 /* Last MemTab is used for storing TabRecords */
2082 /*************************************************************************/
2083 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
2084 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
2085 /* Updating in Decoder Context with memRecords */
2086 u4_num_mem_rec++;
2087 ps_mem_rec++;
2088 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
2089
2090 if(u4_num_mem_rec != ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
2091 {
2092 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
2093 return(IV_FAIL);
2094 }
2095
2096 ps_dec_state->u4_num_frames_decoded = 0;
2097 ps_dec_state->aps_ref_pics[0] = NULL;
2098 ps_dec_state->aps_ref_pics[1] = NULL;
2099
2100 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
2101
2102 impeg2d_init_arch(ps_dec_state);
2103
2104 impeg2d_init_function_ptr(ps_dec_state);
2105
2106 return(IV_SUCCESS);
2107 }
2108
2109 /*****************************************************************************/
2110 /* */
2111 /* Function Name : impeg2d_api_retrieve_mem_rec */
2112 /* */
2113 /* Description : */
2114 /* */
2115 /* Inputs : */
2116 /* Globals : <Does it use any global variables?> */
2117 /* Outputs : */
2118 /* Returns : void */
2119 /* */
2120 /* Issues : none */
2121 /* */
2122 /* Revision History: */
2123 /* */
2124 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2125 /* 22 10 2008 100356 Draft */
2126 /* */
2127 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2128 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
2129 void *pv_api_ip,
2130 void *pv_api_op)
2131 {
2132 UWORD32 u4_i;
2133 dec_state_t *ps_dec_state;
2134 dec_state_multi_core_t *ps_dec_state_multi_core;
2135 iv_mem_rec_t *ps_mem_rec;
2136 iv_mem_rec_t *ps_temp_rec;
2137 IMPEG2D_ERROR_CODES_T ret;
2138 dec_state_t *ps_dec_thd;
2139
2140
2141
2142 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
2143 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
2144
2145 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2146 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2147
2148 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2149 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
2150 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
2151 ps_temp_rec = ps_dec_state->pv_memTab;
2152
2153 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
2154 {
2155 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
2156 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
2157 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
2158 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
2159 }
2160
2161 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
2162 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
2163
2164 if(ps_dec_state->i4_threads_active)
2165 {
2166 impeg2d_join_threads(ps_dec_state_multi_core);
2167
2168 for(u4_i = 0; u4_i < MAX_THREADS; u4_i++)
2169 {
2170 ps_dec_thd = ps_dec_state_multi_core->ps_dec_state[u4_i];
2171
2172 ret = ithread_cond_destroy(ps_dec_thd->pv_proc_start_condition);
2173 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2174 return(IV_FAIL);
2175
2176 ret = ithread_cond_destroy(ps_dec_thd->pv_proc_done_condition);
2177 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2178 return(IV_FAIL);
2179
2180 ret = ithread_mutex_destroy(ps_dec_thd->pv_proc_start_mutex);
2181 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2182 return(IV_FAIL);
2183
2184 ret = ithread_mutex_destroy(ps_dec_thd->pv_proc_done_mutex);
2185 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2186 return(IV_FAIL);
2187 }
2188 }
2189
2190 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
2191 IMPEG2D_PRINT_STATISTICS();
2192
2193
2194 return(IV_SUCCESS);
2195
2196 }
2197
2198 /*****************************************************************************/
2199 /* */
2200 /* Function Name : impeg2d_api_ctl */
2201 /* */
2202 /* Description : */
2203 /* */
2204 /* Inputs : */
2205 /* Globals : <Does it use any global variables?> */
2206 /* Outputs : */
2207 /* Returns : void */
2208 /* */
2209 /* Issues : none */
2210 /* */
2211 /* Revision History: */
2212 /* */
2213 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2214 /* 22 10 2008 100356 Draft */
2215 /* */
2216 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2217 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
2218 void *pv_api_ip,
2219 void *pv_api_op)
2220 {
2221 WORD32 i4_sub_cmd;
2222 UWORD32 *pu4_api_ip;
2223 IV_API_CALL_STATUS_T u4_error_code;
2224
2225 pu4_api_ip = (UWORD32 *)pv_api_ip;
2226 i4_sub_cmd = *(pu4_api_ip + 2);
2227
2228 switch(i4_sub_cmd)
2229 {
2230 case IVD_CMD_CTL_GETPARAMS:
2231 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
2232 (void *)pv_api_op);
2233 break;
2234
2235 case IVD_CMD_CTL_SETPARAMS:
2236 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
2237 (void *)pv_api_op);
2238 break;
2239
2240 case IVD_CMD_CTL_RESET:
2241 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
2242 (void *)pv_api_op);
2243 break;
2244
2245 case IVD_CMD_CTL_SETDEFAULT:
2246 u4_error_code = impeg2d_api_set_default(ps_dechdl,
2247 (void *)pv_api_ip,
2248 (void *)pv_api_op);
2249 break;
2250
2251 case IVD_CMD_CTL_FLUSH:
2252 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
2253 (void *)pv_api_ip,
2254 (void *)pv_api_op);
2255 break;
2256
2257 case IVD_CMD_CTL_GETBUFINFO:
2258 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
2259 (void *)pv_api_ip,
2260 (void *)pv_api_op);
2261 break;
2262
2263 case IVD_CMD_CTL_GETVERSION:
2264 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
2265 (void *)pv_api_op);
2266 break;
2267
2268 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2269 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
2270 (void *)pv_api_ip,
2271 (void *)pv_api_op);
2272 break;
2273
2274 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2275 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
2276 (void *)pv_api_ip,
2277 (void *)pv_api_op);
2278 break;
2279
2280 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2281 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl,
2282 (void *)pv_api_ip,
2283 (void *)pv_api_op);
2284 break;
2285
2286 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2287 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
2288 (void *)pv_api_op);
2289 break;
2290
2291 default:
2292 u4_error_code = IV_FAIL;
2293 break;
2294 }
2295
2296 return (u4_error_code);
2297
2298 }
2299
2300 /*****************************************************************************/
2301 /* */
2302 /* Function Name : impeg2d_api_check_struct_sanity */
2303 /* */
2304 /* Description : */
2305 /* */
2306 /* Inputs : */
2307 /* Globals : <Does it use any global variables?> */
2308 /* Outputs : */
2309 /* Returns : void */
2310 /* */
2311 /* Issues : none */
2312 /* */
2313 /* Revision History: */
2314 /* */
2315 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2316 /* 22 10 2008 100356 Draft */
2317 /* */
2318 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)2319 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
2320 void *pv_api_ip,
2321 void *pv_api_op)
2322 {
2323 WORD32 i4_cmd;
2324 UWORD32 *pu4_api_ip;
2325 UWORD32 *pu4_api_op;
2326 WORD32 i,j;
2327
2328 if(NULL == pv_api_op)
2329 return(IV_FAIL);
2330
2331 if(NULL == pv_api_ip)
2332 return(IV_FAIL);
2333
2334 pu4_api_ip = (UWORD32 *)pv_api_ip;
2335 pu4_api_op = (UWORD32 *)pv_api_op;
2336 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2337
2338 /* error checks on handle */
2339 switch(i4_cmd)
2340 {
2341 case IV_CMD_GET_NUM_MEM_REC:
2342 case IV_CMD_FILL_NUM_MEM_REC:
2343 break;
2344 case IV_CMD_INIT:
2345 if(ps_handle == NULL)
2346 {
2347 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2348 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2349 return IV_FAIL;
2350 }
2351
2352 if(ps_handle->u4_size != sizeof(iv_obj_t))
2353 {
2354 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2355 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2356 return IV_FAIL;
2357 }
2358 break;
2359 case IVD_CMD_GET_DISPLAY_FRAME:
2360 case IVD_CMD_VIDEO_DECODE:
2361 case IV_CMD_RETRIEVE_MEMREC:
2362 case IVD_CMD_SET_DISPLAY_FRAME:
2363 case IVD_CMD_REL_DISPLAY_FRAME:
2364 case IVD_CMD_VIDEO_CTL:
2365 {
2366 if(ps_handle == NULL)
2367 {
2368 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2369 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2370 return IV_FAIL;
2371 }
2372
2373 if(ps_handle->u4_size != sizeof(iv_obj_t))
2374 {
2375 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2376 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2377 return IV_FAIL;
2378 }
2379 if(ps_handle->pv_fxns != impeg2d_api_function)
2380 {
2381 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2382 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2383 return IV_FAIL;
2384 }
2385
2386 if(ps_handle->pv_codec_handle == NULL)
2387 {
2388 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2389 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2390 return IV_FAIL;
2391 }
2392 }
2393 break;
2394 default:
2395 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2396 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2397 return IV_FAIL;
2398 }
2399
2400 switch(i4_cmd)
2401 {
2402 case IV_CMD_GET_NUM_MEM_REC:
2403 {
2404 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2405 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2406 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2407
2408 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2409 {
2410 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2411 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2412 return(IV_FAIL);
2413 }
2414
2415 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2416 {
2417 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2418 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2419 return(IV_FAIL);
2420 }
2421 }
2422 break;
2423 case IV_CMD_FILL_NUM_MEM_REC:
2424 {
2425 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2426 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2427 iv_mem_rec_t *ps_mem_rec;
2428
2429 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2430
2431 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2432 {
2433 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2434 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2435 return(IV_FAIL);
2436 }
2437
2438 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2439 {
2440 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2441 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2442 return(IV_FAIL);
2443 }
2444
2445 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2446 {
2447 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2448 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2449 return(IV_FAIL);
2450 }
2451
2452 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2453 {
2454 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2455 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2456 return(IV_FAIL);
2457 }
2458
2459 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2460 {
2461 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2462 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2463 return(IV_FAIL);
2464 }
2465
2466 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2467 {
2468 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2469 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2470 return(IV_FAIL);
2471 }
2472
2473 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2474 {
2475 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2476 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2477 return(IV_FAIL);
2478 }
2479
2480 /* check memrecords sizes are correct */
2481 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2482 for(i=0;i<NUM_MEM_RECORDS;i++)
2483 {
2484 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2485 {
2486 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2487 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2488 return IV_FAIL;
2489 }
2490 }
2491 }
2492 break;
2493
2494 case IV_CMD_INIT:
2495 {
2496 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2497 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2498 iv_mem_rec_t *ps_mem_rec;
2499 UWORD32 u4_tot_num_mem_recs;
2500
2501 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2502
2503 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2504 {
2505 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2506 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2507 return(IV_FAIL);
2508 }
2509
2510 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2511 {
2512 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2513 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2514 return(IV_FAIL);
2515 }
2516
2517 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2518
2519
2520
2521
2522 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2523 {
2524 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2525 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2526 return(IV_FAIL);
2527 }
2528
2529 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2530 {
2531 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2532 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2533 return(IV_FAIL);
2534 }
2535
2536 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2537 {
2538 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2539 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2540 return(IV_FAIL);
2541 }
2542
2543 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2544 {
2545 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2546 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2547 return(IV_FAIL);
2548 }
2549
2550 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2551 {
2552 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2553 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2554 return(IV_FAIL);
2555 }
2556
2557 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2558 {
2559 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2560 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2561 return(IV_FAIL);
2562 }
2563
2564 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2565 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2566 {
2567 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2568 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2569 return(IV_FAIL);
2570 }
2571
2572 /* verify number of mem records */
2573 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2574 {
2575 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2576 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2577 return IV_FAIL;
2578 }
2579
2580 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2581 /* verify wether first memrecord is handle or not */
2582 /*
2583 if(ps_mem_rec->pv_base != ps_handle)
2584 {
2585 // indicate the incorrect handle error
2586 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2587 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2588 return IV_FAIL;
2589 }
2590 */
2591 /* check memrecords sizes are correct */
2592 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2593 {
2594 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2595 {
2596 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2597 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2598 return IV_FAIL;
2599 }
2600 }
2601
2602 /* verify memtabs for overlapping regions */
2603 {
2604 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2605 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2606
2607
2608 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2609 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2610 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2611 {
2612 /* This array is populated to check memtab overlapp */
2613 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2614 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2615
2616 for(j = 0; j < i; j++)
2617 {
2618 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2619 {
2620 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2621 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2622 return IV_FAIL;
2623 }
2624
2625 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2626 {
2627 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2628 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2629 return IV_FAIL;
2630 }
2631
2632 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2633 {
2634 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2635 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2636 return IV_FAIL;
2637 }
2638 }
2639 }
2640 }
2641
2642
2643
2644
2645 {
2646 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2647
2648 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2649 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2650 IV_API_CALL_STATUS_T e_status;
2651 WORD32 i4_num_memrec;
2652 {
2653
2654 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2655 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2656
2657
2658 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2659 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2660
2661 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2662 impeg2d_api_function(NULL,
2663 (void *)&s_no_of_mem_rec_query_ip,
2664 (void *)&s_no_of_mem_rec_query_op);
2665
2666 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2667
2668
2669
2670 }
2671
2672
2673 /* initialize mem records array with sizes */
2674 for(i = 0; i < i4_num_memrec; i++)
2675 {
2676 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2677 }
2678
2679 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2680 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2681 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2682 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2683 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2684 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2685 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2686 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2687
2688
2689 e_status = impeg2d_api_function(NULL,
2690 (void *)&s_fill_mem_rec_ip,
2691 (void *)&s_fill_mem_rec_op);
2692 if(IV_FAIL == e_status)
2693 {
2694 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2695 return(IV_FAIL);
2696 }
2697
2698
2699
2700 for(i = 0; i < i4_num_memrec; i ++)
2701 {
2702 if(ps_mem_rec[i].pv_base == NULL)
2703 {
2704 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2705 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2706 return IV_FAIL;
2707 }
2708 #ifdef CHECK_ALIGN
2709
2710 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2711 {
2712 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2713 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2714 return IV_FAIL;
2715 }
2716 #endif //CHECK_ALIGN
2717 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2718 {
2719 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2720 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2721 return IV_FAIL;
2722 }
2723
2724 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2725 {
2726 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2727 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2728 return IV_FAIL;
2729 }
2730
2731 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2732 {
2733 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2734 {
2735 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2736 {
2737 continue;
2738 }
2739 }
2740 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2741 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2742 return IV_FAIL;
2743 }
2744 }
2745 }
2746
2747
2748 }
2749 break;
2750
2751 case IVD_CMD_GET_DISPLAY_FRAME:
2752 {
2753 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2754 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2755
2756 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2757
2758 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2759 {
2760 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2761 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2762 return(IV_FAIL);
2763 }
2764
2765 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2766 {
2767 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2768 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2769 return(IV_FAIL);
2770 }
2771
2772 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2773 {
2774 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2775 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2776 return IV_FAIL;
2777 }
2778
2779 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2780 {
2781 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2782 {
2783 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2784 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2785 return IV_FAIL;
2786 }
2787
2788 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2789 {
2790 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2791 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2792 return IV_FAIL;
2793 }
2794 /*
2795 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2796 {
2797 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2798 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2799 return IV_FAIL;
2800 }
2801 */
2802 }
2803 }
2804 break;
2805 case IVD_CMD_REL_DISPLAY_FRAME:
2806 {
2807 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2808 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2809
2810 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2811
2812 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2813 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2814 {
2815 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2816 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2817 return(IV_FAIL);
2818 }
2819
2820 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2821 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2822 {
2823 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2824 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2825 return(IV_FAIL);
2826 }
2827
2828 }
2829 break;
2830
2831
2832 case IVD_CMD_SET_DISPLAY_FRAME:
2833 {
2834 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2835 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2836 UWORD32 j, i;
2837
2838 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2839
2840 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2841 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2842 {
2843 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2844 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2845 return(IV_FAIL);
2846 }
2847
2848 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2849 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2850 {
2851 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2853 return(IV_FAIL);
2854 }
2855
2856 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2857 {
2858 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2859 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2860 return IV_FAIL;
2861 }
2862
2863 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2864 {
2865 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2866 {
2867 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2868 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2869 return IV_FAIL;
2870 }
2871
2872 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2873 {
2874 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2875 {
2876 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2877 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2878 return IV_FAIL;
2879 }
2880
2881 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2882 {
2883 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2884 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2885 return IV_FAIL;
2886 }
2887 }
2888 }
2889 }
2890 break;
2891
2892 case IVD_CMD_VIDEO_DECODE:
2893 {
2894 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2895 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2896
2897 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2898
2899 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2900 {
2901 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2902 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2903 return(IV_FAIL);
2904 }
2905
2906 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2907 {
2908 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2909 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2910 return(IV_FAIL);
2911 }
2912
2913 }
2914 break;
2915
2916 case IV_CMD_RETRIEVE_MEMREC:
2917 {
2918 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2919 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2920 iv_mem_rec_t *ps_mem_rec;
2921
2922 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2923
2924 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2925 {
2926 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2927 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2928 return(IV_FAIL);
2929 }
2930
2931 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2932 {
2933 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2934 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2935 return(IV_FAIL);
2936 }
2937
2938 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2939 /* check memrecords sizes are correct */
2940 for(i=0;i < NUM_MEM_RECORDS ; i++)
2941 {
2942 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2943 {
2944 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2945 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2946 return IV_FAIL;
2947 }
2948 }
2949 }
2950 break;
2951
2952 case IVD_CMD_VIDEO_CTL:
2953 {
2954 UWORD32 *pu4_ptr_cmd;
2955 UWORD32 u4_sub_command;
2956
2957 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2958 pu4_ptr_cmd += 2;
2959 u4_sub_command = *pu4_ptr_cmd;
2960
2961 switch(u4_sub_command)
2962 {
2963 case IVD_CMD_CTL_SETPARAMS:
2964 {
2965 impeg2d_ctl_set_config_ip_t *ps_ip;
2966 impeg2d_ctl_set_config_op_t *ps_op;
2967 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2968 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2969
2970 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2971
2972 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2973 {
2974 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2975 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2976 return IV_FAIL;
2977 }
2978 }
2979 case IVD_CMD_CTL_SETDEFAULT:
2980 {
2981 impeg2d_ctl_set_config_op_t *ps_op;
2982 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2983 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2984
2985 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2986 {
2987 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2988 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2989 return IV_FAIL;
2990 }
2991 }
2992 break;
2993
2994 case IVD_CMD_CTL_GETPARAMS:
2995 {
2996 impeg2d_ctl_getstatus_ip_t *ps_ip;
2997 impeg2d_ctl_getstatus_op_t *ps_op;
2998
2999 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
3000 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
3001
3002 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
3003
3004 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
3005 {
3006 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3007 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3008 return IV_FAIL;
3009 }
3010 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
3011 {
3012 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3013 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3014 return IV_FAIL;
3015 }
3016 }
3017 break;
3018
3019 case IVD_CMD_CTL_GETBUFINFO:
3020 {
3021 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
3022 impeg2d_ctl_getbufinfo_op_t *ps_op;
3023 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
3024 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
3025
3026 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
3027
3028 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
3029 {
3030 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3031 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3032 return IV_FAIL;
3033 }
3034 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
3035 {
3036 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3037 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3038 return IV_FAIL;
3039 }
3040 }
3041 break;
3042
3043 case IVD_CMD_CTL_GETVERSION:
3044 {
3045 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
3046 impeg2d_ctl_getversioninfo_op_t *ps_op;
3047 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
3048 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
3049
3050 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
3051
3052 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
3053 {
3054 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3055 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3056 return IV_FAIL;
3057 }
3058 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
3059 {
3060 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3061 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3062 return IV_FAIL;
3063 }
3064 }
3065 break;
3066
3067 case IVD_CMD_CTL_FLUSH:
3068 {
3069 impeg2d_ctl_flush_ip_t *ps_ip;
3070 impeg2d_ctl_flush_op_t *ps_op;
3071 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
3072 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
3073
3074 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
3075
3076 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
3077 {
3078 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3079 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3080 return IV_FAIL;
3081 }
3082 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
3083 {
3084 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3085 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3086 return IV_FAIL;
3087 }
3088 }
3089 break;
3090
3091 case IVD_CMD_CTL_RESET:
3092 {
3093 impeg2d_ctl_reset_ip_t *ps_ip;
3094 impeg2d_ctl_reset_op_t *ps_op;
3095 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
3096 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
3097
3098 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
3099
3100 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
3101 {
3102 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3103 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3104 return IV_FAIL;
3105 }
3106 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
3107 {
3108 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3109 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3110 return IV_FAIL;
3111 }
3112 }
3113 break;
3114
3115 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3116 {
3117 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
3118 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
3119
3120 ps_ip =
3121 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3122 ps_op =
3123 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3124
3125 if(ps_ip->u4_size
3126 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
3127 {
3128 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3129 ps_op->u4_error_code |=
3130 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3131 return IV_FAIL;
3132 }
3133
3134 if(ps_op->u4_size
3135 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
3136 {
3137 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3138 ps_op->u4_error_code |=
3139 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3140 return IV_FAIL;
3141 }
3142
3143 break;
3144 }
3145 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
3146 {
3147 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
3148 impeg2d_ctl_get_seq_info_op_t *ps_op;
3149
3150 ps_ip =
3151 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
3152 ps_op =
3153 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
3154
3155 if(ps_ip->u4_size
3156 != sizeof(impeg2d_ctl_get_seq_info_ip_t))
3157 {
3158 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3159 ps_op->u4_error_code |=
3160 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3161 return IV_FAIL;
3162 }
3163
3164 if(ps_op->u4_size
3165 != sizeof(impeg2d_ctl_get_seq_info_op_t))
3166 {
3167 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3168 ps_op->u4_error_code |=
3169 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3170 return IV_FAIL;
3171 }
3172
3173 break;
3174 }
3175 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
3176 {
3177 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
3178 impeg2d_ctl_set_num_cores_op_t *ps_op;
3179
3180 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
3181 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
3182
3183 if(ps_ip->u4_size
3184 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
3185 {
3186 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3187 ps_op->u4_error_code |=
3188 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3189 return IV_FAIL;
3190 }
3191
3192 if(ps_op->u4_size
3193 != sizeof(impeg2d_ctl_set_num_cores_op_t))
3194 {
3195 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3196 ps_op->u4_error_code |=
3197 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3198 return IV_FAIL;
3199 }
3200
3201 #ifdef MULTICORE
3202 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
3203 #else
3204 if(ps_ip->u4_num_cores != 1)
3205 #endif
3206 {
3207 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3208 return IV_FAIL;
3209 }
3210 break;
3211 }
3212 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
3213 {
3214 impeg2d_ctl_set_processor_ip_t *ps_ip;
3215 impeg2d_ctl_set_processor_op_t *ps_op;
3216
3217 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
3218 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
3219
3220 if(ps_ip->u4_size
3221 != sizeof(impeg2d_ctl_set_processor_ip_t))
3222 {
3223 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3224 ps_op->u4_error_code |=
3225 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3226 return IV_FAIL;
3227 }
3228
3229 if(ps_op->u4_size
3230 != sizeof(impeg2d_ctl_set_processor_op_t))
3231 {
3232 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3233 ps_op->u4_error_code |=
3234 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3235 return IV_FAIL;
3236 }
3237
3238 break;
3239 }
3240 default:
3241 break;
3242
3243 }
3244 }
3245 break;
3246
3247 default:
3248 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
3249 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
3250 return IV_FAIL;
3251 }
3252
3253
3254 }
3255
3256 return IV_SUCCESS;
3257 }
3258
3259 /*****************************************************************************/
3260 /* */
3261 /* Function Name : impeg2d_api_entity */
3262 /* */
3263 /* Description : */
3264 /* */
3265 /* Inputs : */
3266 /* Globals : <Does it use any global variables?> */
3267 /* Outputs : */
3268 /* Returns : void */
3269 /* */
3270 /* Issues : none */
3271 /* */
3272 /* Revision History: */
3273 /* */
3274 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3275 /* 22 10 2008 100356 Draft */
3276 /* */
3277 /*****************************************************************************/
3278
3279
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)3280 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
3281 void *pv_api_ip,
3282 void *pv_api_op)
3283 {
3284 iv_obj_t *ps_dec_handle;
3285 dec_state_t *ps_dec_state;
3286 dec_state_multi_core_t *ps_dec_state_multi_core;
3287
3288 impeg2d_video_decode_ip_t *ps_dec_ip;
3289
3290 impeg2d_video_decode_op_t *ps_dec_op;
3291 WORD32 bytes_remaining;
3292 pic_buf_t *ps_disp_pic;
3293
3294
3295
3296 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
3297 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
3298
3299 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
3300
3301 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3302 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3303 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3304
3305 ps_dec_handle = (iv_obj_t *)ps_dechdl;
3306
3307 if(ps_dechdl == NULL)
3308 {
3309 return(IV_FAIL);
3310 }
3311
3312
3313
3314 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
3315 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
3316
3317 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3318 if(0 == ps_dec_state->u4_share_disp_buf)
3319 {
3320 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3321 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3322 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3323 }
3324
3325 ps_dec_state->ps_disp_pic = NULL;
3326 ps_dec_state->i4_frame_decoded = 0;
3327 /*rest bytes consumed */
3328 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
3329
3330 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
3331
3332 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
3333 {
3334 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3335 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
3336 return IV_FAIL;
3337 }
3338
3339
3340 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
3341 {
3342 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
3343 return(IV_FAIL);
3344 }
3345
3346 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
3347 {
3348 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
3349 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
3350 }
3351
3352 if((1 != ps_dec_state->u2_decode_header) &&
3353 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm))
3354 {
3355 if(ps_dec_state->u1_flushfrm)
3356 {
3357 if(ps_dec_state->aps_ref_pics[1] != NULL)
3358 {
3359 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
3360 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
3361 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3362
3363 ps_dec_state->aps_ref_pics[1] = NULL;
3364 ps_dec_state->aps_ref_pics[0] = NULL;
3365
3366 }
3367 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3368 {
3369 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3370 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3371
3372 ps_dec_state->aps_ref_pics[0] = NULL;
3373 }
3374 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3375 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3376
3377 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3378
3379 ps_dec_state->ps_disp_pic = ps_disp_pic;
3380 if(ps_disp_pic == NULL)
3381 {
3382 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3383 }
3384 else
3385 {
3386 WORD32 fmt_conv;
3387 if(0 == ps_dec_state->u4_share_disp_buf)
3388 {
3389 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3390 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3391 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3392 fmt_conv = 1;
3393 }
3394 else
3395 {
3396 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3397 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3398 {
3399 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3400 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3401 fmt_conv = 0;
3402 }
3403 else
3404 {
3405 UWORD8 *pu1_buf;
3406
3407 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3408 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3409
3410 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3411 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3412 fmt_conv = 1;
3413 }
3414 }
3415
3416 if(fmt_conv == 1)
3417 {
3418 iv_yuv_buf_t *ps_dst;
3419
3420
3421 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3422 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame))
3423 {
3424 impeg2d_deinterlace(ps_dec_state,
3425 ps_disp_pic,
3426 ps_dst,
3427 0,
3428 ps_dec_state->u2_vertical_size);
3429
3430 }
3431 else
3432 {
3433 impeg2d_format_convert(ps_dec_state,
3434 ps_disp_pic,
3435 ps_dst,
3436 0,
3437 ps_dec_state->u2_vertical_size);
3438 }
3439 }
3440
3441 if(ps_dec_state->u4_deinterlace)
3442 {
3443 if(ps_dec_state->ps_deint_pic)
3444 {
3445 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3446 ps_dec_state->ps_deint_pic->i4_buf_id,
3447 MPEG2_BUF_MGR_DEINT);
3448 }
3449 ps_dec_state->ps_deint_pic = ps_disp_pic;
3450 }
3451 if(0 == ps_dec_state->u4_share_disp_buf)
3452 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3453
3454 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3455 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3456 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3457
3458 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3459 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3460
3461 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3462
3463 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3464
3465 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3466
3467 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3468 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3469 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3470
3471 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3472 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3473 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3474
3475 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3476 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3477 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3478 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3479
3480 switch(ps_dec_state->i4_chromaFormat)
3481 {
3482 case IV_YUV_420SP_UV:
3483 case IV_YUV_420SP_VU:
3484 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (((ps_dec_state->u2_horizontal_size + 1) >> 1) << 1);
3485 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3486 break;
3487 case IV_YUV_422ILE:
3488 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3489 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3490 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3491 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3492 break;
3493 default:
3494 break;
3495 }
3496
3497
3498 }
3499 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3500 {
3501 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3502 {
3503 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3504 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3505 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3506 ps_dec_state->u4_frm_buf_stride,
3507 ps_dec_state->u2_horizontal_size,
3508 ps_dec_state->u2_vertical_size,
3509 ps_dec_state->i4_chromaFormat,
3510 ps_dec_state->u2_horizontal_size,
3511 ps_dec_state->u2_vertical_size);
3512 }
3513 return(IV_SUCCESS);
3514 }
3515 else
3516 {
3517 ps_dec_state->u1_flushfrm = 0;
3518
3519 return(IV_FAIL);
3520 }
3521
3522 }
3523 else if(ps_dec_state->u1_flushfrm==0)
3524 {
3525 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3526 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3527 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3528 {
3529 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3530 return(IV_FAIL);
3531 }
3532
3533 if(1 == ps_dec_state->u4_share_disp_buf)
3534 {
3535 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3536 {
3537 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3538 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3539 return IV_FAIL;
3540 }
3541 }
3542
3543
3544 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3545
3546 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3547
3548 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3549
3550 if (0 == ps_dec_state->u4_frm_buf_stride)
3551 {
3552 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size);
3553 }
3554
3555 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3556 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3557 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3558
3559 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3560 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3561 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3562
3563 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3564 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3565 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3566 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3567
3568 switch(ps_dec_state->i4_chromaFormat)
3569 {
3570 case IV_YUV_420SP_UV:
3571 case IV_YUV_420SP_VU:
3572 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (((ps_dec_state->u2_horizontal_size + 1) >> 1) << 1);
3573 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3574 break;
3575 case IV_YUV_422ILE:
3576 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3577 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3578 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3579 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3580 break;
3581 default:
3582 break;
3583 }
3584
3585 if( ps_dec_state->u1_flushfrm == 0)
3586 {
3587 ps_dec_state->u1_flushcnt = 0;
3588
3589 ps_dec_state->ps_out_buf = &ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer;
3590 if (IV_SUCCESS != check_app_out_buf_size(ps_dec_state))
3591 {
3592 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
3593 return IV_FAIL;
3594 }
3595
3596 /*************************************************************************/
3597 /* Frame Decode */
3598 /*************************************************************************/
3599 ps_dec_state->u4_inp_ts = ps_dec_ip->s_ivd_video_decode_ip_t.u4_ts;
3600
3601 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3602
3603 if (IVD_ERROR_NONE ==
3604 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3605 {
3606 if(ps_dec_state->u1_first_frame_done == 0)
3607 {
3608 ps_dec_state->u1_first_frame_done = 1;
3609 }
3610
3611 if(ps_dec_state->ps_disp_pic)
3612 {
3613 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3614 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3615 {
3616 case I_PIC :
3617 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3618 break;
3619
3620 case P_PIC:
3621 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3622 break;
3623
3624 case B_PIC:
3625 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3626 break;
3627
3628 case D_PIC:
3629 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3630 break;
3631
3632 default :
3633 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3634 break;
3635 }
3636 }
3637 else
3638 {
3639 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3640 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3641 }
3642
3643 ps_dec_state->u4_num_frames_decoded++;
3644 }
3645 }
3646 else
3647 {
3648 ps_dec_state->u1_flushcnt++;
3649 }
3650 }
3651 if(ps_dec_state->ps_disp_pic)
3652 {
3653 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3654 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3655
3656 if(0 == ps_dec_state->u4_share_disp_buf)
3657 {
3658 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3659 }
3660 }
3661
3662 if(ps_dec_state->u4_deinterlace)
3663 {
3664 if(ps_dec_state->ps_deint_pic)
3665 {
3666 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3667 ps_dec_state->ps_deint_pic->i4_buf_id,
3668 MPEG2_BUF_MGR_DEINT);
3669 }
3670 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic;
3671 }
3672
3673 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3674 {
3675 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3676 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3677 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3678 ps_dec_state->u4_frm_buf_stride,
3679 ps_dec_state->u2_horizontal_size,
3680 ps_dec_state->u2_vertical_size,
3681 ps_dec_state->i4_chromaFormat,
3682 ps_dec_state->u2_horizontal_size,
3683 ps_dec_state->u2_vertical_size);
3684 }
3685
3686 }
3687
3688 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3689 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3690
3691
3692 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3693 return IV_FAIL;
3694 else
3695 return IV_SUCCESS;
3696 }
3697