1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <[email protected]>
25 * Wu Fengguang <[email protected]>
26 *
27 */
28
29 #include <unistd.h>
30 #include <stdlib.h>
31 #include <stdio.h>
32 #include <string.h>
33 #include <err.h>
34 #include <arpa/inet.h>
35 #include "intel_io.h"
36 #include "intel_reg.h"
37 #include "intel_chipset.h"
38 #include "drmtest.h"
39
40 static uint32_t devid;
41
42 static int aud_reg_base = 0; /* base address of audio registers */
43 static int disp_reg_base = 0; /* base address of display registers */
44
45 #define IS_HASWELL_PLUS(devid) (IS_HASWELL(devid) || IS_BROADWELL(devid))
46
47 #define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
48 #define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
49 #define REG_BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
50 #define REG_BIT(reg, n) REG_BITS(reg, n, n)
51
52 #define min_t(type, x, y) ({ \
53 type __min1 = (x); \
54 type __min2 = (y); \
55 __min1 < __min2 ? __min1 : __min2; })
56
57 #define OPNAME(names, index) \
58 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
59
60 #define set_aud_reg_base(base) (aud_reg_base = (base))
61
62 #define set_reg_base(base, audio_offset) \
63 do { \
64 disp_reg_base = (base); \
65 set_aud_reg_base((base) + (audio_offset)); \
66 } while (0)
67
68 #define dump_reg(reg, desc) \
69 do { \
70 dword = INREG(reg); \
71 printf("%-21s(%#x) 0x%08x %s\n", # reg, reg, dword, desc); \
72 } while (0)
73
74 #define dump_disp_reg(reg, desc) \
75 do { \
76 dword = INREG(disp_reg_base + reg); \
77 printf("%-21s(%#x) 0x%08x %s\n", # reg, reg, dword, desc); \
78 } while (0)
79
80 #define dump_aud_reg(reg, desc) \
81 do { \
82 dword = INREG(aud_reg_base + reg); \
83 printf("%-21s(%#x) 0x%08x %s\n", # reg, reg, dword, desc); \
84 } while (0)
85
86 #define read_aud_reg(reg) INREG(aud_reg_base + (reg))
87
get_num_pipes(void)88 static int get_num_pipes(void)
89 {
90 int num_pipes;
91
92 if (IS_VALLEYVIEW(devid))
93 num_pipes = 2; /* Valleyview is Gen 7 but only has 2 pipes */
94 else if (IS_G4X(devid) || IS_GEN5(devid))
95 num_pipes = 2;
96 else
97 num_pipes = 3;
98
99 return num_pipes;
100 }
101
102 static const char * const cts_m_value_index[] = {
103 [0] = "CTS",
104 [1] = "M",
105 };
106
107 static const char * const pixel_clock[] = {
108 [0] = "25.2 / 1.001 MHz",
109 [1] = "25.2 MHz",
110 [2] = "27 MHz",
111 [3] = "27 * 1.001 MHz",
112 [4] = "54 MHz",
113 [5] = "54 * 1.001 MHz",
114 [6] = "74.25 / 1.001 MHz",
115 [7] = "74.25 MHz",
116 [8] = "148.5 / 1.001 MHz",
117 [9] = "148.5 MHz",
118 [10] = "Reserved",
119 };
120
121 static const char * const power_state[] = {
122 [0] = "D0",
123 [1] = "D1",
124 [2] = "D2",
125 [3] = "D3",
126 };
127
128 static const char * const stream_type[] = {
129 [0] = "default samples",
130 [1] = "one bit stream",
131 [2] = "DST stream",
132 [3] = "MLP stream",
133 [4] = "Reserved",
134 };
135
136 static const char * const dip_port[] = {
137 [0] = "Reserved",
138 [1] = "Digital Port B",
139 [2] = "Digital Port C",
140 [3] = "Digital Port D",
141 };
142
143 static const char * const dip_type[] = {
144 [0] = "Audio DIP Disabled",
145 [1] = "Audio DIP Enabled",
146 };
147
148 static const char * const dip_gen1_state[] = {
149 [0] = "Generic 1 (ACP) DIP Disabled",
150 [1] = "Generic 1 (ACP) DIP Enabled",
151 };
152
153 static const char * const dip_gen2_state[] = {
154 [0] = "Generic 2 DIP Disabled",
155 [1] = "Generic 2 DIP Enabled",
156 };
157
158 static const char * const dip_index[] = {
159 [0] = "Audio DIP",
160 [1] = "ACP DIP",
161 [2] = "ISRC1 DIP",
162 [3] = "ISRC2 DIP",
163 [4] = "Reserved",
164 };
165
166 static const char * const dip_trans[] = {
167 [0] = "disabled",
168 [1] = "reserved",
169 [2] = "send once",
170 [3] = "best effort",
171 };
172
173 static const char * const video_dip_index[] = {
174 [0] = "AVI DIP",
175 [1] = "Vendor-specific DIP",
176 [2] = "Gamut Metadata DIP",
177 [3] = "Source Product Description DIP",
178 };
179
180 static const char * const video_dip_trans[] = {
181 [0] = "send once",
182 [1] = "send every vsync",
183 [2] = "send at least every other vsync",
184 [3] = "reserved",
185 };
186
187 static const char * const trans_to_port_sel[] = {
188 [0] = "no port",
189 [1] = "Digital Port B",
190 [2] = "Digital Port C",
191 [3] = "Digital Port D",
192 [4] = "reserved",
193 [5] = "reserved",
194 [6] = "reserved",
195 [7] = "reserved",
196 };
197
198 static const char * const ddi_mode[] = {
199 [0] = "HDMI mode",
200 [1] = "DVI mode",
201 [2] = "DP SST mode",
202 [3] = "DP MST mode",
203 [4] = "DP FDI mode",
204 [5] = "reserved",
205 [6] = "reserved",
206 [7] = "reserved",
207 };
208
209 static const char * const bits_per_color[] = {
210 [0] = "8 bpc",
211 [1] = "10 bpc",
212 [2] = "6 bpc",
213 [3] = "12 bpc",
214 [4] = "reserved",
215 [5] = "reserved",
216 [6] = "reserved",
217 [7] = "reserved",
218 };
219
220 static const char * const transcoder_select[] = {
221 [0] = "Transcoder A",
222 [1] = "Transcoder B",
223 [2] = "Transcoder C",
224 [3] = "reserved",
225 };
226
227 static const char * const dp_port_width[] = {
228 [0] = "x1 mode",
229 [1] = "x2 mode",
230 [2] = "reserved",
231 [3] = "x4 mode",
232 [4] = "reserved",
233 [5] = "reserved",
234 [6] = "reserved",
235 [7] = "reserved",
236 };
237
238 static const char * const sample_base_rate[] = {
239 [0] = "48 kHz",
240 [1] = "44.1 kHz",
241 };
242
243 static const char * const sample_base_rate_mult[] = {
244 [0] = "x1 (48 kHz, 44.1 kHz or less)",
245 [1] = "x2 (96 kHz, 88.2 kHz, 32 kHz)",
246 [2] = "x3 (144 kHz)",
247 [3] = "x4 (192 kHz, 176.4 kHz)",
248 [4] = "Reserved",
249 };
250
251 static const char * const sample_base_rate_divisor[] = {
252 [0] = "Divided by 1 (48 kHz, 44.1 kHz)",
253 [1] = "Divided by 2 (24 kHz, 22.05 kHz)",
254 [2] = "Divided by 3 (16 kHz, 32 kHz)",
255 [3] = "Divided by 4 (11.025 kHz)",
256 [4] = "Divided by 5 (9.6 kHz)",
257 [5] = "Divided by 6 (8 kHz)",
258 [6] = "Divided by 7",
259 [7] = "Divided by 8 (6 kHz)",
260 };
261
262 static const char * const connect_list_form[] = {
263 [0] = "Short Form",
264 [1] = "Long Form",
265 };
266
267
268 static const char * const bits_per_sample[] = {
269 [0] = "reserved",
270 [1] = "16 bits",
271 [2] = "24 bits",
272 [3] = "32 bits",
273 [4] = "20 bits",
274 [5] = "reserved",
275 };
276
277 static const char * const sdvo_hdmi_encoding[] = {
278 [0] = "SDVO",
279 [1] = "reserved",
280 [2] = "TMDS",
281 [3] = "reserved",
282 };
283
284 static const char * const n_index_value[] = {
285 [0] = "HDMI",
286 [1] = "DisplayPort",
287 };
288
289 static const char * const immed_result_valid[] = {
290 [0] = "No immediate response is available",
291 [1] = "Immediate response is available",
292 };
293
294 static const char * const immed_cmd_busy[] = {
295 [0] = "Can accept an immediate command",
296 [1] = "Immediate command is available",
297 };
298
299 static const char * const vanilla_dp12_en[] = {
300 [0] = "DP 1.2 features are disabled",
301 [1] = "DP 1.2 features are enabled",
302 };
303
304 static const char * const vanilla_3_widgets_en[] = {
305 [0] = "2nd & 3rd pin/convertor widgets are disabled",
306 [1] = "All three pin/convertor widgets are enabled",
307 };
308
309 static const char * const block_audio[] = {
310 [0] = "Allow audio data to reach the port",
311 [1] = "Block audio data from reaching the port",
312 };
313
314 static const char * const dis_eld_valid_pulse_trans[] = {
315 [0] = "Enable ELD valid pulse transition when unsol is disabled",
316 [1] = "Disable ELD valid pulse transition when unsol is disabled",
317 };
318
319 static const char * const dis_pd_pulse_trans[] = {
320 [0] = "Enable Presense Detect pulse transition when unsol is disabled",
321 [1] = "Disable Presense Detect pulse transition when unsol is disabled",
322 };
323
324 static const char * const dis_ts_delta_err[] = {
325 [0] = "Enable timestamp delta error for 32/44 KHz",
326 [1] = "Disable timestamp delta error for 32/44 KHz",
327 };
328
329 static const char * const dis_ts_fix_dp_hbr[] = {
330 [0] = "Enable timestamp fix for DP HBR",
331 [1] = "Disable timestamp fix for DP HBR",
332 };
333
334 static const char * const pattern_gen_8_ch_en[] = {
335 [0] = "Disable 8-channel pattern generator",
336 [1] = "Enable 8-channel pattern generator",
337 };
338
339 static const char * const pattern_gen_2_ch_en[] = {
340 [0] = "Disable 2-channel pattern generator",
341 [1] = "Enable 2-channel pattern generator",
342 };
343
344 static const char * const fabric_32_44_dis[] = {
345 [0] = "Allow sample fabrication for 32/44 KHz",
346 [1] = "Disable sample fabrication for 32/44 KHz",
347 };
348
349 static const char * const epss_dis[] = {
350 [0] = "Allow audio EPSS",
351 [1] = "Disable audio EPSS",
352 };
353
354 static const char * const ts_test_mode[] = {
355 [0] = "Default time stamp mode",
356 [1] = "Audio time stamp test mode for audio only feature",
357 };
358
359 static const char * const en_mmio_program[] = {
360 [0] = "Programming by HD-Audio Azalia",
361 [1] = "Programming by MMIO debug registers",
362 };
363
364 static const char * const sdi_operate_mode[] = {
365 [0] = "2T mode with sdi data held for 2 bit clocks",
366 [1] = "1T mode with sdi data held for 1 bit clock only",
367 };
368
369 static const char * const bclk_96mhz[] = {
370 [0] = "iDisplay audio link 96MHz bclk off",
371 [1] = "iDisplay audio link 96MHz bclk on",
372 };
373
374 static const char * const bclk_48mhz[] = {
375 [0] = "iDisplay audio link 48MHz bclk off",
376 [1] = "iDisplay audio link 48MHz bclk on",
377 };
378
379 static const char * const audio_dp_dip_status[] = {
380 [0] = "audfc dp fifo full",
381 [1] = "audfc dp fifo empty",
382 [2] = "audfc dp fifo overrun",
383 [3] = "audfc dip fifo full",
384 [4] = "audfc dp fifo empty cd",
385 [5] = "audfb dp fifo full",
386 [6] = "audfb dp fifo empty",
387 [7] = "audfb dp fifo overrun",
388 [8] = "audfb dip fifo full",
389 [9] = "audfb dp fifo empty cd",
390 [10] = "audfa dp fifo full",
391 [11] = "audfa dp fifo empty",
392 [12] = "audfa dp fifo overrun",
393 [13] = "audfa dip fifo full",
394 [14] = "audfa dp fifo empty cd",
395 [15] = "Pipe c audio overflow",
396 [16] = "Pipe b audio overflow",
397 [17] = "Pipe a audio overflow",
398 [31] = 0,
399 };
400
401 #undef TRANSCODER_A
402 #undef TRANSCODER_B
403 #undef TRANSCODER_C
404
405 enum {
406 TRANSCODER_A = 0,
407 TRANSCODER_B,
408 TRANSCODER_C,
409 };
410
411 enum {
412 PIPE_A = 0,
413 PIPE_B,
414 PIPE_C,
415 };
416
417 enum {
418 PORT_A = 0,
419 PORT_B,
420 PORT_C,
421 PORT_D,
422 PORT_E,
423 };
424
425 enum {
426 CONVERTER_1 = 0,
427 CONVERTER_2,
428 CONVERTER_3,
429 };
430
do_self_tests(void)431 static void do_self_tests(void)
432 {
433 if (REG_BIT(1, 0) != 1)
434 exit(1);
435 if (REG_BIT(0x80000000, 31) != 1)
436 exit(2);
437 if (REG_BITS(0xc0000000, 31, 30) != 3)
438 exit(3);
439 }
440
441 /*
442 * EagleLake registers
443 */
444 #define AUD_CONFIG 0x62000
445 #define AUD_DEBUG 0x62010
446 #define AUD_VID_DID 0x62020
447 #define AUD_RID 0x62024
448 #define AUD_SUBN_CNT 0x62028
449 #define AUD_FUNC_GRP 0x62040
450 #define AUD_SUBN_CNT2 0x62044
451 #define AUD_GRP_CAP 0x62048
452 #define AUD_PWRST 0x6204c
453 #define AUD_SUPPWR 0x62050
454 #define AUD_SID 0x62054
455 #define AUD_OUT_CWCAP 0x62070
456 #define AUD_OUT_PCMSIZE 0x62074
457 #define AUD_OUT_STR 0x62078
458 #define AUD_OUT_DIG_CNVT 0x6207c
459 #define AUD_OUT_CH_STR 0x62080
460 #define AUD_OUT_STR_DESC 0x62084
461 #define AUD_PINW_CAP 0x620a0
462 #define AUD_PIN_CAP 0x620a4
463 #define AUD_PINW_CONNLNG 0x620a8
464 #define AUD_PINW_CONNLST 0x620ac
465 #define AUD_PINW_CNTR 0x620b0
466 #define AUD_PINW_UNSOLRESP 0x620b8
467 #define AUD_CNTL_ST 0x620b4
468 #define AUD_PINW_CONFIG 0x620bc
469 #define AUD_HDMIW_STATUS 0x620d4
470 #define AUD_HDMIW_HDMIEDID 0x6210c
471 #define AUD_HDMIW_INFOFR 0x62118
472 #define AUD_CONV_CHCNT 0x62120
473 #define AUD_CTS_ENABLE 0x62128
474
475 #define VIDEO_DIP_CTL 0x61170
476 #define VIDEO_DIP_ENABLE (1<<31)
477 #define VIDEO_DIP_ENABLE_AVI (1<<21)
478 #define VIDEO_DIP_ENABLE_VENDOR (1<<22)
479 #define VIDEO_DIP_ENABLE_SPD (1<<24)
480 #define VIDEO_DIP_BUF_AVI (0<<19)
481 #define VIDEO_DIP_BUF_VENDOR (1<<19)
482 #define VIDEO_DIP_BUF_SPD (3<<19)
483 #define VIDEO_DIP_TRANS_ONCE (0<<16)
484 #define VIDEO_DIP_TRANS_1 (1<<16)
485 #define VIDEO_DIP_TRANS_2 (2<<16)
486
487 #define AUDIO_HOTPLUG_EN (1<<24)
488
489
dump_eaglelake(void)490 static void dump_eaglelake(void)
491 {
492 uint32_t dword;
493 int i;
494
495 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
496
497 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
498 dump_reg(SDVOB, "Digital Display Port B Control Register");
499 dump_reg(SDVOC, "Digital Display Port C Control Register");
500 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
501
502 dump_reg(AUD_CONFIG, "Audio Configuration");
503 dump_reg(AUD_DEBUG, "Audio Debug");
504 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
505 dump_reg(AUD_RID, "Audio Revision ID");
506 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
507 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
508 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
509 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
510 dump_reg(AUD_PWRST, "Audio Power State");
511 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
512 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
513 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
514 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
515 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
516 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
517 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
518 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
519 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
520 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
521 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
522 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
523 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
524 dump_reg(AUD_PINW_UNSOLRESP, "Audio Unsolicited Response Enable");
525 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
526 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
527 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
528 dump_reg(AUD_HDMIW_HDMIEDID, "Audio HDMI Data EDID Block");
529 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
530 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
531 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
532
533 printf("\nDetails:\n\n");
534
535 dword = INREG(AUD_VID_DID);
536 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
537 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
538
539 dword = INREG(AUD_RID);
540 printf("AUD_RID major revision\t\t\t0x%lx\n", REG_BITS(dword, 23, 20));
541 printf("AUD_RID minor revision\t\t\t0x%lx\n", REG_BITS(dword, 19, 16));
542 printf("AUD_RID revision id\t\t\t0x%lx\n", REG_BITS(dword, 15, 8));
543 printf("AUD_RID stepping id\t\t\t0x%lx\n", REG_BITS(dword, 7, 0));
544
545 dword = INREG(SDVOB);
546 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
547 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
548 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
549 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
550 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
551
552 dword = INREG(SDVOC);
553 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
554 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
555 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
556 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
557 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
558
559 dword = INREG(PORT_HOTPLUG_EN);
560 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", REG_BIT(dword, 29)),
561 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", REG_BIT(dword, 28)),
562 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", REG_BIT(dword, 27)),
563 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", REG_BIT(dword, 26)),
564 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", REG_BIT(dword, 25)),
565 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", REG_BIT(dword, 24)),
566 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", REG_BIT(dword, 23)),
567 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", REG_BIT(dword, 9)),
568
569 dword = INREG(VIDEO_DIP_CTL);
570 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", REG_BIT(dword, 31)),
571 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
572 REG_BITS(dword, 30, 29), dip_port[REG_BITS(dword, 30, 29)]);
573 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", REG_BIT(dword, 28));
574 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", REG_BIT(dword, 21));
575 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", REG_BIT(dword, 22));
576 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", REG_BIT(dword, 24));
577 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
578 REG_BITS(dword, 20, 19), video_dip_index[REG_BITS(dword, 20, 19)]);
579 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
580 REG_BITS(dword, 17, 16), video_dip_trans[REG_BITS(dword, 17, 16)]);
581 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", REG_BITS(dword, 11, 8));
582 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", REG_BITS(dword, 3, 0));
583
584 dword = INREG(AUD_CONFIG);
585 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", REG_BITS(dword, 19, 16),
586 OPNAME(pixel_clock, REG_BITS(dword, 19, 16)));
587 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", REG_BITS(dword, 2, 2));
588 printf("AUD_CONFIG professional use allowed\t%lu\n", REG_BIT(dword, 1));
589 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", REG_BIT(dword, 0));
590
591 dword = INREG(AUD_DEBUG);
592 printf("AUD_DEBUG function reset\t\t%lu\n", REG_BIT(dword, 0));
593
594 dword = INREG(AUD_SUBN_CNT);
595 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", REG_BITS(dword, 23, 16));
596 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", REG_BITS(dword, 7, 0));
597
598 dword = INREG(AUD_SUBN_CNT2);
599 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", REG_BITS(dword, 24, 16));
600 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", REG_BITS(dword, 7, 0));
601
602 dword = INREG(AUD_FUNC_GRP);
603 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", REG_BIT(dword, 8));
604 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", REG_BITS(dword, 7, 0));
605
606 dword = INREG(AUD_GRP_CAP);
607 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", REG_BIT(dword, 16));
608 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", REG_BITS(dword, 11, 8));
609 printf("AUD_GRP_CAP output delay\t\t%lu\n", REG_BITS(dword, 3, 0));
610
611 dword = INREG(AUD_PWRST);
612 printf("AUD_PWRST device power state\t\t%s\n",
613 power_state[REG_BITS(dword, 5, 4)]);
614 printf("AUD_PWRST device power state setting\t%s\n",
615 power_state[REG_BITS(dword, 1, 0)]);
616
617 dword = INREG(AUD_SUPPWR);
618 printf("AUD_SUPPWR support D0\t\t\t%lu\n", REG_BIT(dword, 0));
619 printf("AUD_SUPPWR support D1\t\t\t%lu\n", REG_BIT(dword, 1));
620 printf("AUD_SUPPWR support D2\t\t\t%lu\n", REG_BIT(dword, 2));
621 printf("AUD_SUPPWR support D3\t\t\t%lu\n", REG_BIT(dword, 3));
622
623 dword = INREG(AUD_OUT_CWCAP);
624 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", REG_BITS(dword, 23, 20));
625 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", REG_BITS(dword, 19, 16));
626 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
627 REG_BITS(dword, 15, 13) * 2 + REG_BIT(dword, 0) + 1);
628 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", REG_BIT(dword, 11));
629 printf("AUD_OUT_CWCAP power control\t\t%lu\n", REG_BIT(dword, 10));
630 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", REG_BIT(dword, 9));
631 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", REG_BIT(dword, 8));
632 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", REG_BIT(dword, 7));
633 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", REG_BIT(dword, 5));
634 printf("AUD_OUT_CWCAP format override\t\t%lu\n", REG_BIT(dword, 4));
635 printf("AUD_OUT_CWCAP amp param override\t%lu\n", REG_BIT(dword, 3));
636 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", REG_BIT(dword, 2));
637 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", REG_BIT(dword, 1));
638
639 dword = INREG(AUD_OUT_DIG_CNVT);
640 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", REG_BITS(dword, 14, 8));
641 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", REG_BIT(dword, 7));
642 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", REG_BIT(dword, 6));
643 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", REG_BIT(dword, 5));
644 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", REG_BIT(dword, 4));
645 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", REG_BIT(dword, 3));
646 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", REG_BIT(dword, 2));
647 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", REG_BIT(dword, 1));
648 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", REG_BIT(dword, 0));
649
650 dword = INREG(AUD_OUT_CH_STR);
651 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", REG_BITS(dword, 7, 4));
652 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", REG_BITS(dword, 3, 0));
653
654 dword = INREG(AUD_OUT_STR_DESC);
655 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", REG_BITS(dword, 3, 0) + 1);
656 printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n",
657 REG_BITS(dword, 6, 4), OPNAME(bits_per_sample, REG_BITS(dword, 6, 4)));
658
659 dword = INREG(AUD_PINW_CAP);
660 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", REG_BITS(dword, 23, 20));
661 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", REG_BITS(dword, 19, 16));
662 printf("AUD_PINW_CAP channel count\t\t%lu\n",
663 REG_BITS(dword, 15, 13) * 2 + REG_BIT(dword, 0) + 1);
664 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", REG_BIT(dword, 12));
665 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", REG_BIT(dword, 11));
666 printf("AUD_PINW_CAP power control\t\t%lu\n", REG_BIT(dword, 10));
667 printf("AUD_PINW_CAP digital\t\t\t%lu\n", REG_BIT(dword, 9));
668 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", REG_BIT(dword, 8));
669 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", REG_BIT(dword, 7));
670 printf("AUD_PINW_CAP mute\t\t\t%lu\n", REG_BIT(dword, 5));
671 printf("AUD_PINW_CAP format override\t\t%lu\n", REG_BIT(dword, 4));
672 printf("AUD_PINW_CAP amp param override\t\t%lu\n", REG_BIT(dword, 3));
673 printf("AUD_PINW_CAP out amp present\t\t%lu\n", REG_BIT(dword, 2));
674 printf("AUD_PINW_CAP in amp present\t\t%lu\n", REG_BIT(dword, 1));
675
676
677 dword = INREG(AUD_PIN_CAP);
678 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", REG_BIT(dword, 16));
679 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", REG_BIT(dword, 7));
680 printf("AUD_PIN_CAP output\t\t\t%lu\n", REG_BIT(dword, 4));
681 printf("AUD_PIN_CAP presence detect\t\t%lu\n", REG_BIT(dword, 2));
682
683 dword = INREG(AUD_PINW_CNTR);
684 printf("AUD_PINW_CNTR mute status\t\t%lu\n", REG_BIT(dword, 8));
685 printf("AUD_PINW_CNTR out enable\t\t%lu\n", REG_BIT(dword, 6));
686 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", REG_BIT(dword, 8));
687 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", REG_BIT(dword, 8));
688 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
689 REG_BITS(dword, 2, 0),
690 OPNAME(stream_type, REG_BITS(dword, 2, 0)));
691
692 dword = INREG(AUD_PINW_UNSOLRESP);
693 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", REG_BIT(dword, 31));
694
695 dword = INREG(AUD_CNTL_ST);
696 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", REG_BIT(dword, 21));
697 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", REG_BIT(dword, 22));
698 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", REG_BIT(dword, 23));
699 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
700 REG_BITS(dword, 30, 29), dip_port[REG_BITS(dword, 30, 29)]);
701 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
702 REG_BITS(dword, 20, 18), OPNAME(dip_index, REG_BITS(dword, 20, 18)));
703 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
704 REG_BITS(dword, 17, 16), dip_trans[REG_BITS(dword, 17, 16)]);
705 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", REG_BITS(dword, 3, 0));
706 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", REG_BIT(dword, 15));
707 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", REG_BIT(dword, 14));
708 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", REG_BIT(dword, 4));
709 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", REG_BITS(dword, 13, 9));
710 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", REG_BITS(dword, 8, 5));
711
712 dword = INREG(AUD_HDMIW_STATUS);
713 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", REG_BIT(dword, 31));
714 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", REG_BIT(dword, 30));
715 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", REG_BIT(dword, 29));
716 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", REG_BIT(dword, 28));
717
718 dword = INREG(AUD_CONV_CHCNT);
719 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", REG_BITS(dword, 15, 14));
720 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", REG_BITS(dword, 11, 8) + 1);
721
722 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
723 for (i = 0; i < 8; i++) {
724 OUTREG(AUD_CONV_CHCNT, i);
725 dword = INREG(AUD_CONV_CHCNT);
726 printf("\t\t\t\t\t[0x%x] %u => %lu\n", dword, i, REG_BITS(dword, 7, 4));
727 }
728
729 printf("AUD_HDMIW_HDMIEDID HDMI ELD:\n\t");
730 dword = INREG(AUD_CNTL_ST);
731 dword &= ~BITMASK(8, 5);
732 OUTREG(AUD_CNTL_ST, dword);
733 for (i = 0; i < REG_BITS(dword, 14, 10) / 4; i++)
734 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID)));
735 printf("\n");
736
737 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
738 dword = INREG(AUD_CNTL_ST);
739 dword &= ~BITMASK(20, 18);
740 dword &= ~BITMASK(3, 0);
741 OUTREG(AUD_CNTL_ST, dword);
742 for (i = 0; i < 8; i++)
743 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
744 printf("\n");
745 }
746
747 #undef AUD_RID
748 #undef AUD_VID_DID
749 #undef AUD_PWRST
750 #undef AUD_OUT_CH_STR
751 #undef AUD_HDMIW_STATUS
752
753 /*
754 * CougarPoint registers
755 */
756 #define DP_CTL_B 0xE4100
757 #define DP_CTL_C 0xE4200
758 #define DP_AUX_CTL_C 0xE4210
759 #define DP_AUX_TST_C 0xE4228
760 #define SPORT_DDI_CRC_C 0xE4250
761 #define SPORT_DDI_CRC_R 0xE4264
762 #define DP_CTL_D 0xE4300
763 #define DP_AUX_CTL_D 0xE4310
764 #define DP_AUX_TST_D 0xE4328
765 #define SPORT_DDI_CRC_CTL_D 0xE4350
766 #define AUD_CONFIG_A 0xE5000
767 #define AUD_MISC_CTRL_A 0xE5010
768 #define AUD_VID_DID 0xE5020
769 #define AUD_RID 0xE5024
770 #define AUD_CTS_ENABLE_A 0xE5028
771 #define AUD_PWRST 0xE504C
772 #define AUD_HDMIW_HDMIEDID_A 0xE5050
773 #define AUD_HDMIW_INFOFR_A 0xE5054
774 #define AUD_PORT_EN_HD_CFG 0xE507C
775 #define AUD_OUT_DIG_CNVT_A 0xE5080
776 #define AUD_OUT_STR_DESC_A 0xE5084
777 #define AUD_OUT_CH_STR 0xE5088
778 #define AUD_PINW_CONNLNG_LIST 0xE50A8
779 #define AUD_PINW_CONNLNG_SEL 0xE50AC
780 #define AUD_CNTL_ST_A 0xE50B4
781 #define AUD_CNTRL_ST2 0xE50C0
782 #define AUD_CNTRL_ST3 0xE50C4
783 #define AUD_HDMIW_STATUS 0xE50D4
784 #define AUD_CONFIG_B 0xE5100
785 #define AUD_MISC_CTRL_B 0xE5110
786 #define AUD_CTS_ENABLE_B 0xE5128
787 #define AUD_HDMIW_HDMIEDID_B 0xE5150
788 #define AUD_HDMIW_INFOFR_B 0xE5154
789 #define AUD_OUT_DIG_CNVT_B 0xE5180
790 #define AUD_OUT_STR_DESC_B 0xE5184
791 #define AUD_CNTL_ST_B 0xE51B4
792 #define AUD_CONFIG_C 0xE5200
793 #define AUD_MISC_CTRL_C 0xE5210
794 #define AUD_CTS_ENABLE_C 0xE5228
795 #define AUD_HDMIW_HDMIEDID_C 0xE5250
796 #define AUD_HDMIW_INFOFR_C 0xE5254
797 #define AUD_OUT_DIG_CNVT_C 0xE5280
798 #define AUD_OUT_STR_DESC_C 0xE5284
799 #define AUD_CNTL_ST_C 0xE52B4
800 #define AUD_CONFIG_D 0xE5300
801 #define AUD_MISC_CTRL_D 0xE5310
802 #define AUD_CTS_ENABLE_D 0xE5328
803 #define AUD_HDMIW_HDMIEDID_D 0xE5350
804 #define AUD_HDMIW_INFOFR_D 0xE5354
805 #define AUD_OUT_DIG_CNVT_D 0xE5380
806 #define AUD_OUT_STR_DESC_D 0xE5384
807 #define AUD_CNTL_ST_D 0xE53B4
808
809 #define VIDEO_DIP_CTL_A 0xE0200
810 #define VIDEO_DIP_CTL_B 0xE1200
811 #define VIDEO_DIP_CTL_C 0xE2200
812 #define VIDEO_DIP_CTL_D 0xE3200
813
814
dump_cpt(void)815 static void dump_cpt(void)
816 {
817 uint32_t dword;
818 int i;
819
820 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
821 dump_reg(HDMIC, "HDMI Port C Control");
822 dump_reg(HDMID, "HDMI Port D Control");
823 dump_reg(DP_CTL_B, "DisplayPort B Control");
824 dump_reg(DP_CTL_C, "DisplayPort C Control");
825 dump_reg(DP_CTL_D, "DisplayPort D Control");
826 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
827 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
828 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
829 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
830 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
831 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
832 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
833 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
834 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
835 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
836 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
837 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
838 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
839 dump_reg(AUD_RID, "Audio Revision ID");
840 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
841 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
842 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
843 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
844 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
845 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
846 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
847 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
848 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
849 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
850 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
851 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
852 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
853 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
854 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
855 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
856 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
857 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
858 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
859 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
860 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
861 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
862 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
863
864 printf("\nDetails:\n\n");
865
866 dword = INREG(VIDEO_DIP_CTL_A);
867 printf("VIDEO_DIP_CTL_A Enable_Graphics_DIP\t\t\t%ld\n", REG_BIT(dword, 31)),
868 printf("VIDEO_DIP_CTL_A GCP_DIP_enable\t\t\t\t%ld\n", REG_BIT(dword, 25)),
869 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable AVI\t\t%lu\n", REG_BIT(dword, 21));
870 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Vendor\t\t%lu\n", REG_BIT(dword, 22));
871 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Gamut\t\t%lu\n", REG_BIT(dword, 23));
872 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Source \t\t%lu\n", REG_BIT(dword, 24));
873 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
874 REG_BITS(dword, 20, 19), video_dip_index[REG_BITS(dword, 20, 19)]);
875 printf("VIDEO_DIP_CTL_A Video_DIP_frequency\t\t\t[0x%lx] %s\n",
876 REG_BITS(dword, 17, 16), video_dip_trans[REG_BITS(dword, 17, 16)]);
877 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_size\t\t\t%lu\n", REG_BITS(dword, 11, 8));
878 printf("VIDEO_DIP_CTL_A Video_DIP_access_address\t\t%lu\n", REG_BITS(dword, 3, 0));
879
880 dword = INREG(VIDEO_DIP_CTL_B);
881 printf("VIDEO_DIP_CTL_B Enable_Graphics_DIP\t\t\t%ld\n", REG_BIT(dword, 31)),
882 printf("VIDEO_DIP_CTL_B GCP_DIP_enable\t\t\t\t%ld\n", REG_BIT(dword, 25)),
883 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable AVI\t\t%lu\n", REG_BIT(dword, 21));
884 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Vendor\t\t%lu\n", REG_BIT(dword, 22));
885 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Gamut\t\t%lu\n", REG_BIT(dword, 23));
886 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Source \t\t%lu\n", REG_BIT(dword, 24));
887 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
888 REG_BITS(dword, 20, 19), video_dip_index[REG_BITS(dword, 20, 19)]);
889 printf("VIDEO_DIP_CTL_B Video_DIP_frequency\t\t\t[0x%lx] %s\n",
890 REG_BITS(dword, 17, 16), video_dip_trans[REG_BITS(dword, 17, 16)]);
891 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_size\t\t\t%lu\n", REG_BITS(dword, 11, 8));
892 printf("VIDEO_DIP_CTL_B Video_DIP_access_address\t\t%lu\n", REG_BITS(dword, 3, 0));
893
894 dword = INREG(VIDEO_DIP_CTL_C);
895 printf("VIDEO_DIP_CTL_C Enable_Graphics_DIP\t\t\t%ld\n", REG_BIT(dword, 31)),
896 printf("VIDEO_DIP_CTL_C GCP_DIP_enable\t\t\t\t%ld\n", REG_BIT(dword, 25)),
897 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable AVI\t\t%lu\n", REG_BIT(dword, 21));
898 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Vendor\t\t%lu\n", REG_BIT(dword, 22));
899 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Gamut\t\t%lu\n", REG_BIT(dword, 23));
900 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Source \t\t%lu\n", REG_BIT(dword, 24));
901 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
902 REG_BITS(dword, 20, 19), video_dip_index[REG_BITS(dword, 20, 19)]);
903 printf("VIDEO_DIP_CTL_C Video_DIP_frequency\t\t\t[0x%lx] %s\n",
904 REG_BITS(dword, 17, 16), video_dip_trans[REG_BITS(dword, 17, 16)]);
905 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_size\t\t\t%lu\n", REG_BITS(dword, 11, 8));
906 printf("VIDEO_DIP_CTL_C Video_DIP_access_address\t\t%lu\n", REG_BITS(dword, 3, 0));
907
908 dword = INREG(AUD_VID_DID);
909 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
910 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
911
912 dword = INREG(AUD_RID);
913 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", REG_BITS(dword, 23, 20));
914 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", REG_BITS(dword, 19, 16));
915 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", REG_BITS(dword, 15, 8));
916 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", REG_BITS(dword, 7, 0));
917
918 dword = INREG(HDMIB);
919 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
920 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
921 REG_BITS(dword, 30, 29), transcoder_select[REG_BITS(dword, 30, 29)]);
922 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", REG_BIT(dword, 7));
923 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", REG_BIT(dword, 5));
924 printf("HDMIB SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", REG_BIT(dword, 23));
925 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", REG_BIT(dword, 2));
926 printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n",
927 REG_BITS(dword, 11, 10), sdvo_hdmi_encoding[REG_BITS(dword, 11, 10)]);
928 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", REG_BIT(dword, 9) ? "HDMI" : "DVI");
929 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
930
931 dword = INREG(HDMIC);
932 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
933 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
934 REG_BITS(dword, 30, 29), transcoder_select[REG_BITS(dword, 30, 29)]);
935 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", REG_BIT(dword, 7));
936 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", REG_BIT(dword, 5));
937 printf("HDMIC SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", REG_BIT(dword, 23));
938 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", REG_BIT(dword, 2));
939 printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n",
940 REG_BITS(dword, 11, 10), sdvo_hdmi_encoding[REG_BITS(dword, 11, 10)]);
941 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", REG_BIT(dword, 9) ? "HDMI" : "DVI");
942 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
943
944 dword = INREG(HDMID);
945 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
946 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
947 REG_BITS(dword, 30, 29), transcoder_select[REG_BITS(dword, 30, 29)]);
948 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", REG_BIT(dword, 7));
949 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", REG_BIT(dword, 5));
950 printf("HDMID SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", REG_BIT(dword, 23));
951 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", REG_BIT(dword, 2));
952 printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n",
953 REG_BITS(dword, 11, 10), sdvo_hdmi_encoding[REG_BITS(dword, 11, 10)]);
954 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", REG_BIT(dword, 9) ? "HDMI" : "DVI");
955 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
956
957 dword = INREG(DP_CTL_B);
958 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", REG_BIT(dword, 31));
959 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
960 REG_BITS(dword, 21, 19), dp_port_width[REG_BITS(dword, 21, 19)]);
961 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", REG_BIT(dword, 2));
962 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", REG_BIT(dword, 5));
963 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", REG_BIT(dword, 6));
964
965 dword = INREG(DP_CTL_C);
966 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", REG_BIT(dword, 31));
967 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
968 REG_BITS(dword, 21, 19), dp_port_width[REG_BITS(dword, 21, 19)]);
969 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", REG_BIT(dword, 2));
970 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", REG_BIT(dword, 5));
971 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", REG_BIT(dword, 6));
972
973 dword = INREG(DP_CTL_D);
974 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", REG_BIT(dword, 31));
975 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
976 REG_BITS(dword, 21, 19), dp_port_width[REG_BITS(dword, 21, 19)]);
977 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", REG_BIT(dword, 2));
978 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", REG_BIT(dword, 5));
979 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", REG_BIT(dword, 6));
980
981 dword = INREG(AUD_CONFIG_A);
982 printf("AUD_CONFIG_A N_index_value\t\t\t\t[0x%lx] %s\n", REG_BIT(dword, 29),
983 n_index_value[REG_BIT(dword, 29)]);
984 printf("AUD_CONFIG_A N_programming_enable\t\t\t%lu\n", REG_BIT(dword, 28));
985 printf("AUD_CONFIG_A Upper_N_value\t\t\t\t0x%02lx\n", REG_BITS(dword, 27, 20));
986 printf("AUD_CONFIG_A Lower_N_value\t\t\t\t0x%03lx\n", REG_BITS(dword, 15, 4));
987 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 19, 16),
988 OPNAME(pixel_clock, REG_BITS(dword, 19, 16)));
989 printf("AUD_CONFIG_A Disable_NCTS\t\t\t\t%lu\n", REG_BIT(dword, 3));
990 dword = INREG(AUD_CONFIG_B);
991 printf("AUD_CONFIG_B N_index_value\t\t\t\t[0x%lx] %s\n", REG_BIT(dword, 29),
992 n_index_value[REG_BIT(dword, 29)]);
993 printf("AUD_CONFIG_B N_programming_enable\t\t\t%lu\n", REG_BIT(dword, 28));
994 printf("AUD_CONFIG_B Upper_N_value\t\t\t\t0x%02lx\n", REG_BITS(dword, 27, 20));
995 printf("AUD_CONFIG_B Lower_N_value\t\t\t\t0x%03lx\n", REG_BITS(dword, 15, 4));
996 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 19, 16),
997 OPNAME(pixel_clock, REG_BITS(dword, 19, 16)));
998 printf("AUD_CONFIG_B Disable_NCTS\t\t\t\t%lu\n", REG_BIT(dword, 3));
999 dword = INREG(AUD_CONFIG_C);
1000 printf("AUD_CONFIG_C N_index_value\t\t\t\t[0x%lx] %s\n", REG_BIT(dword, 29),
1001 n_index_value[REG_BIT(dword, 29)]);
1002 printf("AUD_CONFIG_C N_programming_enable\t\t\t%lu\n", REG_BIT(dword, 28));
1003 printf("AUD_CONFIG_C Upper_N_value\t\t\t\t0x%02lx\n", REG_BITS(dword, 27, 20));
1004 printf("AUD_CONFIG_C Lower_N_value\t\t\t\t0x%03lx\n", REG_BITS(dword, 15, 4));
1005 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 19, 16),
1006 OPNAME(pixel_clock, REG_BITS(dword, 19, 16)));
1007 printf("AUD_CONFIG_C Disable_NCTS\t\t\t\t%lu\n", REG_BIT(dword, 3));
1008
1009 dword = INREG(AUD_CTS_ENABLE_A);
1010 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", REG_BIT(dword, 20));
1011 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", REG_BIT(dword, 21) ? "CTS" : "M");
1012 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", REG_BITS(dword, 19, 0));
1013 dword = INREG(AUD_CTS_ENABLE_B);
1014 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", REG_BIT(dword, 20));
1015 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", REG_BIT(dword, 21) ? "CTS" : "M");
1016 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", REG_BITS(dword, 19, 0));
1017 dword = INREG(AUD_CTS_ENABLE_C);
1018 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", REG_BIT(dword, 20));
1019 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", REG_BIT(dword, 21) ? "CTS" : "M");
1020 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", REG_BITS(dword, 19, 0));
1021
1022 dword = INREG(AUD_MISC_CTRL_A);
1023 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", REG_BIT(dword, 2));
1024 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", REG_BIT(dword, 8));
1025 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", REG_BITS(dword, 7, 4));
1026 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", REG_BIT(dword, 1));
1027 dword = INREG(AUD_MISC_CTRL_B);
1028 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", REG_BIT(dword, 2));
1029 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", REG_BIT(dword, 8));
1030 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", REG_BITS(dword, 7, 4));
1031 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", REG_BIT(dword, 1));
1032 dword = INREG(AUD_MISC_CTRL_C);
1033 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", REG_BIT(dword, 2));
1034 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", REG_BIT(dword, 8));
1035 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", REG_BITS(dword, 7, 4));
1036 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", REG_BIT(dword, 1));
1037
1038 dword = INREG(AUD_PWRST);
1039 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[REG_BITS(dword, 27, 26)]);
1040 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[REG_BITS(dword, 25, 24)]);
1041 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 15, 14)]);
1042 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[REG_BITS(dword, 13, 12)]);
1043 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 19, 18)]);
1044 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[REG_BITS(dword, 17, 16)]);
1045 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[REG_BITS(dword, 23, 22)]);
1046 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[REG_BITS(dword, 21, 20)]);
1047 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 3, 2)]);
1048 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[REG_BITS(dword, 1, 0)]);
1049 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 7, 6)]);
1050 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[REG_BITS(dword, 5, 4)]);
1051 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 11, 10)]);
1052 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[REG_BITS(dword, 9, 8)]);
1053
1054 dword = INREG(AUD_PORT_EN_HD_CFG);
1055 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", REG_BIT(dword, 0));
1056 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", REG_BIT(dword, 1));
1057 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", REG_BIT(dword, 2));
1058 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", REG_BITS(dword, 7, 4));
1059 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", REG_BITS(dword, 11, 8));
1060 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", REG_BITS(dword, 15, 12));
1061 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 16));
1062 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 17));
1063 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 18));
1064 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 20));
1065 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 21));
1066 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 22));
1067
1068 dword = INREG(AUD_OUT_DIG_CNVT_A);
1069 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", REG_BIT(dword, 1));
1070 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", REG_BIT(dword, 2));
1071 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", REG_BIT(dword, 3));
1072 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", REG_BIT(dword, 4));
1073 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", REG_BIT(dword, 5));
1074 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", REG_BIT(dword, 6));
1075 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", REG_BIT(dword, 7));
1076 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", REG_BITS(dword, 14, 8));
1077 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n", REG_BITS(dword, 19, 16));
1078 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", REG_BITS(dword, 23, 20));
1079
1080 dword = INREG(AUD_OUT_DIG_CNVT_B);
1081 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", REG_BIT(dword, 1));
1082 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", REG_BIT(dword, 2));
1083 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", REG_BIT(dword, 3));
1084 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", REG_BIT(dword, 4));
1085 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", REG_BIT(dword, 5));
1086 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", REG_BIT(dword, 6));
1087 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", REG_BIT(dword, 7));
1088 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", REG_BITS(dword, 14, 8));
1089 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n", REG_BITS(dword, 19, 16));
1090 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", REG_BITS(dword, 23, 20));
1091
1092 dword = INREG(AUD_OUT_DIG_CNVT_C);
1093 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", REG_BIT(dword, 1));
1094 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", REG_BIT(dword, 2));
1095 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", REG_BIT(dword, 3));
1096 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", REG_BIT(dword, 4));
1097 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", REG_BIT(dword, 5));
1098 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", REG_BIT(dword, 6));
1099 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", REG_BIT(dword, 7));
1100 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", REG_BITS(dword, 14, 8));
1101 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n", REG_BITS(dword, 19, 16));
1102 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", REG_BITS(dword, 23, 20));
1103
1104 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1105 for (i = 0; i < 8; i++) {
1106 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1107 dword = INREG(AUD_OUT_CH_STR);
1108 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1109 1 + REG_BITS(dword, 3, 0),
1110 1 + REG_BITS(dword, 7, 4),
1111 1 + REG_BITS(dword, 15, 12),
1112 1 + REG_BITS(dword, 23, 20));
1113 }
1114
1115 dword = INREG(AUD_OUT_STR_DESC_A);
1116 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", REG_BITS(dword, 28, 27));
1117 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", REG_BITS(dword, 20, 16) + 1);
1118 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1119 REG_BITS(dword, 6, 4), OPNAME(bits_per_sample, REG_BITS(dword, 6, 4)));
1120 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + REG_BITS(dword, 3, 0));
1121
1122 dword = INREG(AUD_OUT_STR_DESC_B);
1123 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", REG_BITS(dword, 28, 27));
1124 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", REG_BITS(dword, 20, 16) + 1);
1125 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1126 REG_BITS(dword, 6, 4), OPNAME(bits_per_sample, REG_BITS(dword, 6, 4)));
1127 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + REG_BITS(dword, 3, 0));
1128
1129 dword = INREG(AUD_OUT_STR_DESC_C);
1130 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", REG_BITS(dword, 28, 27));
1131 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", REG_BITS(dword, 20, 16) + 1);
1132 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1133 REG_BITS(dword, 6, 4), OPNAME(bits_per_sample, REG_BITS(dword, 6, 4)));
1134 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + REG_BITS(dword, 3, 0));
1135
1136 dword = INREG(AUD_PINW_CONNLNG_SEL);
1137 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", REG_BITS(dword, 7, 0));
1138 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", REG_BITS(dword, 15, 8));
1139 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", REG_BITS(dword, 23, 16));
1140
1141 dword = INREG(AUD_CNTL_ST_A);
1142 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1143 REG_BITS(dword, 30, 29), dip_port[REG_BITS(dword, 30, 29)]);
1144 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", REG_BIT(dword, 21));
1145 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", REG_BIT(dword, 22));
1146 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", REG_BIT(dword, 23));
1147 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1148 REG_BITS(dword, 17, 16), dip_trans[REG_BITS(dword, 17, 16)]);
1149 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", REG_BIT(dword, 4));
1150 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", REG_BITS(dword, 14, 10));
1151
1152 dword = INREG(AUD_CNTL_ST_B);
1153 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1154 REG_BITS(dword, 30, 29), dip_port[REG_BITS(dword, 30, 29)]);
1155 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", REG_BIT(dword, 21));
1156 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", REG_BIT(dword, 22));
1157 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", REG_BIT(dword, 23));
1158 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1159 REG_BITS(dword, 17, 16), dip_trans[REG_BITS(dword, 17, 16)]);
1160 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", REG_BIT(dword, 4));
1161 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", REG_BITS(dword, 14, 10));
1162
1163 dword = INREG(AUD_CNTL_ST_C);
1164 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1165 REG_BITS(dword, 30, 29), dip_port[REG_BITS(dword, 30, 29)]);
1166 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t\t%lu\n", REG_BIT(dword, 21));
1167 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", REG_BIT(dword, 22));
1168 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", REG_BIT(dword, 23));
1169 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1170 REG_BITS(dword, 17, 16), dip_trans[REG_BITS(dword, 17, 16)]);
1171 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", REG_BIT(dword, 4));
1172 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", REG_BITS(dword, 14, 10));
1173
1174 dword = INREG(AUD_CNTRL_ST2);
1175 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", REG_BIT(dword, 1));
1176 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", REG_BIT(dword, 0));
1177 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", REG_BIT(dword, 5));
1178 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", REG_BIT(dword, 4));
1179 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", REG_BIT(dword, 9));
1180 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", REG_BIT(dword, 8));
1181
1182 dword = INREG(AUD_CNTRL_ST3);
1183 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", REG_BIT(dword, 3));
1184 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1185 REG_BITS(dword, 2, 0), trans_to_port_sel[REG_BITS(dword, 2, 0)]);
1186 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", REG_BIT(dword, 7));
1187 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1188 REG_BITS(dword, 6, 4), trans_to_port_sel[REG_BITS(dword, 6, 4)]);
1189 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", REG_BIT(dword, 11));
1190 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1191 REG_BITS(dword, 10, 8), trans_to_port_sel[REG_BITS(dword, 10, 8)]);
1192
1193 dword = INREG(AUD_HDMIW_STATUS);
1194 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 27));
1195 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 26));
1196 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 29));
1197 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 28));
1198 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 31));
1199 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 30));
1200 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", REG_BIT(dword, 25));
1201 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", REG_BIT(dword, 24));
1202
1203 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1204 dword = INREG(AUD_CNTL_ST_A);
1205 dword &= ~BITMASK(9, 5);
1206 OUTREG(AUD_CNTL_ST_A, dword);
1207 for (i = 0; i < REG_BITS(dword, 14, 10) / 4; i++)
1208 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1209 printf("\n");
1210
1211 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1212 dword = INREG(AUD_CNTL_ST_B);
1213 dword &= ~BITMASK(9, 5);
1214 OUTREG(AUD_CNTL_ST_B, dword);
1215 for (i = 0; i < REG_BITS(dword, 14, 10) / 4; i++)
1216 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1217 printf("\n");
1218
1219 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1220 dword = INREG(AUD_CNTL_ST_C);
1221 dword &= ~BITMASK(9, 5);
1222 OUTREG(AUD_CNTL_ST_C, dword);
1223 for (i = 0; i < REG_BITS(dword, 14, 10) / 4; i++)
1224 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1225 printf("\n");
1226
1227 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1228 dword = INREG(AUD_CNTL_ST_A);
1229 dword &= ~BITMASK(20, 18);
1230 dword &= ~BITMASK(3, 0);
1231 OUTREG(AUD_CNTL_ST_A, dword);
1232 for (i = 0; i < 8; i++)
1233 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1234 printf("\n");
1235
1236 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1237 dword = INREG(AUD_CNTL_ST_B);
1238 dword &= ~BITMASK(20, 18);
1239 dword &= ~BITMASK(3, 0);
1240 OUTREG(AUD_CNTL_ST_B, dword);
1241 for (i = 0; i < 8; i++)
1242 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1243 printf("\n");
1244
1245 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1246 dword = INREG(AUD_CNTL_ST_C);
1247 dword &= ~BITMASK(20, 18);
1248 dword &= ~BITMASK(3, 0);
1249 OUTREG(AUD_CNTL_ST_C, dword);
1250 for (i = 0; i < 8; i++)
1251 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1252 printf("\n");
1253
1254 }
1255
1256 /* Audio config registers of Ironlake */
1257 #undef AUD_CONFIG_A
1258 #undef AUD_CONFIG_B
1259 #undef AUD_MISC_CTRL_A
1260 #undef AUD_MISC_CTRL_B
1261 #undef AUD_VID_DID
1262 #undef AUD_RID
1263 #undef AUD_CTS_ENABLE_A
1264 #undef AUD_CTS_ENABLE_B
1265 #undef AUD_PWRST
1266 #undef AUD_HDMIW_HDMIEDID_A
1267 #undef AUD_HDMIW_HDMIEDID_B
1268 #undef AUD_HDMIW_INFOFR_A
1269 #undef AUD_HDMIW_INFOFR_B
1270 #undef AUD_PORT_EN_HD_CFG
1271 #undef AUD_OUT_DIG_CNVT_A
1272 #undef AUD_OUT_DIG_CNVT_B
1273 #undef AUD_OUT_STR_DESC_A
1274 #undef AUD_OUT_STR_DESC_B
1275 #undef AUD_OUT_CH_STR
1276 #undef AUD_PINW_CONNLNG_LIST
1277 #undef AUD_PINW_CONNLNG_SEL
1278 #undef AUD_CNTL_ST_A
1279 #undef AUD_CNTL_ST_B
1280 #undef AUD_CNTL_ST2
1281 #undef AUD_HDMIW_STATUS
1282
1283 #define PIPE_OFS 0x100
1284
1285 #define AUD_CONFIG_A 0x0
1286 #define AUD_CONFIG_B (AUD_CONFIG_A + PIPE_OFS)
1287 #define AUD_MISC_CTRL_A 0x010
1288 #define AUD_MISC_CTRL_B (AUD_MISC_CTRL_A + PIPE_OFS)
1289 #define AUD_VID_DID 0x020
1290 #define AUD_RID 0x024
1291 #define AUD_CTS_ENABLE_A 0x028
1292 #define AUD_CTS_ENABLE_B (AUD_CTS_ENABLE_A + PIPE_OFS)
1293 #define AUD_PWRST 0x04C
1294 #define AUD_HDMIW_HDMIEDID_A 0x050
1295 #define AUD_HDMIW_HDMIEDID_B (AUD_HDMIW_HDMIEDID_A + PIPE_OFS)
1296 #define AUD_HDMIW_INFOFR_A 0x054
1297 #define AUD_HDMIW_INFOFR_B (AUD_HDMIW_INFOFR_A + PIPE_OFS)
1298 #define AUD_PORT_EN_HD_CFG 0x07c
1299 #define AUD_OUT_DIG_CNVT_A 0x080
1300 #define AUD_OUT_DIG_CNVT_B (AUD_OUT_DIG_CNVT_A + PIPE_OFS)
1301 #define AUD_OUT_STR_DESC_A 0x084
1302 #define AUD_OUT_STR_DESC_B (AUD_OUT_STR_DESC_A + PIPE_OFS)
1303 #define AUD_OUT_CH_STR 0x088
1304 #define AUD_PINW_CONNLNG_LIST 0x0a8
1305 #define AUD_PINW_CONNLNG_SEL 0x0aC
1306 #define AUD_CNTL_ST_A 0x0b4
1307 #define AUD_CNTL_ST_B (AUD_CNTL_ST_A + PIPE_OFS)
1308 #define AUD_CNTL_ST2 0x0c0
1309 #define AUD_HDMIW_STATUS 0x0d4
1310 #define AUD_FREQ_CNTRL 0x900
1311
1312 /* Audio config registers of Haswell+ */
1313 #define AUD_TCA_CONFIG AUD_CONFIG_A
1314 #define AUD_TCB_CONFIG (AUD_TCA_CONFIG + PIPE_OFS)
1315 #define AUD_TCC_CONFIG (AUD_TCA_CONFIG + PIPE_OFS * 2)
1316 #define AUD_C1_MISC_CTRL AUD_MISC_CTRL_A
1317 #define AUD_C2_MISC_CTRL (AUD_MISC_CTRL_A + PIPE_OFS)
1318 #define AUD_C3_MISC_CTRL (AUD_MISC_CTRL_A + PIPE_OFS * 2)
1319 #define AUD_TCA_M_CTS_ENABLE AUD_CTS_ENABLE_A
1320 #define AUD_TCB_M_CTS_ENABLE (AUD_TCA_M_CTS_ENABLE + PIPE_OFS)
1321 #define AUD_TCC_M_CTS_ENABLE (AUD_TCA_M_CTS_ENABLE + PIPE_OFS * 2)
1322 #define AUD_TCA_EDID_DATA AUD_HDMIW_HDMIEDID_A
1323 #define AUD_TCB_EDID_DATA (AUD_TCA_EDID_DATA + PIPE_OFS)
1324 #define AUD_TCC_EDID_DATA (AUD_TCA_EDID_DATA + PIPE_OFS * 2)
1325 #define AUD_TCA_INFOFR AUD_HDMIW_INFOFR_A
1326 #define AUD_TCB_INFOFR (AUD_TCA_INFOFR + PIPE_OFS)
1327 #define AUD_TCC_INFOFR (AUD_TCA_INFOFR + PIPE_OFS * 2)
1328 #define AUD_PIPE_CONV_CFG AUD_PORT_EN_HD_CFG
1329 #define AUD_C1_DIG_CNVT AUD_OUT_DIG_CNVT_A
1330 #define AUD_C2_DIG_CNVT (AUD_C1_DIG_CNVT + PIPE_OFS)
1331 #define AUD_C3_DIG_CNVT (AUD_C1_DIG_CNVT + PIPE_OFS * 2)
1332 #define AUD_C1_STR_DESC AUD_OUT_STR_DESC_A
1333 #define AUD_C2_STR_DESC (AUD_C1_STR_DESC + PIPE_OFS)
1334 #define AUD_C3_STR_DESC (AUD_C1_STR_DESC + PIPE_OFS * 2)
1335 #define AUD_OUT_CHAN_MAP AUD_OUT_CH_STR
1336 #define AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH AUD_PINW_CONNLNG_LIST
1337 #define AUD_TCB_PIN_PIPE_CONN_ENTRY_LNGTH (AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH + PIPE_OFS)
1338 #define AUD_TCC_PIN_PIPE_CONN_ENTRY_LNGTH (AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH + PIPE_OFS * 2)
1339 #define AUD_PIPE_CONN_SEL_CTRL AUD_PINW_CONNLNG_SEL
1340 #define AUD_TCA_DIP_ELD_CTRL_ST AUD_CNTL_ST_A
1341 #define AUD_TCB_DIP_ELD_CTRL_ST (AUD_TCA_DIP_ELD_CTRL_ST + PIPE_OFS)
1342 #define AUD_TCC_DIP_ELD_CTRL_ST (AUD_TCA_DIP_ELD_CTRL_ST + PIPE_OFS * 2)
1343 #define AUD_PIN_ELD_CP_VLD AUD_CNTL_ST2
1344 #define AUD_HDMI_FIFO_STATUS AUD_HDMIW_STATUS
1345 #define AUD_ICOI 0xf00
1346 #define AUD_IRII 0xf04
1347 #define AUD_ICS 0xf08
1348 #define AUD_CHICKENBIT_REG 0xf10
1349 #define AUD_DP_DIP_STATUS 0xf20
1350 #define AUD_TCA_M_CTS 0xf44
1351 #define AUD_TCB_M_CTS 0xf54
1352 #define AUD_TCC_M_CTS 0xf64
1353 #define AUD_HDA_DMA_REG 0xe00
1354 #define AUD_HDA_LPIB0_REG 0xe04
1355 #define AUD_HDA_LPIB1_REG 0xe08
1356 #define AUD_HDA_LPIB2_REG 0xe0c
1357 #define AUD_HDA_EXTRA_REG 0xe10
1358 #define AUD_FPGA_CRC_CTL_A 0xf14
1359 #define AUD_FPGA_CRC_CTL_B 0xf24
1360 #define AUD_FPGA_CRC_CTL_C 0xf34
1361 #define AUD_FPGA_CRC_RESULT_A 0xf18
1362 #define AUD_FPGA_CRC_RESULT_B 0xf28
1363 #define AUD_FPGA_CRC_RESULT_C 0xf38
1364 #define AUD_DFT_MVAL_REG 0xe20
1365 #define AUD_DFT_NVAL_REG 0xe24
1366 #define AUD_DFT_LOAD_REG 0xe28
1367
1368 /* Common functions to dump audio registers */
1369 #define MAX_PREFIX_SIZE 128
1370
dump_aud_config(int index)1371 static void dump_aud_config(int index)
1372 {
1373 uint32_t dword;
1374 char prefix[MAX_PREFIX_SIZE];
1375
1376 if (!IS_HASWELL_PLUS(devid)) {
1377 dword = INREG(aud_reg_base + AUD_CONFIG_A + (index - PIPE_A) * 0x100);
1378 sprintf(prefix, "AUD_CONFIG_%c ", 'A' + index - PIPE_A);
1379 } else {
1380 dword = INREG(aud_reg_base + AUD_TCA_CONFIG + (index - TRANSCODER_A) * 0x100);
1381 sprintf(prefix, "AUD_TC%c_CONFIG", 'A' + index - TRANSCODER_A);
1382 }
1383
1384 printf("%s Disable_NCTS\t\t\t\t%lu\n", prefix, REG_BIT(dword, 3));
1385 printf("%s Lower_N_value\t\t\t\t0x%03lx\n", prefix, REG_BITS(dword, 15, 4));
1386 printf("%s Pixel_Clock_HDMI\t\t\t[0x%lx] %s\n", prefix, REG_BITS(dword, 19, 16),
1387 OPNAME(pixel_clock, REG_BITS(dword, 19, 16)));
1388 printf("%s Upper_N_value\t\t\t\t0x%02lx\n", prefix, REG_BITS(dword, 27, 20));
1389 printf("%s N_programming_enable\t\t\t%lu\n", prefix, REG_BIT(dword, 28));
1390 printf("%s N_index_value\t\t\t\t[0x%lx] %s\n", prefix, REG_BIT(dword, 29),
1391 OPNAME(n_index_value, REG_BIT(dword, 29)));
1392 }
1393
dump_aud_misc_control(int index)1394 static void dump_aud_misc_control(int index)
1395 {
1396 uint32_t dword;
1397 char prefix[MAX_PREFIX_SIZE];
1398
1399 if (!IS_HASWELL_PLUS(devid)) {
1400 dword = INREG(aud_reg_base + AUD_MISC_CTRL_A + (index - PIPE_A) * 0x100);
1401 sprintf(prefix, "AUD_MISC_CTRL_%c ", 'A' + index - PIPE_A);
1402 } else {
1403 dword = INREG(aud_reg_base + AUD_C1_MISC_CTRL + (index - CONVERTER_1) * 0x100);
1404 sprintf(prefix, "AUD_C%c_MISC_CTRL", '1' + index - CONVERTER_1);
1405 }
1406
1407 printf("%s Pro_Allowed\t\t\t\t%lu\n", prefix, REG_BIT(dword, 1));
1408 printf("%s Sample_Fabrication_EN_bit\t\t%lu\n", prefix, REG_BIT(dword, 2));
1409 printf("%s Output_Delay\t\t\t\t%lu\n", prefix, REG_BITS(dword, 7, 4));
1410 printf("%s Sample_present_Disable\t\t%lu\n", prefix, REG_BIT(dword, 8));
1411 }
1412
dump_aud_vendor_device_id(void)1413 static void dump_aud_vendor_device_id(void)
1414 {
1415 uint32_t dword;
1416
1417 dword = INREG(aud_reg_base + AUD_VID_DID);
1418 printf("AUD_VID_DID device id\t\t\t\t\t0x%lx\n", REG_BITS(dword, 15, 0));
1419 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%lx\n", REG_BITS(dword, 31, 16));
1420 }
1421
dump_aud_revision_id(void)1422 static void dump_aud_revision_id(void)
1423 {
1424 uint32_t dword;
1425
1426 dword = INREG(aud_reg_base + AUD_RID);
1427 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", REG_BITS(dword, 7, 0));
1428 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", REG_BITS(dword, 15, 8));
1429 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", REG_BITS(dword, 19, 16));
1430 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", REG_BITS(dword, 23, 20));
1431 }
1432
dump_aud_m_cts_enable(int index)1433 static void dump_aud_m_cts_enable(int index)
1434 {
1435 uint32_t dword;
1436 char prefix[MAX_PREFIX_SIZE];
1437
1438 if (!IS_HASWELL_PLUS(devid)) {
1439 dword = INREG(aud_reg_base + AUD_CTS_ENABLE_A + (index - PIPE_A) * 0x100);
1440 sprintf(prefix, "AUD_CTS_ENABLE_%c ", 'A' + index - PIPE_A);
1441 } else {
1442 dword = INREG(aud_reg_base + AUD_TCA_M_CTS_ENABLE + (index - TRANSCODER_A) * 0x100);
1443 sprintf(prefix, "AUD_TC%c_M_CTS_ENABLE", 'A' + index - TRANSCODER_A);
1444 }
1445
1446 printf("%s CTS_programming\t\t\t%#lx\n", prefix, REG_BITS(dword, 19, 0));
1447 printf("%s Enable_CTS_or_M_programming\t%lu\n", prefix, REG_BIT(dword, 20));
1448 printf("%s CTS_M value Index\t\t\t[0x%lx] %s\n",prefix, REG_BIT(dword, 21),
1449 OPNAME(cts_m_value_index, REG_BIT(dword, 21)));
1450 }
1451
dump_aud_power_state(void)1452 static void dump_aud_power_state(void)
1453 {
1454 uint32_t dword;
1455 int num_pipes;
1456
1457 dword = INREG(aud_reg_base + AUD_PWRST);
1458 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[REG_BITS(dword, 1, 0)]);
1459 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 3, 2)]);
1460 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[REG_BITS(dword, 5, 4)]);
1461 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 7, 6)]);
1462 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[REG_BITS(dword, 9, 8)]);
1463 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 11, 10)]);
1464
1465 if (!IS_HASWELL_PLUS(devid)) {
1466 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[REG_BITS(dword, 13, 12)]);
1467 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 15, 14)]);
1468 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[REG_BITS(dword, 17, 16)]);
1469 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 19, 18)]);
1470 } else {
1471 printf("AUD_PWRST Convertor1_Widget_Power_State_Requsted \t%s\n", power_state[REG_BITS(dword, 13, 12)]);
1472 printf("AUD_PWRST Convertor1_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 15, 14)]);
1473 printf("AUD_PWRST Convertor2_Widget_Power_State_Requested \t%s\n", power_state[REG_BITS(dword, 17, 16)]);
1474 printf("AUD_PWRST Convertor2_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 19, 18)]);
1475 }
1476
1477 num_pipes = get_num_pipes();
1478 if (num_pipes == 2) {
1479 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[REG_BITS(dword, 21, 20)]);
1480 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[REG_BITS(dword, 23, 22)]);
1481 } else { /* 3 pipes */
1482 if (!IS_HASWELL_PLUS(devid)) {
1483 printf("AUD_PWRST ConvertorC_Widget_Power_State_Requested \t%s\n", power_state[REG_BITS(dword, 21, 20)]);
1484 printf("AUD_PWRST ConvertorC_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 23, 22)]);
1485 } else {
1486 printf("AUD_PWRST Convertor3_Widget_Power_State_Requested \t%s\n", power_state[REG_BITS(dword, 21, 20)]);
1487 printf("AUD_PWRST Convertor3_Widget_Power_State_Current \t%s\n", power_state[REG_BITS(dword, 23, 22)]);
1488 }
1489 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[REG_BITS(dword, 25, 24)]);
1490 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[REG_BITS(dword, 27, 26)]);
1491 }
1492 }
1493
dump_aud_edid_data(int index)1494 static void dump_aud_edid_data(int index)
1495 {
1496 uint32_t dword;
1497 int i;
1498 int offset;
1499 int aud_ctrl_st, edid_data;
1500
1501 if (IS_HASWELL_PLUS(devid)) {
1502 offset = (index - TRANSCODER_A) * 0x100;
1503 aud_ctrl_st = aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset;
1504 edid_data = aud_reg_base + AUD_TCA_EDID_DATA + offset;
1505 printf("AUD_TC%c_EDID_DATA ELD:\n\t", 'A' + index - TRANSCODER_A);
1506 } else {
1507 offset = (index - PIPE_A) * 0x100;
1508 aud_ctrl_st = aud_reg_base + AUD_CNTL_ST_A + offset;
1509 edid_data = aud_reg_base + AUD_HDMIW_HDMIEDID_A + offset;
1510 printf("AUD_HDMIW_HDMIEDID_%c HDMI ELD:\n\t", 'A' + index - PIPE_A);
1511 }
1512
1513 dword = INREG(aud_ctrl_st);
1514 dword &= ~BITMASK(9, 5);
1515 OUTREG(aud_ctrl_st, dword);
1516 for (i = 0; i < REG_BITS(dword, 14, 10) / 4; i++)
1517 printf("%08x ", htonl(INREG(edid_data)));
1518 printf("\n");
1519 }
1520
dump_aud_infoframe(int index)1521 static void dump_aud_infoframe(int index)
1522 {
1523 uint32_t dword;
1524 int i;
1525 int offset;
1526 int aud_ctrl_st, info_frm;
1527
1528 if (IS_HASWELL_PLUS(devid)) {
1529 offset = (index - TRANSCODER_A) * 0x100;
1530 aud_ctrl_st = aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset;
1531 info_frm = aud_reg_base + AUD_TCA_INFOFR + offset;
1532 printf("AUD_TC%c_INFOFR audio Infoframe:\n\t", 'A' + index - TRANSCODER_A);
1533 } else {
1534 offset = (index - PIPE_A) * 0x100;
1535 aud_ctrl_st = aud_reg_base + AUD_CNTL_ST_A + offset;
1536 info_frm = aud_reg_base + AUD_HDMIW_INFOFR_A + offset;
1537 printf("AUD_HDMIW_INFOFR_%c HDMI audio Infoframe:\n\t", 'A' + index - PIPE_A);
1538 }
1539
1540 dword = INREG(aud_ctrl_st);
1541 dword &= ~BITMASK(20, 18);
1542 dword &= ~BITMASK(3, 0);
1543 OUTREG(aud_ctrl_st, dword);
1544 for (i = 0; i < 8; i++)
1545 printf("%08x ", htonl(INREG(info_frm)));
1546 printf("\n");
1547 }
1548
dump_aud_port_en_hd_cfg(void)1549 static void dump_aud_port_en_hd_cfg(void)
1550 {
1551 uint32_t dword;
1552 int num_pipes = get_num_pipes();
1553
1554 dword = INREG(aud_reg_base + AUD_PORT_EN_HD_CFG);
1555 if (num_pipes == 2) {
1556 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", REG_BIT(dword, 0));
1557 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", REG_BIT(dword, 1));
1558 printf("AUD_PORT_EN_HD_CFG Convertor_A_Stream_ID\t\t%lu\n", REG_BITS(dword, 7, 4));
1559 printf("AUD_PORT_EN_HD_CFG Convertor_B_Stream_ID\t\t%lu\n", REG_BITS(dword, 11, 8));
1560
1561 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 12));
1562 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 13));
1563 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 14));
1564 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 16));
1565 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 17));
1566 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 18));
1567 } else { /* three pipes */
1568 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", REG_BIT(dword, 0));
1569 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", REG_BIT(dword, 1));
1570 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", REG_BIT(dword, 2));
1571 printf("AUD_PORT_EN_HD_CFG Convertor_A_Stream_ID\t\t%lu\n", REG_BITS(dword, 7, 4));
1572 printf("AUD_PORT_EN_HD_CFG Convertor_B_Stream_ID\t\t%lu\n", REG_BITS(dword, 11, 8));
1573 printf("AUD_PORT_EN_HD_CFG Convertor_C_Stream_ID\t\t%lu\n", REG_BITS(dword, 15, 12));
1574
1575 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 16));
1576 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 17));
1577 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 18));
1578 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 20));
1579 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 21));
1580 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 22));
1581 }
1582 }
1583
dump_aud_pipe_conv_cfg(void)1584 static void dump_aud_pipe_conv_cfg(void)
1585 {
1586 uint32_t dword;
1587
1588 dword = INREG(aud_reg_base + AUD_PIPE_CONV_CFG);
1589 printf("AUD_PIPE_CONV_CFG Convertor_1_Digen\t\t\t%lu\n", REG_BIT(dword, 0));
1590 printf("AUD_PIPE_CONV_CFG Convertor_2_Digen\t\t\t%lu\n", REG_BIT(dword, 1));
1591 printf("AUD_PIPE_CONV_CFG Convertor_3_Digen\t\t\t%lu\n", REG_BIT(dword, 2));
1592 printf("AUD_PIPE_CONV_CFG Convertor_1_Stream_ID\t\t%lu\n", REG_BITS(dword, 7, 4));
1593 printf("AUD_PIPE_CONV_CFG Convertor_2_Stream_ID\t\t%lu\n", REG_BITS(dword, 11, 8));
1594 printf("AUD_PIPE_CONV_CFG Convertor_3_Stream_ID\t\t%lu\n", REG_BITS(dword, 15, 12));
1595
1596 printf("AUD_PIPE_CONV_CFG Port_B_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 16));
1597 printf("AUD_PIPE_CONV_CFG Port_C_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 17));
1598 printf("AUD_PIPE_CONV_CFG Port_D_Out_Enable\t\t\t%lu\n", REG_BIT(dword, 18));
1599 printf("AUD_PIPE_CONV_CFG Port_B_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 20));
1600 printf("AUD_PIPE_CONV_CFG Port_C_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 21));
1601 printf("AUD_PIPE_CONV_CFG Port_D_Amp_Mute_Status\t\t%lu\n", REG_BIT(dword, 22));
1602 }
1603
dump_aud_dig_cnvt(int index)1604 static void dump_aud_dig_cnvt(int index)
1605 {
1606 uint32_t dword;
1607 char prefix[MAX_PREFIX_SIZE];
1608
1609 if (!IS_HASWELL_PLUS(devid)) {
1610 dword = INREG(aud_reg_base + AUD_OUT_DIG_CNVT_A + (index - PIPE_A) * 0x100);
1611 sprintf(prefix, "AUD_OUT_DIG_CNVT_%c", 'A' + index - PIPE_A);
1612 } else {
1613 dword = INREG(aud_reg_base + AUD_C1_DIG_CNVT + (index - CONVERTER_1) * 0x100);
1614 sprintf(prefix, "AUD_C%c_DIG_CNVT ", '1' + index - CONVERTER_1);
1615 }
1616
1617 printf("%s V\t\t\t\t\t%lu\n", prefix, REG_BIT(dword, 1));
1618 printf("%s VCFG\t\t\t\t%lu\n", prefix, REG_BIT(dword, 2));
1619 printf("%s PRE\t\t\t\t\t%lu\n", prefix, REG_BIT(dword, 3));
1620 printf("%s Copy\t\t\t\t%lu\n", prefix, REG_BIT(dword, 4));
1621 printf("%s NonAudio\t\t\t\t%lu\n", prefix, REG_BIT(dword, 5));
1622 printf("%s PRO\t\t\t\t\t%lu\n", prefix, REG_BIT(dword, 6));
1623 printf("%s Level\t\t\t\t%lu\n", prefix, REG_BIT(dword, 7));
1624 printf("%s Category_Code\t\t\t%lu\n", prefix, REG_BITS(dword, 14, 8));
1625 printf("%s Lowest_Channel_Number\t\t%lu\n", prefix, REG_BITS(dword, 19, 16));
1626 printf("%s Stream_ID\t\t\t\t%lu\n", prefix, REG_BITS(dword, 23, 20));
1627 }
1628
dump_aud_str_desc(int index)1629 static void dump_aud_str_desc(int index)
1630 {
1631 uint32_t dword;
1632 char prefix[MAX_PREFIX_SIZE];
1633 uint32_t rate;
1634
1635 if (!IS_HASWELL_PLUS(devid)) {
1636 dword = INREG(aud_reg_base + AUD_OUT_STR_DESC_A + (index - PIPE_A) * 0x100);
1637 sprintf(prefix, "AUD_OUT_STR_DESC_%c", 'A' + index - PIPE_A);
1638 } else {
1639 dword = INREG(aud_reg_base + AUD_C1_STR_DESC + (index - CONVERTER_1) * 0x100);
1640 sprintf(prefix, "AUD_C%c_STR_DESC ", '1' + index - CONVERTER_1);
1641 }
1642
1643 printf("%s Number_of_Channels_in_a_Stream\t%lu\n", prefix, REG_BITS(dword, 3, 0) + 1);
1644 printf("%s Bits_per_Sample\t\t\t[%#lx] %s\n", prefix, REG_BITS(dword, 6, 4),
1645 OPNAME(bits_per_sample, REG_BITS(dword, 6, 4)));
1646
1647 printf("%s Sample_Base_Rate_Divisor\t\t[%#lx] %s\n", prefix, REG_BITS(dword, 10, 8),
1648 OPNAME(sample_base_rate_divisor, REG_BITS(dword, 10, 8)));
1649 printf("%s Sample_Base_Rate_Mult\t\t[%#lx] %s\n", prefix, REG_BITS(dword, 13, 11),
1650 OPNAME(sample_base_rate_mult, REG_BITS(dword, 13, 11)));
1651 printf("%s Sample_Base_Rate\t\t\t[%#lx] %s\t", prefix, REG_BIT(dword, 14),
1652 OPNAME(sample_base_rate, REG_BIT(dword, 14)));
1653 rate = (REG_BIT(dword, 14) ? 44100 : 48000) * (REG_BITS(dword, 13, 11) + 1)
1654 /(REG_BITS(dword, 10, 8) + 1);
1655 printf("=> Sample Rate %d Hz\n", rate);
1656
1657 printf("%s Convertor_Channel_Count\t\t%lu\n", prefix, REG_BITS(dword, 20, 16) + 1);
1658
1659 if (!IS_HASWELL_PLUS(devid))
1660 printf("%s HBR_enable\t\t\t\t%lu\n", prefix, REG_BITS(dword, 28, 27));
1661 }
1662
1663 #define dump_aud_out_ch_str dump_aud_out_chan_map
dump_aud_out_chan_map(void)1664 static void dump_aud_out_chan_map(void)
1665 {
1666 uint32_t dword;
1667 int i;
1668
1669 printf("AUD_OUT_CHAN_MAP Converter_Channel_MAP PORTB PORTC PORTD\n");
1670 for (i = 0; i < 8; i++) {
1671 OUTREG(aud_reg_base + AUD_OUT_CHAN_MAP, i | (i << 8) | (i << 16));
1672 dword = INREG(aud_reg_base + AUD_OUT_CHAN_MAP);
1673 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1674 1 + REG_BITS(dword, 3, 0),
1675 1 + REG_BITS(dword, 7, 4),
1676 1 + REG_BITS(dword, 15, 12),
1677 1 + REG_BITS(dword, 23, 20));
1678 }
1679 }
1680
dump_aud_connect_list(void)1681 static void dump_aud_connect_list(void)
1682 {
1683 uint32_t dword;
1684 char prefix[MAX_PREFIX_SIZE];
1685
1686 dword = INREG(aud_reg_base + AUD_PINW_CONNLNG_LIST);
1687 sprintf(prefix, "AUD_PINW_CONNLNG_LIST");
1688
1689 printf("%s Connect_List_Length\t\t%lu\n", prefix, REG_BITS(dword, 6, 0));
1690 printf("%s Form \t\t\t\t[%#lx] %s\n", prefix, REG_BIT(dword, 7),
1691 OPNAME(connect_list_form, REG_BIT(dword, 7)));
1692 printf("%s Connect_List_Entry\t\t%lu, %lu\n", prefix, REG_BITS(dword, 15, 8), REG_BITS(dword, 23, 16));
1693 }
1694
dump_aud_connect_select(void)1695 static void dump_aud_connect_select(void)
1696 {
1697 uint32_t dword;
1698 char prefix[MAX_PREFIX_SIZE];
1699
1700 if (IS_HASWELL_PLUS(devid)) {
1701 dword = INREG(aud_reg_base + AUD_PIPE_CONN_SEL_CTRL);
1702 sprintf(prefix, "AUD_PIPE_CONN_SEL_CTRL");
1703
1704 } else {
1705 dword = INREG(aud_reg_base + AUD_PINW_CONNLNG_SEL);
1706 sprintf(prefix, "AUD_PINW_CONNLNG_SEL ");
1707 }
1708
1709 printf("%s Connection_select_Port_B\t%#lx\n", prefix, REG_BITS(dword, 7, 0));
1710 printf("%s Connection_select_Port_C\t%#lx\n", prefix, REG_BITS(dword, 15, 8));
1711 printf("%s Connection_select_Port_D\t%#lx\n", prefix, REG_BITS(dword, 23, 16));
1712 }
1713
dump_aud_ctrl_state(int index)1714 static void dump_aud_ctrl_state(int index)
1715 {
1716 uint32_t dword;
1717 int offset;
1718
1719 if (IS_HASWELL_PLUS(devid)) {
1720 offset = (index - TRANSCODER_A) * 0x100;
1721 dword = INREG(aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset);
1722 printf("Audio DIP and ELD control state for Transcoder %c\n", 'A' + index - TRANSCODER_A);
1723 } else {
1724 offset = (index - PIPE_A) * 0x100;
1725 dword = INREG(aud_reg_base + AUD_CNTL_ST_A + offset);
1726 printf("Audio control state - Pipe %c\n", 'A' + index - PIPE_A);
1727 }
1728
1729 printf("\tELD_ACK\t\t\t\t\t\t%lu\n", REG_BIT(dword, 4));
1730 printf("\tELD_buffer_size\t\t\t\t\t%lu\n", REG_BITS(dword, 14, 10));
1731 printf("\tDIP_transmission_frequency\t\t\t[0x%lx] %s\n", REG_BITS(dword, 17, 16),
1732 dip_trans[REG_BITS(dword, 17, 16)]);
1733 printf("\tDIP Buffer Index \t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 20, 18),
1734 dip_index[REG_BITS(dword, 20, 18)]);
1735 printf("\tAudio DIP type enable status\t\t\t[0x%04lx] %s, %s, %s\n", REG_BITS(dword, 24, 21),
1736 dip_type[REG_BIT(dword, 21)], dip_gen1_state[REG_BIT(dword, 22)], dip_gen2_state[REG_BIT(dword, 23)]);
1737 printf("\tAudio DIP port select\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 30, 29),
1738 dip_port[REG_BITS(dword, 30, 29)]);
1739 printf("\n");
1740 }
1741
dump_aud_ctrl_state2(void)1742 static void dump_aud_ctrl_state2(void)
1743 {
1744 uint32_t dword;
1745
1746 dword = INREG(aud_reg_base + AUD_CNTL_ST2);
1747 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", REG_BIT(dword, 0));
1748 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", REG_BIT(dword, 1));
1749 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", REG_BIT(dword, 4));
1750 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", REG_BIT(dword, 5));
1751 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", REG_BIT(dword, 8));
1752 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", REG_BIT(dword, 9));
1753 }
1754
1755 /* for hsw+ */
dump_aud_eld_cp_vld(void)1756 static void dump_aud_eld_cp_vld(void)
1757 {
1758 uint32_t dword;
1759
1760 dword = INREG(aud_reg_base + AUD_PIN_ELD_CP_VLD);
1761 printf("AUD_PIN_ELD_CP_VLD Transcoder_A ELD_valid\t\t%lu\n", REG_BIT(dword, 0));
1762 printf("AUD_PIN_ELD_CP_VLD Transcoder_A CP_Ready \t\t%lu\n", REG_BIT(dword, 1));
1763 printf("AUD_PIN_ELD_CP_VLD Transcoder_A Out_enable\t\t%lu\n", REG_BIT(dword, 2));
1764 printf("AUD_PIN_ELD_CP_VLD Transcoder_A Inactive\t\t%lu\n", REG_BIT(dword, 3));
1765 printf("AUD_PIN_ELD_CP_VLD Transcoder_B ELD_valid\t\t%lu\n", REG_BIT(dword, 4));
1766 printf("AUD_PIN_ELD_CP_VLD Transcoder_B CP_Ready\t\t%lu\n", REG_BIT(dword, 5));
1767 printf("AUD_PIN_ELD_CP_VLD Transcoder_B OUT_enable\t\t%lu\n", REG_BIT(dword, 6));
1768 printf("AUD_PIN_ELD_CP_VLD Transcoder_B Inactive\t\t%lu\n", REG_BIT(dword, 7));
1769 printf("AUD_PIN_ELD_CP_VLD Transcoder_C ELD_valid\t\t%lu\n", REG_BIT(dword, 8));
1770 printf("AUD_PIN_ELD_CP_VLD Transcoder_C CP_Ready\t\t%lu\n", REG_BIT(dword, 9));
1771 printf("AUD_PIN_ELD_CP_VLD Transcoder_C OUT_enable\t\t%lu\n", REG_BIT(dword, 10));
1772 printf("AUD_PIN_ELD_CP_VLD Transcoder_C Inactive\t\t%lu\n", REG_BIT(dword, 11));
1773 }
1774
dump_aud_hdmi_status(void)1775 static void dump_aud_hdmi_status(void)
1776 {
1777 uint32_t dword;
1778
1779 dword = INREG(aud_reg_base + AUD_HDMIW_STATUS);
1780 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", REG_BIT(dword, 24));
1781 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", REG_BIT(dword, 25));
1782 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 28));
1783 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 29));
1784 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 30));
1785 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 31));
1786 }
1787
1788 /*
1789 * Display registers of Ironlake and Valleyview
1790 */
1791 #undef DP_CTL_B
1792 #undef DP_CTL_C
1793 #undef DP_CTL_D
1794
1795 #define DP_CTL_B 0x4100
1796 #define DP_CTL_C 0x4200
1797 #define DP_CTL_D 0x4300
1798
1799 /* ILK HDMI port ctrl */
1800 #define HDMI_CTL_B 0x1140
1801 #define HDMI_CTL_C 0x1150
1802 #define HDMI_CTL_D 0x1160
1803 #define BSW_HDMI_CTL_B 0x1140
1804 #define BSW_HDMI_CTL_C 0x1160
1805 #define BSW_HDMI_CTL_D 0x116c
1806
1807 /* VLV HDMI port ctrl */
1808 #define SDVO_HDMI_CTL_B 0x1140
1809 #define SDVO_HDMI_CTL_C 0x1160
1810
dump_dp_port_ctrl(int port)1811 static void dump_dp_port_ctrl(int port)
1812 {
1813 uint32_t dword;
1814 int port_ctrl;
1815 char prefix[MAX_PREFIX_SIZE];
1816
1817 sprintf(prefix, "DP_%c", 'B' + port - PORT_B);
1818
1819 port_ctrl = disp_reg_base + DP_CTL_B + (port - PORT_B) * 0x100;
1820 dword = INREG(port_ctrl);
1821 printf("%s DisplayPort_Enable\t\t\t\t\t%lu\n", prefix, REG_BIT(dword, 31));
1822 printf("%s Transcoder_Select\t\t\t\t\t%s\n", prefix, REG_BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
1823 printf("%s Port_Width_Selection\t\t\t\t[0x%lx] %s\n", prefix, REG_BITS(dword, 21, 19),
1824 dp_port_width[REG_BITS(dword, 21, 19)]);
1825 printf("%s Port_Detected\t\t\t\t\t%lu\n", prefix, REG_BIT(dword, 2));
1826 printf("%s HDCP_Port_Select\t\t\t\t\t%lu\n", prefix, REG_BIT(dword, 5));
1827 printf("%s Audio_Output_Enable\t\t\t\t%lu\n", prefix, REG_BIT(dword, 6));
1828 }
1829
dump_hdmi_port_ctrl(int port)1830 static void dump_hdmi_port_ctrl(int port)
1831 {
1832 uint32_t dword;
1833 int port_ctrl;
1834 char prefix[MAX_PREFIX_SIZE];
1835
1836 if (IS_VALLEYVIEW(devid)) {
1837 sprintf(prefix, "SDVO/HDMI%c", 'B' + port - PORT_B);
1838 port_ctrl = disp_reg_base + SDVO_HDMI_CTL_B + (port - PORT_B) * 0x20;
1839 } else {
1840 sprintf(prefix, "HDMI%c ", 'B' + port - PORT_B);
1841 port_ctrl = disp_reg_base + HDMI_CTL_B + (port - PORT_B) * 0x10;
1842 }
1843
1844 dword = INREG(port_ctrl);
1845 printf("%s HDMI_Enable\t\t\t\t\t%u\n", prefix, !!(dword & SDVO_ENABLE));
1846 printf("%s Transcoder_Select\t\t\t\t%s\n", prefix, REG_BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
1847 printf("%s HDCP_Port_Select\t\t\t\t%lu\n", prefix, REG_BIT(dword, 5));
1848 if (port == PORT_B) /* TODO: check spec, not found in Ibx b-spec, and only for port B? */
1849 printf("%s SDVO Hot Plug Interrupt Detect Enable\t%lu\n", prefix, REG_BIT(dword, 23));
1850 printf("%s Digital_Port_Detected\t\t\t%lu\n", prefix, REG_BIT(dword, 2));
1851 printf("%s Encoding\t\t\t\t\t[0x%lx] %s\n", prefix, REG_BITS(dword, 11, 10),
1852 sdvo_hdmi_encoding[REG_BITS(dword, 11, 10)]);
1853 printf("%s Null_packets_enabled_during_Vsync\t\t%u\n", prefix, !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
1854 printf("%s Audio_Output_Enable\t\t\t\t%u\n", prefix, !!(dword & SDVO_AUDIO_ENABLE));
1855 }
1856
dump_ironlake(void)1857 static void dump_ironlake(void)
1858 {
1859 uint32_t dword;
1860
1861 if (!IS_VALLEYVIEW(devid))
1862 set_reg_base(0xe0000, 0x2000); /* ironlake */
1863 else
1864 set_reg_base(0x60000 + VLV_DISPLAY_BASE, 0x2000);
1865
1866 if (!IS_VALLEYVIEW(devid)) {
1867 dump_disp_reg(HDMI_CTL_B, "sDVO/HDMI Port B Control");
1868 dump_disp_reg(HDMI_CTL_C, "HDMI Port C Control");
1869 dump_disp_reg(HDMI_CTL_D, "HDMI Port D Control");
1870 } else {
1871 dump_disp_reg(SDVO_HDMI_CTL_B, "sDVO/HDMI Port B Control");
1872 dump_disp_reg(SDVO_HDMI_CTL_C, "sDVO/HDMI Port C Control");
1873 }
1874
1875 dump_disp_reg(DP_CTL_B, "DisplayPort B Control Register");
1876 dump_disp_reg(DP_CTL_C, "DisplayPort C Control Register");
1877 if (!IS_VALLEYVIEW(devid))
1878 dump_disp_reg(DP_CTL_D, "DisplayPort D Control Register");
1879
1880 dump_aud_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
1881 dump_aud_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
1882 dump_aud_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
1883 dump_aud_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
1884 dump_aud_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
1885 dump_aud_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
1886 dump_aud_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
1887 dump_aud_reg(AUD_RID, "Audio Revision ID");
1888 dump_aud_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
1889 dump_aud_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
1890 dump_aud_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
1891 dump_aud_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
1892 dump_aud_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
1893 dump_aud_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
1894 dump_aud_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
1895 dump_aud_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
1896 dump_aud_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
1897 dump_aud_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
1898 dump_aud_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
1899 dump_aud_reg(AUD_CNTL_ST2, "Audio Control State 2");
1900 dump_aud_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
1901 dump_aud_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
1902 dump_aud_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
1903 dump_aud_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
1904 dump_aud_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
1905
1906 printf("\nDetails:\n\n");
1907
1908 dump_aud_vendor_device_id();
1909 dump_aud_revision_id();
1910
1911 dump_hdmi_port_ctrl(PORT_B);
1912 dump_hdmi_port_ctrl(PORT_C);
1913 if (!IS_VALLEYVIEW(devid))
1914 dump_hdmi_port_ctrl(PORT_D);
1915
1916 dump_dp_port_ctrl(PORT_B);
1917 dump_dp_port_ctrl(PORT_C);
1918 if (!IS_VALLEYVIEW(devid))
1919 dump_dp_port_ctrl(PORT_D);
1920
1921 dump_aud_config(PIPE_A);
1922 dump_aud_config(PIPE_B);
1923
1924 dump_aud_m_cts_enable(PIPE_A);
1925 dump_aud_m_cts_enable(PIPE_B);
1926
1927 dump_aud_misc_control(PIPE_A);
1928 dump_aud_misc_control(PIPE_B);
1929
1930 dump_aud_power_state();
1931 dump_aud_port_en_hd_cfg();
1932
1933 dump_aud_dig_cnvt(PIPE_A);
1934 dump_aud_dig_cnvt(PIPE_B);
1935
1936 dump_aud_out_ch_str();
1937
1938 dump_aud_str_desc(PIPE_A);
1939 dump_aud_str_desc(PIPE_B);
1940
1941 dump_aud_connect_list();
1942 dump_aud_connect_select();
1943
1944 dump_aud_ctrl_state(PIPE_A);
1945 dump_aud_ctrl_state(PIPE_B);
1946 dump_aud_ctrl_state2();
1947
1948 dump_aud_hdmi_status();
1949
1950 dump_aud_edid_data(PIPE_A);
1951 dump_aud_edid_data(PIPE_B);
1952
1953 dump_aud_infoframe(PIPE_A);
1954 dump_aud_infoframe(PIPE_B);
1955 }
1956
1957 #undef VIDEO_DIP_CTL_A
1958 #undef VIDEO_DIP_CTL_B
1959 #undef VIDEO_DIP_CTL_C
1960 #undef VIDEO_DIP_CTL_D
1961 #undef VIDEO_DIP_DATA
1962
1963 /*
1964 * Haswell+ display registers
1965 */
1966
1967 /* DisplayPort Transport Control */
1968 #define DP_TP_CTL_A 0x64040
1969 #define DP_TP_CTL_B 0x64140
1970 #define DP_TP_CTL_C 0x64240
1971 #define DP_TP_CTL_D 0x64340
1972 #define DP_TP_CTL_E 0x64440
1973
1974 /* DisplayPort Transport Status */
1975 #define DP_TP_ST_A 0x64044
1976 #define DP_TP_ST_B 0x64144
1977 #define DP_TP_ST_C 0x64244
1978 #define DP_TP_ST_D 0x64344
1979 #define DP_TP_ST_E 0x64444
1980
1981 /* DDI Buffer Control */
1982 #define DDI_BUF_CTL_A 0x64000
1983 #define DDI_BUF_CTL_B 0x64100
1984 #define DDI_BUF_CTL_C 0x64200
1985 #define DDI_BUF_CTL_D 0x64300
1986 #define DDI_BUF_CTL_E 0x64400
1987
1988 /* DDI Buffer Translation */
1989 #define DDI_BUF_TRANS_A 0x64e00
1990 #define DDI_BUF_TRANS_B 0x64e60
1991 #define DDI_BUF_TRANS_C 0x64ec0
1992 #define DDI_BUF_TRANS_D 0x64f20
1993 #define DDI_BUF_TRANS_E 0x64f80
1994
1995 /* DDI Aux Channel */
1996 #define DDI_AUX_CHANNEL_CTRL 0x64010
1997 #define DDI_AUX_DATA 0x64014
1998 #define DDI_AUX_TST 0x64028
1999
2000 /* DDI CRC Control */
2001 #define DDI_CRC_CTL_A 0x64050
2002 #define DDI_CRC_CTL_B 0x64150
2003 #define DDI_CRC_CTL_C 0x64250
2004 #define DDI_CRC_CTL_D 0x64350
2005 #define DDI_CRC_CTL_E 0x64450
2006
2007 /* Pipe DDI Function Control */
2008 #define PIPE_DDI_FUNC_CTL_A 0x60400
2009 #define PIPE_DDI_FUNC_CTL_B 0x61400
2010 #define PIPE_DDI_FUNC_CTL_C 0x62400
2011 #define PIPE_DDI_FUNC_CTL_EDP 0x6F400
2012
2013 /* Pipe Configuration */
2014 #define PIPE_CONF_A 0x70008
2015 #define PIPE_CONF_B 0x71008
2016 #define PIPE_CONF_C 0x72008
2017 #define PIPE_CONF_EDP 0x7F008
2018
2019 /* Video DIP Control */
2020 #define VIDEO_DIP_CTL_A 0x60200
2021 #define VIDEO_DIP_CTL_B 0x61200
2022 #define VIDEO_DIP_CTL_C 0x62200
2023 #define VIDEO_DIP_CTL_D 0x63200
2024
2025 #define VIDEO_DIP_DATA 0x60220
2026 #define VIDEO_DIP_ECC 0x60240
2027
dump_ddi_buf_ctl(int port)2028 static void dump_ddi_buf_ctl(int port)
2029 {
2030 uint32_t dword;
2031
2032 dword = INREG(DDI_BUF_CTL_A + (port - PORT_A) * 0x100);
2033 printf("DDI %c Buffer control\n", 'A' + port - PORT_A);
2034
2035 printf("\tDP port width\t\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 3, 1),
2036 OPNAME(dp_port_width, REG_BITS(dword, 3, 1)));
2037 printf("\tDDI Buffer Enable\t\t\t\t%ld\n", REG_BIT(dword, 31));
2038 }
2039
dump_ddi_func_ctl(int pipe)2040 static void dump_ddi_func_ctl(int pipe)
2041 {
2042 uint32_t dword;
2043
2044 dword = INREG(PIPE_DDI_FUNC_CTL_A + (pipe - PIPE_A) * 0x1000);
2045 printf("Pipe %c DDI Function Control\n", 'A' + pipe - PIPE_A);
2046
2047 printf("\tREG_BITS per color\t\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 22, 20),
2048 OPNAME(bits_per_color, REG_BITS(dword, 22, 20)));
2049 printf("\tPIPE DDI Mode\t\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 26, 24),
2050 OPNAME(ddi_mode, REG_BITS(dword, 26, 24)));
2051 printf("\tPIPE DDI selection\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 30, 28),
2052 OPNAME(trans_to_port_sel, REG_BITS(dword, 30, 28)));
2053 printf("\tPIPE DDI Function Enable\t\t\t[0x%lx]\n", REG_BIT(dword, 31));
2054 }
2055
dump_aud_connect_list_entry_length(int transcoder)2056 static void dump_aud_connect_list_entry_length(int transcoder)
2057 {
2058 uint32_t dword;
2059 char prefix[MAX_PREFIX_SIZE];
2060
2061 dword = INREG(aud_reg_base + AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH + (transcoder - TRANSCODER_A) * 0x100);
2062 sprintf(prefix, "AUD_TC%c_PIN_PIPE_CONN_ENTRY_LNGTH", 'A' + transcoder - TRANSCODER_A);
2063
2064 printf("%s Connect_List_Length\t%lu\n", prefix, REG_BITS(dword, 6, 0));
2065 printf("%s Form \t\t[%#lx] %s\n", prefix, REG_BIT(dword, 7),
2066 OPNAME(connect_list_form, REG_BIT(dword, 7)));
2067 printf("%s Connect_List_Entry\t%lu\n", prefix, REG_BITS(dword, 15, 8));
2068 }
2069
dump_aud_connect_select_ctrl(void)2070 static void dump_aud_connect_select_ctrl(void)
2071 {
2072 uint32_t dword;
2073
2074 dword = INREG(aud_reg_base + AUD_PIPE_CONN_SEL_CTRL);
2075 printf("AUD_PIPE_CONN_SEL_CTRL Connection_select_Port_B\t%#lx\n", REG_BITS(dword, 7, 0));
2076 printf("AUD_PIPE_CONN_SEL_CTRL Connection_select_Port_C\t%#lx\n", REG_BITS(dword, 15, 8));
2077 printf("AUD_PIPE_CONN_SEL_CTRL Connection_select_Port_D\t%#lx\n", REG_BITS(dword, 23, 16));
2078 }
2079
dump_aud_dip_eld_ctrl_st(int transcoder)2080 static void dump_aud_dip_eld_ctrl_st(int transcoder)
2081 {
2082 uint32_t dword;
2083 int offset = (transcoder - TRANSCODER_A) * 0x100;
2084
2085 dword = INREG(aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset);
2086 printf("Audio DIP and ELD control state for Transcoder %c\n", 'A' + transcoder - TRANSCODER_A);
2087
2088 printf("\tELD_ACK\t\t\t\t\t\t%lu\n", REG_BIT(dword, 4));
2089 printf("\tELD_buffer_size\t\t\t\t\t%lu\n", REG_BITS(dword, 14, 10));
2090 printf("\tDIP_transmission_frequency\t\t\t[0x%lx] %s\n", REG_BITS(dword, 17, 16),
2091 dip_trans[REG_BITS(dword, 17, 16)]);
2092 printf("\tDIP Buffer Index \t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 20, 18),
2093 dip_index[REG_BITS(dword, 20, 18)]);
2094 printf("\tAudio DIP type enable status\t\t\t[0x%04lx] %s, %s, %s\n", REG_BITS(dword, 24, 21),
2095 dip_type[REG_BIT(dword, 21)], dip_gen1_state[REG_BIT(dword, 22)], dip_gen2_state[REG_BIT(dword, 23)]);
2096 printf("\tAudio DIP port select\t\t\t\t[0x%lx] %s\n", REG_BITS(dword, 30, 29),
2097 dip_port[REG_BITS(dword, 30, 29)]);
2098 printf("\n");
2099 }
2100
dump_aud_hdmi_fifo_status(void)2101 static void dump_aud_hdmi_fifo_status(void)
2102 {
2103 uint32_t dword;
2104
2105 dword = INREG(aud_reg_base + AUD_HDMI_FIFO_STATUS);
2106 printf("AUD_HDMI_FIFO_STATUS Function_Reset\t\t\t%lu\n", REG_BIT(dword, 24));
2107 printf("AUD_HDMI_FIFO_STATUS Conv_1_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 26));
2108 printf("AUD_HDMI_FIFO_STATUS Conv_1_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 27));
2109 printf("AUD_HDMI_FIFO_STATUS Conv_2_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 28));
2110 printf("AUD_HDMI_FIFO_STATUS Conv_2_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 29));
2111 printf("AUD_HDMI_FIFO_STATUS Conv_3_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", REG_BIT(dword, 30));
2112 printf("AUD_HDMI_FIFO_STATUS Conv_3_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", REG_BIT(dword, 31));
2113 }
2114
parse_bdw_audio_chicken_bit_reg(uint32_t dword)2115 static void parse_bdw_audio_chicken_bit_reg(uint32_t dword)
2116 {
2117 printf("\t");
2118 printf("%s\n\t", OPNAME(vanilla_dp12_en, REG_BIT(dword, 31)));
2119 printf("%s\n\t", OPNAME(vanilla_3_widgets_en, REG_BIT(dword, 30)));
2120 printf("%s\n\t", OPNAME(block_audio, REG_BIT(dword, 10)));
2121 printf("%s\n\t", OPNAME(dis_eld_valid_pulse_trans, REG_BIT(dword, 9)));
2122 printf("%s\n\t", OPNAME(dis_pd_pulse_trans, REG_BIT(dword, 8)));
2123 printf("%s\n\t", OPNAME(dis_ts_delta_err, REG_BIT(dword, 7)));
2124 printf("%s\n\t", OPNAME(dis_ts_fix_dp_hbr, REG_BIT(dword, 6)));
2125 printf("%s\n\t", OPNAME(pattern_gen_8_ch_en, REG_BIT(dword, 5)));
2126 printf("%s\n\t", OPNAME(pattern_gen_2_ch_en, REG_BIT(dword, 4)));
2127 printf("%s\n\t", OPNAME(fabric_32_44_dis, REG_BIT(dword, 3)));
2128 printf("%s\n\t", OPNAME(epss_dis, REG_BIT(dword, 2)));
2129 printf("%s\n\t", OPNAME(ts_test_mode, REG_BIT(dword, 1)));
2130 printf("%s\n", OPNAME(en_mmio_program, REG_BIT(dword, 0)));
2131 }
2132
parse_skl_audio_freq_cntrl_reg(uint32_t dword)2133 static void parse_skl_audio_freq_cntrl_reg(uint32_t dword)
2134 {
2135 printf("\t");
2136 printf("%s\n\t", OPNAME(sdi_operate_mode, REG_BIT(dword, 15)));
2137 printf("%s\n\t", OPNAME(bclk_96mhz, REG_BIT(dword, 4)));
2138 printf("%s\n", OPNAME(bclk_48mhz, REG_BIT(dword, 3)));
2139 }
2140
2141 /* Dump audio registers for Haswell and its successors (eg. Broadwell).
2142 * Their register layout are same in the north display engine.
2143 */
dump_hsw_plus(void)2144 static void dump_hsw_plus(void)
2145 {
2146 uint32_t dword;
2147 int i;
2148
2149 set_aud_reg_base(0x65000);
2150
2151 dump_reg(PORT_HOTPLUG_EN, "port hotplug enable");
2152 dump_reg(PORT_HOTPLUG_STAT, "port hotplug status");
2153 dump_reg(DISPLAY_HOTPLUG_CTL, "display hotplug control");
2154
2155 /* HSW DDI Buffer */
2156 dump_reg(DDI_BUF_CTL_A, "DDI Buffer Controler A");
2157 dump_reg(DDI_BUF_CTL_B, "DDI Buffer Controler B");
2158 dump_reg(DDI_BUF_CTL_C, "DDI Buffer Controler C");
2159 dump_reg(DDI_BUF_CTL_D, "DDI Buffer Controler D");
2160 dump_reg(DDI_BUF_CTL_E, "DDI Buffer Controler E");
2161
2162 /* HSW Pipe Function */
2163 dump_reg(PIPE_CONF_A, "PIPE Configuration A");
2164 dump_reg(PIPE_CONF_B, "PIPE Configuration B");
2165 dump_reg(PIPE_CONF_C, "PIPE Configuration C");
2166 dump_reg(PIPE_CONF_EDP, "PIPE Configuration EDP");
2167
2168 dump_reg(PIPE_DDI_FUNC_CTL_A, "PIPE DDI Function Control A");
2169 dump_reg(PIPE_DDI_FUNC_CTL_B, "PIPE DDI Function Control B");
2170 dump_reg(PIPE_DDI_FUNC_CTL_C, "PIPE DDI Function Control C");
2171 dump_reg(PIPE_DDI_FUNC_CTL_EDP, "PIPE DDI Function Control EDP");
2172
2173 /* HSW Display port */
2174 dump_reg(DP_TP_CTL_A, "DisplayPort Transport A Control");
2175 dump_reg(DP_TP_CTL_B, "DisplayPort Transport B Control");
2176 dump_reg(DP_TP_CTL_C, "DisplayPort Transport C Control");
2177 dump_reg(DP_TP_CTL_D, "DisplayPort Transport D Control");
2178 dump_reg(DP_TP_CTL_E, "DisplayPort Transport E Control");
2179
2180 dump_reg(DP_TP_ST_A, "DisplayPort Transport A Status");
2181 dump_reg(DP_TP_ST_B, "DisplayPort Transport B Status");
2182 dump_reg(DP_TP_ST_C, "DisplayPort Transport C Status");
2183 dump_reg(DP_TP_ST_D, "DisplayPort Transport D Status");
2184 dump_reg(DP_TP_ST_E, "DisplayPort Transport E Status");
2185
2186 /* HSW North Display Audio */
2187 dump_aud_reg(AUD_TCA_CONFIG, "Audio Configuration - Transcoder A");
2188 dump_aud_reg(AUD_TCB_CONFIG, "Audio Configuration - Transcoder B");
2189 dump_aud_reg(AUD_TCC_CONFIG, "Audio Configuration - Transcoder C");
2190 dump_aud_reg(AUD_C1_MISC_CTRL, "Audio Converter 1 MISC Control");
2191 dump_aud_reg(AUD_C2_MISC_CTRL, "Audio Converter 2 MISC Control");
2192 dump_aud_reg(AUD_C3_MISC_CTRL, "Audio Converter 3 MISC Control");
2193 dump_aud_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
2194 dump_aud_reg(AUD_RID, "Audio Revision ID");
2195 dump_aud_reg(AUD_TCA_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder A");
2196 dump_aud_reg(AUD_TCB_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder B");
2197 dump_aud_reg(AUD_TCC_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder C");
2198 dump_aud_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
2199 dump_aud_reg(AUD_TCA_EDID_DATA, "Audio EDID Data Block - Transcoder A");
2200 dump_aud_reg(AUD_TCB_EDID_DATA, "Audio EDID Data Block - Transcoder B");
2201 dump_aud_reg(AUD_TCC_EDID_DATA, "Audio EDID Data Block - Transcoder C");
2202 if (IS_GEN9(devid))
2203 dump_aud_reg(AUD_FREQ_CNTRL, "Audio BCLK Frequency Control");
2204 dump_aud_reg(AUD_TCA_INFOFR, "Audio Widget Data Island Packet - Transcoder A");
2205 dump_aud_reg(AUD_TCB_INFOFR, "Audio Widget Data Island Packet - Transcoder B");
2206 dump_aud_reg(AUD_TCC_INFOFR, "Audio Widget Data Island Packet - Transcoder C");
2207 dump_aud_reg(AUD_PIPE_CONV_CFG, "Audio Pipe and Converter Configs");
2208 dump_aud_reg(AUD_C1_DIG_CNVT, "Audio Digital Converter - Converter 1");
2209 dump_aud_reg(AUD_C2_DIG_CNVT, "Audio Digital Converter - Converter 2");
2210 dump_aud_reg(AUD_C3_DIG_CNVT, "Audio Digital Converter - Converter 3");
2211 dump_aud_reg(AUD_C1_STR_DESC, "Audio Stream Descriptor Format - Converter 1");
2212 dump_aud_reg(AUD_C2_STR_DESC, "Audio Stream Descriptor Format - Converter 2");
2213 dump_aud_reg(AUD_C3_STR_DESC, "Audio Stream Descriptor Format - Converter 3");
2214 dump_aud_reg(AUD_OUT_CHAN_MAP, "Audio Output Channel Mapping");
2215 dump_aud_reg(AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder A");
2216 dump_aud_reg(AUD_TCB_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder B");
2217 dump_aud_reg(AUD_TCC_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder C");
2218 dump_aud_reg(AUD_PIPE_CONN_SEL_CTRL, "Audio Pipe Connection Select Control");
2219 dump_aud_reg(AUD_TCA_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder A");
2220 dump_aud_reg(AUD_TCB_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder B");
2221 dump_aud_reg(AUD_TCC_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder C");
2222 dump_aud_reg(AUD_PIN_ELD_CP_VLD, "Audio pin ELD valid and CP ready status");
2223 dump_aud_reg(AUD_HDMI_FIFO_STATUS, "Audio HDMI FIFO Status");
2224
2225 /* Audio debug registers */
2226 dump_aud_reg(AUD_ICOI, "Audio Immediate Command Output Interface");
2227 dump_aud_reg(AUD_IRII, "Audio Immediate Response Input Interface");
2228 dump_aud_reg(AUD_ICS, "Audio Immediate Command Status");
2229 dump_aud_reg(AUD_CHICKENBIT_REG, "Audio Chicken Bit Register");
2230 dump_aud_reg(AUD_DP_DIP_STATUS, "Audio DP and DIP FIFO Debug Status");
2231 dump_aud_reg(AUD_TCA_M_CTS, "Audio M CTS Read Back Transcoder A");
2232 dump_aud_reg(AUD_TCB_M_CTS, "Audio M CTS Read Back Transcoder B");
2233 dump_aud_reg(AUD_TCC_M_CTS, "Audio M CTS Read Back Transcoder C");
2234 if (IS_GEN9(devid)) {
2235 dump_aud_reg(AUD_HDA_DMA_REG, "Audio HD Audio DMA Control Register");
2236 dump_aud_reg(AUD_HDA_LPIB0_REG, "Audio HD Audio Stream0 Link Position in Buffer");
2237 dump_aud_reg(AUD_HDA_LPIB1_REG, "Audio HD Audio Stream1 Link Position in Buffer");
2238 dump_aud_reg(AUD_HDA_LPIB2_REG, "Audio HD Audio Stream2 Link Position in Buffer");
2239 dump_aud_reg(AUD_HDA_EXTRA_REG, "Audio HD Audio Extra Register");
2240 dump_aud_reg(AUD_FPGA_CRC_CTL_A, "Audio FPGA Pipe A CRC Control");
2241 dump_aud_reg(AUD_FPGA_CRC_CTL_B, "Audio FPGA Pipe B CRC Control");
2242 dump_aud_reg(AUD_FPGA_CRC_CTL_C, "Audio FPGA Pipe C CRC Control");
2243 dump_aud_reg(AUD_FPGA_CRC_RESULT_A, "Audio FPGA Pipe A CRC Result");
2244 dump_aud_reg(AUD_FPGA_CRC_RESULT_B, "Audio FPGA Pipe B CRC Result");
2245 dump_aud_reg(AUD_FPGA_CRC_RESULT_C, "Audio FPGA Pipe C CRC Result");
2246 dump_aud_reg(AUD_DFT_MVAL_REG, "Audio DFT M Value Register");
2247 dump_aud_reg(AUD_DFT_NVAL_REG, "Audio DFT N Value Register");
2248 dump_aud_reg(AUD_DFT_LOAD_REG, "Audio DFT LOAD Register");
2249 }
2250
2251 printf("\nDetails:\n\n");
2252
2253 dump_ddi_buf_ctl(PORT_A);
2254 dump_ddi_buf_ctl(PORT_B);
2255 dump_ddi_buf_ctl(PORT_C);
2256 dump_ddi_buf_ctl(PORT_D);
2257 dump_ddi_buf_ctl(PORT_E);
2258
2259 dump_ddi_func_ctl(PIPE_A);
2260 dump_ddi_func_ctl(PIPE_B);
2261 dump_ddi_func_ctl(PIPE_C);
2262
2263 /* audio configuration - details */
2264 dump_aud_config(TRANSCODER_A);
2265 dump_aud_config(TRANSCODER_B);
2266 dump_aud_config(TRANSCODER_C);
2267
2268 dump_aud_misc_control(CONVERTER_1);
2269 dump_aud_misc_control(CONVERTER_2);
2270 dump_aud_misc_control(CONVERTER_3);
2271
2272 dump_aud_vendor_device_id();
2273 dump_aud_revision_id();
2274
2275 dump_aud_m_cts_enable(TRANSCODER_A);
2276 dump_aud_m_cts_enable(TRANSCODER_B);
2277 dump_aud_m_cts_enable(TRANSCODER_C);
2278
2279 dump_aud_power_state();
2280
2281 dump_aud_edid_data(TRANSCODER_A);
2282 dump_aud_edid_data(TRANSCODER_B);
2283 dump_aud_edid_data(TRANSCODER_C);
2284
2285 dump_aud_infoframe(TRANSCODER_A);
2286 dump_aud_infoframe(TRANSCODER_B);
2287 dump_aud_infoframe(TRANSCODER_C);
2288
2289 dump_aud_pipe_conv_cfg();
2290
2291 dump_aud_dig_cnvt(CONVERTER_1);
2292 dump_aud_dig_cnvt(CONVERTER_2);
2293 dump_aud_dig_cnvt(CONVERTER_3);
2294
2295 dump_aud_str_desc(CONVERTER_1);
2296 dump_aud_str_desc(CONVERTER_2);
2297 dump_aud_str_desc(CONVERTER_3);
2298
2299 dump_aud_out_chan_map();
2300
2301 dump_aud_connect_list_entry_length(TRANSCODER_A);
2302 dump_aud_connect_list_entry_length(TRANSCODER_B);
2303 dump_aud_connect_list_entry_length(TRANSCODER_C);
2304 dump_aud_connect_select_ctrl();
2305
2306 dump_aud_dip_eld_ctrl_st(TRANSCODER_A);
2307 dump_aud_dip_eld_ctrl_st(TRANSCODER_B);
2308 dump_aud_dip_eld_ctrl_st(TRANSCODER_C);
2309
2310 dump_aud_eld_cp_vld();
2311 dump_aud_hdmi_fifo_status();
2312
2313 dword = read_aud_reg(AUD_ICS);
2314 printf("IRV [%1lx] %s\t", REG_BIT(dword, 1),
2315 OPNAME(immed_result_valid, REG_BIT(dword, 1)));
2316 printf("ICB [%1lx] %s\n", REG_BIT(dword, 1),
2317 OPNAME(immed_cmd_busy, REG_BIT(dword, 0)));
2318
2319 dword = read_aud_reg(AUD_CHICKENBIT_REG);
2320 printf("AUD_CHICKENBIT_REG Audio Chicken Bits: %08x\n", dword);
2321 if (IS_BROADWELL(devid))
2322 parse_bdw_audio_chicken_bit_reg(dword);
2323
2324 dword = read_aud_reg(AUD_DP_DIP_STATUS);
2325 printf("AUD_DP_DIP_STATUS Audio DP & DIP FIFO Status: %08x\n\t", dword);
2326 for (i = 31; i >= 0; i--)
2327 if (REG_BIT(dword, i))
2328 printf("%s\n\t", audio_dp_dip_status[i]);
2329 printf("\n");
2330
2331 dword = read_aud_reg(AUD_FREQ_CNTRL);
2332 printf("AUD_FREQ_CNTRL Audio BCLK Frequency Control: %08x\n", dword);
2333 if (IS_GEN9(devid))
2334 parse_skl_audio_freq_cntrl_reg(dword);
2335 }
2336
2337 /* offset of hotplug enable */
2338 #define PORT_HOTPLUG_EN_OFFSET 0x1110
2339 /* offset of hotplug status */
2340 #define PORT_HOTPLUG_STAT_OFFSET 0x1114
2341 /* offset of hotplug control*/
2342 #define DISPLAY_HOTPLUG_CTL_OFFSET 0x1164
2343 /* dump the braswell registers for audio */
dump_braswell(void)2344 static void dump_braswell(void)
2345 {
2346 uint32_t dword;
2347
2348 /* set_aud_reg_base(0x62000 + VLV_DISPLAY_BASE); */
2349 set_reg_base(0x60000 + VLV_DISPLAY_BASE, 0x2000);
2350
2351
2352 dump_disp_reg(PORT_HOTPLUG_EN_OFFSET, "port hotplug enable");
2353 dump_disp_reg(PORT_HOTPLUG_STAT_OFFSET, "port hotplug status");
2354 dump_disp_reg(DISPLAY_HOTPLUG_CTL_OFFSET, "display hotplug control");
2355
2356 dump_disp_reg(BSW_HDMI_CTL_B, "sDVO/HDMI Port B Control");
2357 dump_disp_reg(BSW_HDMI_CTL_C, "HDMI Port C Control"); // The address is wrong?
2358 dump_disp_reg(BSW_HDMI_CTL_D, "HDMI Port D Control");
2359
2360 dump_disp_reg(DP_CTL_B, "DisplayPort B Control Register");
2361 dump_disp_reg(DP_CTL_C, "DisplayPort C Control Register");
2362 dump_disp_reg(DP_CTL_D, "DisplayPort D Control Register");
2363
2364 /* HSW North Display Audio */
2365 dump_aud_reg(AUD_TCA_CONFIG, "Audio Configuration - Transcoder A");
2366 dump_aud_reg(AUD_TCB_CONFIG, "Audio Configuration - Transcoder B");
2367 dump_aud_reg(AUD_TCC_CONFIG, "Audio Configuration - Transcoder C");
2368 dump_aud_reg(AUD_C1_MISC_CTRL, "Audio Converter 1 MISC Control");
2369 dump_aud_reg(AUD_C2_MISC_CTRL, "Audio Converter 2 MISC Control");
2370 dump_aud_reg(AUD_C3_MISC_CTRL, "Audio Converter 3 MISC Control");
2371 dump_aud_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
2372 dump_aud_reg(AUD_RID, "Audio Revision ID");
2373 dump_aud_reg(AUD_TCA_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder A");
2374 dump_aud_reg(AUD_TCB_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder B");
2375 dump_aud_reg(AUD_TCC_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder C");
2376 dump_aud_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
2377 dump_aud_reg(AUD_TCA_EDID_DATA, "Audio EDID Data Block - Transcoder A");
2378 dump_aud_reg(AUD_TCB_EDID_DATA, "Audio EDID Data Block - Transcoder B");
2379 dump_aud_reg(AUD_TCC_EDID_DATA, "Audio EDID Data Block - Transcoder C");
2380 dump_aud_reg(AUD_TCA_INFOFR, "Audio Widget Data Island Packet - Transcoder A");
2381 dump_aud_reg(AUD_TCB_INFOFR, "Audio Widget Data Island Packet - Transcoder B");
2382 dump_aud_reg(AUD_TCC_INFOFR, "Audio Widget Data Island Packet - Transcoder C");
2383 dump_aud_reg(AUD_PIPE_CONV_CFG, "Audio Pipe and Converter Configs");
2384 dump_aud_reg(AUD_C1_DIG_CNVT, "Audio Digital Converter - Converter 1");
2385 dump_aud_reg(AUD_C2_DIG_CNVT, "Audio Digital Converter - Converter 2");
2386 dump_aud_reg(AUD_C3_DIG_CNVT, "Audio Digital Converter - Converter 3");
2387 dump_aud_reg(AUD_C1_STR_DESC, "Audio Stream Descriptor Format - Converter 1");
2388 dump_aud_reg(AUD_C2_STR_DESC, "Audio Stream Descriptor Format - Converter 2");
2389 dump_aud_reg(AUD_C3_STR_DESC, "Audio Stream Descriptor Format - Converter 3");
2390 dump_aud_reg(AUD_OUT_CHAN_MAP, "Audio Output Channel Mapping");
2391 dump_aud_reg(AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder A");
2392 dump_aud_reg(AUD_TCB_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder B");
2393 dump_aud_reg(AUD_TCC_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder C");
2394 dump_aud_reg(AUD_PIPE_CONN_SEL_CTRL, "Audio Pipe Connection Select Control");
2395 dump_aud_reg(AUD_TCA_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder A");
2396 dump_aud_reg(AUD_TCB_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder B");
2397 dump_aud_reg(AUD_TCC_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder C");
2398 dump_aud_reg(AUD_PIN_ELD_CP_VLD, "Audio pin ELD valid and CP ready status");
2399 dump_aud_reg(AUD_HDMI_FIFO_STATUS, "Audio HDMI FIFO Status");
2400
2401 /* Audio debug registers */
2402 dump_aud_reg(AUD_ICOI, "Audio Immediate Command Output Interface");
2403 dump_aud_reg(AUD_IRII, "Audio Immediate Response Input Interface");
2404 dump_aud_reg(AUD_ICS, "Audio Immediate Command Status");
2405 dump_aud_reg(AUD_CHICKENBIT_REG, "Audio Chicken Bit Register");
2406 dump_aud_reg(AUD_DP_DIP_STATUS, "Audio DP and DIP FIFO Debug Status");
2407 dump_aud_reg(AUD_TCA_M_CTS, "Audio M CTS Read Back Transcoder A");
2408 dump_aud_reg(AUD_TCB_M_CTS, "Audio M CTS Read Back Transcoder B");
2409 dump_aud_reg(AUD_TCC_M_CTS, "Audio M CTS Read Back Transcoder C");
2410
2411 printf("\n");
2412
2413 printf("\nDetails:\n\n");
2414
2415 dump_aud_vendor_device_id();
2416 dump_aud_revision_id();
2417
2418 dump_hdmi_port_ctrl(PORT_B);
2419 dump_hdmi_port_ctrl(PORT_C);
2420 if (!IS_VALLEYVIEW(devid))
2421 dump_hdmi_port_ctrl(PORT_D);
2422
2423 dump_dp_port_ctrl(PORT_B);
2424 dump_dp_port_ctrl(PORT_C);
2425 if (!IS_VALLEYVIEW(devid))
2426 dump_dp_port_ctrl(PORT_D);
2427
2428 dump_aud_config(PIPE_A);
2429 dump_aud_config(PIPE_B);
2430
2431 dump_aud_m_cts_enable(PIPE_A);
2432 dump_aud_m_cts_enable(PIPE_B);
2433
2434 dump_aud_misc_control(PIPE_A);
2435 dump_aud_misc_control(PIPE_B);
2436
2437 dump_aud_power_state();
2438 dump_aud_port_en_hd_cfg();
2439
2440 dump_aud_dig_cnvt(PIPE_A);
2441 dump_aud_dig_cnvt(PIPE_B);
2442
2443 dump_aud_out_ch_str();
2444
2445 dump_aud_str_desc(PIPE_A);
2446 dump_aud_str_desc(PIPE_B);
2447
2448 dump_aud_connect_list();
2449 dump_aud_connect_select();
2450
2451 dump_aud_ctrl_state(PIPE_A);
2452 dump_aud_ctrl_state(PIPE_B);
2453 dump_aud_ctrl_state2();
2454
2455 dump_aud_hdmi_status();
2456
2457 dump_aud_edid_data(PIPE_A);
2458 dump_aud_edid_data(PIPE_B);
2459
2460 dump_aud_infoframe(PIPE_A);
2461 dump_aud_infoframe(PIPE_B);
2462 }
2463
main(int argc,char ** argv)2464 int main(int argc, char **argv)
2465 {
2466 struct pci_device *pci_dev;
2467
2468 pci_dev = intel_get_pci_device();
2469 devid = pci_dev->device_id; /* XXX not true when mapping! */
2470
2471 do_self_tests();
2472
2473 if (argc == 2)
2474 intel_mmio_use_dump_file(argv[1]);
2475 else
2476 intel_mmio_use_pci_bar(pci_dev);
2477
2478 printf("%s audio registers:\n\n", intel_get_device_info(devid)->codename);
2479 if (IS_VALLEYVIEW(devid)) {
2480 dump_ironlake();
2481 } else if (IS_CHERRYVIEW(devid)) {
2482 dump_braswell();
2483 } else if (IS_GEN9(devid)
2484 || IS_BROADWELL(devid) || IS_HASWELL(devid)) {
2485 dump_hsw_plus();
2486 } else if (IS_GEN6(devid) || IS_GEN7(devid)
2487 || getenv("HAS_PCH_SPLIT")) {
2488 intel_check_pch();
2489 dump_cpt();
2490 } else if (IS_GEN5(devid)) {
2491 dump_ironlake();
2492 } else if (IS_G4X(devid)) {
2493 dump_eaglelake();
2494 }
2495
2496 return 0;
2497 }
2498