1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "igt.h"
25
26 #include <sys/poll.h>
27
28 IGT_TEST_DESCRIPTION("Basic check of polling for prime fences.");
29
prime_busy(struct pollfd * pfd,bool excl)30 static bool prime_busy(struct pollfd *pfd, bool excl)
31 {
32 pfd->events = excl ? POLLOUT : POLLIN;
33 return poll(pfd, 1, 0) == 0;
34 }
35
36 #define BEFORE 0x1
37 #define AFTER 0x2
38 #define HANG 0x4
39 #define POLL 0x8
40
busy(int fd,unsigned ring,unsigned flags)41 static void busy(int fd, unsigned ring, unsigned flags)
42 {
43 const int gen = intel_gen(intel_get_drm_devid(fd));
44 struct drm_i915_gem_exec_object2 obj[2];
45 struct pollfd pfd[2];
46 #define SCRATCH 0
47 #define BATCH 1
48 struct drm_i915_gem_relocation_entry store[1024+1];
49 struct drm_i915_gem_execbuffer2 execbuf;
50 unsigned size = ALIGN(ARRAY_SIZE(store)*16 + 4, 4096);
51 struct timespec tv;
52 uint32_t *batch, *bbe;
53 int i, count, timeout;
54
55 gem_quiescent_gpu(fd);
56
57 memset(&execbuf, 0, sizeof(execbuf));
58 execbuf.buffers_ptr = (uintptr_t)obj;
59 execbuf.buffer_count = 2;
60 execbuf.flags = ring;
61 if (gen < 6)
62 execbuf.flags |= I915_EXEC_SECURE;
63
64 memset(obj, 0, sizeof(obj));
65 obj[SCRATCH].handle = gem_create(fd, 4096);
66
67 obj[BATCH].handle = gem_create(fd, size);
68 obj[BATCH].relocs_ptr = (uintptr_t)store;
69 obj[BATCH].relocation_count = ARRAY_SIZE(store);
70 memset(store, 0, sizeof(store));
71
72 if (flags & BEFORE) {
73 memset(pfd, 0, sizeof(pfd));
74 pfd[SCRATCH].fd = prime_handle_to_fd(fd, obj[SCRATCH].handle);
75 pfd[BATCH].fd = prime_handle_to_fd(fd, obj[BATCH].handle);
76 }
77
78 batch = gem_mmap__wc(fd, obj[BATCH].handle, 0, size, PROT_WRITE);
79 gem_set_domain(fd, obj[BATCH].handle,
80 I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
81
82 i = 0;
83 for (count = 0; count < 1024; count++) {
84 store[count].target_handle = obj[SCRATCH].handle;
85 store[count].presumed_offset = -1;
86 store[count].offset = sizeof(uint32_t) * (i + 1);
87 store[count].delta = sizeof(uint32_t) * count;
88 store[count].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
89 store[count].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
90 batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
91 if (gen >= 8) {
92 batch[++i] = 0;
93 batch[++i] = 0;
94 } else if (gen >= 4) {
95 batch[++i] = 0;
96 batch[++i] = 0;
97 store[count].offset += sizeof(uint32_t);
98 } else {
99 batch[i]--;
100 batch[++i] = 0;
101 }
102 batch[++i] = count;
103 i++;
104 }
105
106 bbe = &batch[i];
107 store[count].target_handle = obj[BATCH].handle; /* recurse */
108 store[count].presumed_offset = 0;
109 store[count].offset = sizeof(uint32_t) * (i + 1);
110 store[count].delta = 0;
111 store[count].read_domains = I915_GEM_DOMAIN_COMMAND;
112 store[count].write_domain = 0;
113 batch[i] = MI_BATCH_BUFFER_START;
114 if (gen >= 8) {
115 batch[i] |= 1 << 8 | 1;
116 batch[++i] = 0;
117 batch[++i] = 0;
118 } else if (gen >= 6) {
119 batch[i] |= 1 << 8;
120 batch[++i] = 0;
121 } else {
122 batch[i] |= 2 << 6;
123 batch[++i] = 0;
124 if (gen < 4) {
125 batch[i] |= 1;
126 store[count].delta = 1;
127 }
128 }
129 i++;
130
131 igt_assert(i < size/sizeof(*batch));
132 igt_require(__gem_execbuf(fd, &execbuf) == 0);
133
134 if (flags & AFTER) {
135 memset(pfd, 0, sizeof(pfd));
136 pfd[SCRATCH].fd = prime_handle_to_fd(fd, obj[SCRATCH].handle);
137 pfd[BATCH].fd = prime_handle_to_fd(fd, obj[BATCH].handle);
138 }
139
140 igt_assert(prime_busy(&pfd[SCRATCH], false));
141 igt_assert(prime_busy(&pfd[SCRATCH], true));
142
143 igt_assert(!prime_busy(&pfd[BATCH], false));
144 igt_assert(prime_busy(&pfd[BATCH], true));
145
146 timeout = 120;
147 if ((flags & HANG) == 0) {
148 *bbe = MI_BATCH_BUFFER_END;
149 __sync_synchronize();
150 timeout = 1;
151 }
152
153 /* Calling busy in a loop should be enough to flush the rendering */
154 if (flags & POLL) {
155 pfd[BATCH].events = POLLOUT;
156 igt_assert(poll(pfd, 1, timeout * 1000) == 1);
157 } else {
158 memset(&tv, 0, sizeof(tv));
159 while (prime_busy(&pfd[BATCH], true))
160 igt_assert(igt_seconds_elapsed(&tv) < timeout);
161 }
162 igt_assert(!prime_busy(&pfd[SCRATCH], true));
163
164 munmap(batch, size);
165 batch = gem_mmap__wc(fd, obj[SCRATCH].handle, 0, 4096, PROT_READ);
166 for (i = 0; i < 1024; i++)
167 igt_assert_eq_u32(batch[i], i);
168 munmap(batch, 4096);
169
170 gem_close(fd, obj[BATCH].handle);
171 gem_close(fd, obj[SCRATCH].handle);
172
173 close(pfd[BATCH].fd);
174 close(pfd[SCRATCH].fd);
175 }
176
test_engine_mode(int fd,const struct intel_execution_engine * e,const char * name,unsigned int flags)177 static void test_engine_mode(int fd,
178 const struct intel_execution_engine *e,
179 const char *name, unsigned int flags)
180 {
181 igt_hang_t hang = {};
182
183 igt_subtest_group {
184 igt_fixture {
185 gem_require_ring(fd, e->exec_id | e->flags);
186 igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
187
188 if ((flags & HANG) == 0)
189 {
190 igt_fork_hang_detector(fd);
191 }
192 else
193 {
194 igt_skip_on_simulation();
195 hang = igt_allow_hang(fd, 0, 0);
196 }
197 }
198
199 igt_subtest_f("%s%s-%s",
200 !e->exec_id && !(flags & HANG) ? "basic-" : "",
201 name, e->name)
202 busy(fd, e->exec_id | e->flags, flags);
203
204 igt_subtest_f("%swait-%s-%s",
205 !e->exec_id && !(flags & HANG) ? "basic-" : "",
206 name, e->name)
207 busy(fd, e->exec_id | e->flags, flags | POLL);
208
209 igt_fixture {
210 if ((flags & HANG) == 0)
211 igt_stop_hang_detector();
212 else
213 igt_disallow_hang(fd, hang);
214 }
215 }
216 }
217
218 igt_main
219 {
220 const struct intel_execution_engine *e;
221 int fd = -1;
222
223 igt_fixture {
224 fd = drm_open_driver_master(DRIVER_INTEL);
225 igt_require_gem(fd);
226 }
227
228 igt_subtest_group {
229 const struct mode {
230 const char *name;
231 unsigned int flags;
232 } modes[] = {
233 { "before", BEFORE },
234 { "after", AFTER },
235 { "hang", BEFORE | HANG },
236 { NULL },
237 };
238
239 igt_fixture
240 gem_require_mmap_wc(fd);
241
242 for (e = intel_execution_engines; e->name; e++) {
243 for (const struct mode *m = modes; m->name; m++)
244 test_engine_mode(fd, e, m->name, m->flags);
245 }
246 }
247
248 igt_fixture
249 close(fd);
250 }
251