1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <[email protected]>
25 *
26 */
27
28 /** @file gen3_linear_render_blits.c
29 *
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
32 *
33 * The goal is to simply ensure the basics work.
34 */
35
36 #include "igt.h"
37 #include <stdlib.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <fcntl.h>
41 #include <inttypes.h>
42 #include <errno.h>
43 #include <sys/stat.h>
44 #include <sys/time.h>
45 #include <sys/ioctl.h>
46 #include "drm.h"
47
48 #include "i915_reg.h"
49
50 #define WIDTH 512
51 #define HEIGHT 512
52
pack_float(float f)53 static inline uint32_t pack_float(float f)
54 {
55 union {
56 uint32_t dw;
57 float f;
58 } u;
59 u.f = f;
60 return u.dw;
61 }
62
fill_reloc(struct drm_i915_gem_relocation_entry * reloc,uint32_t offset,uint32_t handle,uint32_t read_domain,uint32_t write_domain)63 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
64 uint32_t offset,
65 uint32_t handle,
66 uint32_t read_domain,
67 uint32_t write_domain)
68 {
69 reloc->target_handle = handle;
70 reloc->delta = 0;
71 reloc->offset = offset * sizeof(uint32_t);
72 reloc->presumed_offset = 0;
73 reloc->read_domains = read_domain;
74 reloc->write_domain = write_domain;
75
76 return reloc->presumed_offset + reloc->delta;
77 }
78
79 static void
copy(int fd,uint32_t dst,int dst_tiling,uint32_t src,int src_tiling)80 copy(int fd,
81 uint32_t dst, int dst_tiling,
82 uint32_t src, int src_tiling)
83 {
84 uint32_t batch[1024], *b = batch;
85 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
86 struct drm_i915_gem_exec_object2 obj[3];
87 struct drm_i915_gem_execbuffer2 exec;
88 uint32_t handle;
89 uint32_t tiling_bits;
90
91 /* invariant state */
92 *b++ = (_3DSTATE_AA_CMD |
93 AA_LINE_ECAAR_WIDTH_ENABLE |
94 AA_LINE_ECAAR_WIDTH_1_0 |
95 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
96 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
97 IAB_MODIFY_ENABLE |
98 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
99 IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
100 IAB_SRC_FACTOR_SHIFT) |
101 IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
102 IAB_DST_FACTOR_SHIFT));
103 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
104 *b++ = (0);
105 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
106 *b++ = (0);
107 *b++ = (_3DSTATE_DFLT_Z_CMD);
108 *b++ = (0);
109 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
110 CSB_TCB(0, 0) |
111 CSB_TCB(1, 1) |
112 CSB_TCB(2, 2) |
113 CSB_TCB(3, 3) |
114 CSB_TCB(4, 4) |
115 CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
116 *b++ = (_3DSTATE_RASTER_RULES_CMD |
117 ENABLE_POINT_RASTER_RULE |
118 OGL_POINT_RASTER_RULE |
119 ENABLE_LINE_STRIP_PROVOKE_VRTX |
120 ENABLE_TRI_FAN_PROVOKE_VRTX |
121 LINE_STRIP_PROVOKE_VRTX(1) |
122 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
123 *b++ = (_3DSTATE_MODES_4_CMD |
124 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
125 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
126 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
127 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
128 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
129 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
130 S4_LINE_WIDTH_ONE |
131 S4_CULLMODE_NONE |
132 S4_VFMT_XY);
133 *b++ = (0x00000000); /* Stencil. */
134 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
135 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
136 *b++ = (0);
137 *b++ = (0);
138 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
139 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
140 *b++ = (0);
141 *b++ = (_3DSTATE_STIPPLE);
142 *b++ = (0x00000000);
143 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
144
145 /* samler state */
146 tiling_bits = 0;
147 if (src_tiling != I915_TILING_NONE)
148 tiling_bits = MS3_TILED_SURFACE;
149 if (src_tiling == I915_TILING_Y)
150 tiling_bits |= MS3_TILE_WALK;
151
152 #define TEX_COUNT 1
153 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
154 *b++ = ((1 << TEX_COUNT) - 1);
155 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
156 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
157 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
158 (WIDTH - 1) << MS3_WIDTH_SHIFT);
159 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
160
161 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
162 *b++ = ((1 << TEX_COUNT) - 1);
163 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
164 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
165 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
166 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
167 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
168 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
169 *b++ = (0x00000000);
170
171 /* render target state */
172 tiling_bits = 0;
173 if (dst_tiling != I915_TILING_NONE)
174 tiling_bits = BUF_3D_TILED_SURFACE;
175 if (dst_tiling == I915_TILING_Y)
176 tiling_bits |= BUF_3D_TILE_WALK_Y;
177 *b++ = (_3DSTATE_BUF_INFO_CMD);
178 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
179 *b = fill_reloc(r++, b-batch, dst,
180 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
181 b++;
182
183 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
184 *b++ = (COLR_BUF_ARGB8888 |
185 DSTORG_HORT_BIAS(0x8) |
186 DSTORG_VERT_BIAS(0x8));
187
188 /* draw rect is unconditional */
189 *b++ = (_3DSTATE_DRAW_RECT_CMD);
190 *b++ = (0x00000000);
191 *b++ = (0x00000000); /* ymin, xmin */
192 *b++ = (DRAW_YMAX(HEIGHT - 1) |
193 DRAW_XMAX(WIDTH - 1));
194 /* yorig, xorig (relate to color buffer?) */
195 *b++ = (0x00000000);
196
197 /* texfmt */
198 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
199 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
200 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
201 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
202 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
203 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
204 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
205 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
206
207 /* pixel shader */
208 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
209 /* decl FS_T0 */
210 *b++ = (D0_DCL |
211 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
212 REG_NR(FS_T0) << D0_NR_SHIFT |
213 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
214 *b++ = (0);
215 *b++ = (0);
216 /* decl FS_S0 */
217 *b++ = (D0_DCL |
218 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
219 (REG_NR(FS_S0) << D0_NR_SHIFT) |
220 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
221 *b++ = (0);
222 *b++ = (0);
223 /* texld(FS_OC, FS_S0, FS_T0 */
224 *b++ = (T0_TEXLD |
225 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
226 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
227 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
228 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
229 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
230 *b++ = (0);
231
232 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
233 *b++ = pack_float(WIDTH);
234 *b++ = pack_float(HEIGHT);
235 *b++ = pack_float(WIDTH);
236 *b++ = pack_float(HEIGHT);
237
238 *b++ = pack_float(0);
239 *b++ = pack_float(HEIGHT);
240 *b++ = pack_float(0);
241 *b++ = pack_float(HEIGHT);
242
243 *b++ = pack_float(0);
244 *b++ = pack_float(0);
245 *b++ = pack_float(0);
246 *b++ = pack_float(0);
247
248 *b++ = MI_BATCH_BUFFER_END;
249 if ((b - batch) & 1)
250 *b++ = 0;
251
252 igt_assert(b - batch <= 1024);
253 handle = gem_create(fd, 4096);
254 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
255
256 igt_assert(r-reloc == 2);
257
258 obj[0].handle = dst;
259 obj[0].relocation_count = 0;
260 obj[0].relocs_ptr = 0;
261 obj[0].alignment = 0;
262 obj[0].offset = 0;
263 obj[0].flags = 0;
264 obj[0].rsvd1 = 0;
265 obj[0].rsvd2 = 0;
266
267 obj[1].handle = src;
268 obj[1].relocation_count = 0;
269 obj[1].relocs_ptr = 0;
270 obj[1].alignment = 0;
271 obj[1].offset = 0;
272 obj[1].flags = 0;
273 obj[1].rsvd1 = 0;
274 obj[1].rsvd2 = 0;
275
276 obj[2].handle = handle;
277 obj[2].relocation_count = 2;
278 obj[2].relocs_ptr = (uintptr_t)reloc;
279 obj[2].alignment = 0;
280 obj[2].offset = 0;
281 obj[2].flags = 0;
282 obj[2].rsvd1 = obj[2].rsvd2 = 0;
283
284 exec.buffers_ptr = (uintptr_t)obj;
285 exec.buffer_count = 3;
286 exec.batch_start_offset = 0;
287 exec.batch_len = (b-batch)*sizeof(batch[0]);
288 exec.DR1 = exec.DR4 = 0;
289 exec.num_cliprects = 0;
290 exec.cliprects_ptr = 0;
291 exec.flags = 0;
292 i915_execbuffer2_set_context_id(exec, 0);
293 exec.rsvd2 = 0;
294
295 gem_execbuf(fd, &exec);
296
297 gem_close(fd, handle);
298 }
299
300 static uint32_t
create_bo(int fd,uint32_t val,int tiling)301 create_bo(int fd, uint32_t val, int tiling)
302 {
303 uint32_t handle;
304 uint32_t *v;
305 int i;
306
307 handle = gem_create(fd, WIDTH*HEIGHT*4);
308 gem_set_tiling(fd, handle, tiling, WIDTH*4);
309
310 /* Fill the BO with dwords starting at val */
311 v = gem_mmap__gtt(fd, handle, WIDTH * HEIGHT * 4,
312 PROT_READ | PROT_WRITE);
313 gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
314 for (i = 0; i < WIDTH*HEIGHT; i++)
315 v[i] = val++;
316 munmap(v, WIDTH*HEIGHT*4);
317
318 return handle;
319 }
320
321 static void
check_bo(int fd,uint32_t handle,uint32_t val)322 check_bo(int fd, uint32_t handle, uint32_t val)
323 {
324 uint32_t *v;
325 int i;
326
327 v = gem_mmap__gtt(fd, handle, WIDTH * HEIGHT * 4, PROT_READ);
328 gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, 0);
329 for (i = 0; i < WIDTH*HEIGHT; i++) {
330 igt_assert_f(v[i] == val,
331 "Expected 0x%08x, found 0x%08x "
332 "at offset 0x%08x\n",
333 val, v[i], i * 4);
334 val++;
335 }
336 munmap(v, WIDTH*HEIGHT*4);
337 }
338
339 int count;
340
opt_handler(int opt,int opt_index,void * data)341 static int opt_handler(int opt, int opt_index, void *data)
342 {
343 switch (opt) {
344 case 'c':
345 count = atoi(optarg);
346 break;
347 default:
348 return IGT_OPT_HANDLER_ERROR;
349 }
350
351 return IGT_OPT_HANDLER_SUCCESS;
352 }
353
354 const char *help_str = " -c\tBuffer count\n";
355
356 igt_simple_main_args("c:", NULL, help_str, opt_handler, NULL)
357 {
358 uint32_t *handle, *tiling, *start_val;
359 uint32_t start = 0;
360 int i, fd;
361
362 fd = drm_open_driver(DRIVER_INTEL);
363
364 igt_require(IS_GEN3(intel_get_drm_devid(fd)));
365
366 if (count == 0)
367 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
368 igt_info("Using %d 1MiB buffers\n", count);
369 intel_require_memory(count, 1024*1024, CHECK_RAM);
370
371 handle = malloc(sizeof(uint32_t)*count*3);
372 tiling = handle + count;
373 start_val = tiling + count;
374
375 for (i = 0; i < count; i++) {
376 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
377 start_val[i] = start;
378 start += 1024 * 1024 / 4;
379 }
380
381 igt_info("Verifying initialisation..."); fflush(stdout);
382 for (i = 0; i < count; i++)
383 check_bo(fd, handle[i], start_val[i]);
384 igt_info("done\n");
385
386 igt_info("Cyclic blits, forward..."); fflush(stdout);
387 for (i = 0; i < count * 32; i++) {
388 int src = i % count;
389 int dst = (i + 1) % count;
390
391 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
392 start_val[dst] = start_val[src];
393 }
394 igt_info("verifying..."); fflush(stdout);
395 for (i = 0; i < count; i++)
396 check_bo(fd, handle[i], start_val[i]);
397 igt_info("done\n");
398
399 igt_info("Cyclic blits, backward..."); fflush(stdout);
400 for (i = 0; i < count * 32; i++) {
401 int src = (i + 1) % count;
402 int dst = i % count;
403
404 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
405 start_val[dst] = start_val[src];
406 }
407 igt_info("verifying..."); fflush(stdout);
408 for (i = 0; i < count; i++)
409 check_bo(fd, handle[i], start_val[i]);
410 igt_info("done\n");
411
412 igt_info("Random blits..."); fflush(stdout);
413 for (i = 0; i < count * 32; i++) {
414 int src = random() % count;
415 int dst = random() % count;
416
417 while (src == dst)
418 dst = random() % count;
419
420 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
421 start_val[dst] = start_val[src];
422 }
423 igt_info("verifying..."); fflush(stdout);
424 for (i = 0; i < count; i++)
425 check_bo(fd, handle[i], start_val[i]);
426 igt_info("done\n");
427 }
428