1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <[email protected]>
25 * Jesse Barnes <[email protected]> (based on gem_bad_blit.c)
26 *
27 */
28
29 #include "igt.h"
30 #include <stdlib.h>
31 #include <stdio.h>
32 #include <string.h>
33 #include <fcntl.h>
34 #include <inttypes.h>
35 #include <errno.h>
36 #include <sys/stat.h>
37 #include <sys/time.h>
38 #include "drm.h"
39 #include "intel_bufmgr.h"
40
41 static drm_intel_bufmgr *bufmgr;
42 static drm_intel_bo *target_bo;
43 static int has_ppgtt = 0;
44
45 #define SECURE_DISPATCH (1<<0)
46
47 /* Like the store dword test, but we create new command buffers each time */
48 static void
store_dword_loop(int divider,unsigned flags)49 store_dword_loop(int divider, unsigned flags)
50 {
51 int cmd, i, val = 0;
52 uint32_t *buf;
53 drm_intel_bo *cmd_bo;
54
55 igt_info("running storedw loop with stall every %i batch\n", divider);
56
57 cmd = MI_STORE_DWORD_IMM;
58 if (!has_ppgtt)
59 cmd |= MI_MEM_VIRTUAL;
60
61 for (i = 0; i < SLOW_QUICK(0x2000, 4); i++) {
62 int j = 0;
63 int cmd_address_offset;
64 cmd_bo = drm_intel_bo_alloc(bufmgr, "cmd bo", 4096, 4096);
65 igt_assert(cmd_bo);
66
67 /* Upload through cpu mmaps to make sure we don't have a gtt
68 * mapping which could paper over secure batch submission
69 * failing to bind that. */
70 drm_intel_bo_map(cmd_bo, 1);
71 buf = cmd_bo->virtual;
72
73 buf[j++] = cmd;
74 if (intel_gen(drm_intel_bufmgr_gem_get_devid(bufmgr)) >= 8) {
75 cmd_address_offset = j * 4;
76 buf[j++] = target_bo->offset;
77 buf[j++] = 0;
78 } else {
79 buf[j++] = 0;
80 cmd_address_offset = j * 4;
81 buf[j++] = target_bo->offset;
82 }
83 igt_assert_lt(0, j);
84 buf[j++] = 0x42000000 + val;
85
86 igt_assert(drm_intel_bo_references(cmd_bo, target_bo) == 0);
87
88 igt_assert(drm_intel_bo_emit_reloc(cmd_bo, cmd_address_offset, target_bo, 0,
89 I915_GEM_DOMAIN_INSTRUCTION,
90 I915_GEM_DOMAIN_INSTRUCTION) == 0);
91 buf[j++] = MI_BATCH_BUFFER_END;
92 buf[j++] = MI_BATCH_BUFFER_END;
93
94 drm_intel_bo_unmap(cmd_bo);
95
96 igt_assert(drm_intel_bo_references(cmd_bo, target_bo) == 1);
97
98 #define LOCAL_I915_EXEC_SECURE (1<<9)
99 igt_assert(drm_intel_bo_mrb_exec(cmd_bo, j * 4, NULL, 0, 0,
100 I915_EXEC_BLT |
101 (flags & SECURE_DISPATCH ? LOCAL_I915_EXEC_SECURE : 0))
102 == 0);
103
104 if (i % divider != 0)
105 goto cont;
106
107 drm_intel_bo_wait_rendering(cmd_bo);
108
109 drm_intel_bo_map(target_bo, 1);
110
111 buf = target_bo->virtual;
112 igt_assert_f(buf[0] == (0x42000000 | val),
113 "value mismatch: cur 0x%08x, stored 0x%08x\n",
114 buf[0], 0x42000000 | val);
115
116 buf[0] = 0; /* let batch write it again */
117 drm_intel_bo_unmap(target_bo);
118
119 cont:
120 drm_intel_bo_unreference(cmd_bo);
121
122 val++;
123 }
124
125 igt_info("completed %d writes successfully\n", i);
126 }
127
128 int fd;
129 int devid;
130
131 igt_main
132 {
133 igt_skip_on_simulation();
134
135 igt_fixture {
136 fd = drm_open_driver(DRIVER_INTEL);
137 igt_require_gem(fd);
138 devid = intel_get_drm_devid(fd);
139
140 has_ppgtt = gem_uses_ppgtt(fd);
141
142 /* storedw needs gtt address on gen4+/g33 and snoopable memory.
143 * Strictly speaking we could implement this now ... */
144 igt_require(intel_gen(devid) >= 6);
145
146 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
147 igt_assert(bufmgr);
148
149 // drm_intel_bufmgr_gem_enable_reuse(bufmgr);
150
151 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
152 igt_assert(target_bo);
153 }
154
155 igt_subtest("normal") {
156 store_dword_loop(1, 0);
157 store_dword_loop(2, 0);
158 store_dword_loop(3, 0);
159 store_dword_loop(5, 0);
160 }
161
162 igt_subtest("secure-dispatch") {
163 store_dword_loop(1, SECURE_DISPATCH);
164 store_dword_loop(2, SECURE_DISPATCH);
165 store_dword_loop(3, SECURE_DISPATCH);
166 store_dword_loop(5, SECURE_DISPATCH);
167 }
168
169 igt_subtest("cached-mapping") {
170 gem_set_caching(fd, target_bo->handle, 1);
171 store_dword_loop(1, 0);
172 store_dword_loop(2, 0);
173 store_dword_loop(3, 0);
174 store_dword_loop(5, 0);
175 }
176
177 igt_subtest("uncached-mapping") {
178 gem_set_caching(fd, target_bo->handle, 0);
179 store_dword_loop(1, 0);
180 store_dword_loop(2, 0);
181 store_dword_loop(3, 0);
182 store_dword_loop(5, 0);
183 }
184
185 igt_fixture {
186 drm_intel_bo_unreference(target_bo);
187 drm_intel_bufmgr_destroy(bufmgr);
188
189 close(fd);
190 }
191 }
192