1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <[email protected]>
25 *
26 */
27
28 /** @file gem_linear_render_blits.c
29 *
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
32 *
33 * The goal is to simply ensure the basics work.
34 */
35
36 #include "igt.h"
37 #include <stdlib.h>
38 #include <sys/ioctl.h>
39 #include <stdio.h>
40 #include <string.h>
41 #include <fcntl.h>
42 #include <inttypes.h>
43 #include <errno.h>
44 #include <sys/stat.h>
45 #include <sys/time.h>
46
47 #include <drm.h>
48
49 #include "intel_bufmgr.h"
50
51 #define WIDTH 512
52 #define STRIDE (WIDTH*4)
53 #define HEIGHT 512
54 #define SIZE (HEIGHT*STRIDE)
55
56 static igt_render_copyfunc_t render_copy;
57 static drm_intel_bo *linear;
58 static uint32_t data[WIDTH*HEIGHT];
59 static int snoop;
60
61 static void
check_bo(struct intel_batchbuffer * batch,struct igt_buf * buf,uint32_t val)62 check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val)
63 {
64 struct igt_buf tmp = {};
65 uint32_t *ptr;
66 int i;
67
68 tmp.bo = linear;
69 tmp.stride = STRIDE;
70 tmp.tiling = I915_TILING_NONE;
71 tmp.size = SIZE;
72 tmp.bpp = 32;
73
74 render_copy(batch, NULL, buf, 0, 0, WIDTH, HEIGHT, &tmp, 0, 0);
75 if (snoop) {
76 do_or_die(drm_intel_bo_map(linear, 0));
77 ptr = linear->virtual;
78 } else {
79 do_or_die(drm_intel_bo_get_subdata(linear, 0, sizeof(data), data));
80 ptr = data;
81 }
82 for (i = 0; i < WIDTH*HEIGHT; i++) {
83 igt_assert_f(ptr[i] == val,
84 "Expected 0x%08x, found 0x%08x "
85 "at offset 0x%08x\n",
86 val, ptr[i], i * 4);
87 val++;
88 }
89 if (ptr != data)
90 drm_intel_bo_unmap(linear);
91 }
92
run_test(int fd,int count)93 static void run_test (int fd, int count)
94 {
95 drm_intel_bufmgr *bufmgr;
96 struct intel_batchbuffer *batch;
97 uint32_t *start_val;
98 struct igt_buf *buf;
99 uint32_t start = 0;
100 int i, j;
101 uint32_t devid;
102
103 devid = intel_get_drm_devid(fd);
104
105 render_copy = igt_get_render_copyfunc(devid);
106 igt_require(render_copy);
107
108 snoop = 1;
109 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
110 snoop = 0;
111 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) /* snafu */
112 snoop = 0;
113
114 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
115 drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 32);
116 batch = intel_batchbuffer_alloc(bufmgr, devid);
117
118 linear = drm_intel_bo_alloc(bufmgr, "linear", WIDTH*HEIGHT*4, 0);
119 if (snoop) {
120 gem_set_caching(fd, linear->handle, 1);
121 igt_info("Using a snoop linear buffer for comparisons\n");
122 }
123
124 buf = calloc(sizeof(*buf), count);
125 start_val = malloc(sizeof(*start_val)*count);
126
127 for (i = 0; i < count; i++) {
128 uint32_t tiling = I915_TILING_X + (random() & 1);
129 unsigned long pitch = STRIDE;
130 uint32_t *ptr;
131
132 buf[i].bo = drm_intel_bo_alloc_tiled(bufmgr, "",
133 WIDTH, HEIGHT, 4,
134 &tiling, &pitch, 0);
135 buf[i].stride = pitch;
136 buf[i].tiling = tiling;
137 buf[i].size = SIZE;
138 buf[i].bpp = 32;
139
140 start_val[i] = start;
141
142 do_or_die(drm_intel_gem_bo_map_gtt(buf[i].bo));
143 ptr = buf[i].bo->virtual;
144 for (j = 0; j < WIDTH*HEIGHT; j++)
145 ptr[j] = start++;
146 drm_intel_gem_bo_unmap_gtt(buf[i].bo);
147 }
148
149 igt_info("Verifying initialisation...\n");
150 for (i = 0; i < count; i++)
151 check_bo(batch, &buf[i], start_val[i]);
152
153 igt_info("Cyclic blits, forward...\n");
154 for (i = 0; i < count * 4; i++) {
155 int src = i % count;
156 int dst = (i + 1) % count;
157
158 render_copy(batch, NULL, buf+src, 0, 0, WIDTH, HEIGHT, buf+dst, 0, 0);
159 start_val[dst] = start_val[src];
160 }
161 for (i = 0; i < count; i++)
162 check_bo(batch, &buf[i], start_val[i]);
163
164 igt_info("Cyclic blits, backward...\n");
165 for (i = 0; i < count * 4; i++) {
166 int src = (i + 1) % count;
167 int dst = i % count;
168
169 render_copy(batch, NULL, buf+src, 0, 0, WIDTH, HEIGHT, buf+dst, 0, 0);
170 start_val[dst] = start_val[src];
171 }
172 for (i = 0; i < count; i++)
173 check_bo(batch, &buf[i], start_val[i]);
174
175 igt_info("Random blits...\n");
176 for (i = 0; i < count * 4; i++) {
177 int src = random() % count;
178 int dst = random() % count;
179
180 if (src == dst)
181 continue;
182
183 render_copy(batch, NULL, buf+src, 0, 0, WIDTH, HEIGHT, buf+dst, 0, 0);
184 start_val[dst] = start_val[src];
185 }
186 for (i = 0; i < count; i++)
187 check_bo(batch, &buf[i], start_val[i]);
188
189 /* release resources */
190 drm_intel_bo_unreference(linear);
191 for (i = 0; i < count; i++) {
192 drm_intel_bo_unreference(buf[i].bo);
193 }
194 intel_batchbuffer_free(batch);
195 drm_intel_bufmgr_destroy(bufmgr);
196 }
197
198
199 igt_main
200 {
201 int fd = 0;
202 int count = 0;
203
204 igt_fixture {
205 fd = drm_open_driver(DRIVER_INTEL);
206 igt_require_gem(fd);
207 }
208
209 igt_subtest("basic") {
210 run_test(fd, 2);
211 }
212
213 /* the rest of the tests are too long for simulation */
214 igt_skip_on_simulation();
215
216 igt_subtest("aperture-thrash") {
217 count = 3 * gem_aperture_size(fd) / SIZE / 2;
218 intel_require_memory(count, SIZE, CHECK_RAM);
219 run_test(fd, count);
220 }
221
222 igt_subtest("aperture-shrink") {
223 igt_fork_shrink_helper(fd);
224
225 count = 3 * gem_aperture_size(fd) / SIZE / 2;
226 intel_require_memory(count, SIZE, CHECK_RAM);
227 run_test(fd, count);
228
229 igt_stop_shrink_helper();
230 }
231
232 igt_subtest("swap-thrash") {
233 uint64_t swap_mb = intel_get_total_swap_mb();
234 igt_require(swap_mb > 0);
235 count = ((intel_get_avail_ram_mb() + (swap_mb / 2)) * 1024*1024) / SIZE;
236 intel_require_memory(count, SIZE, CHECK_RAM | CHECK_SWAP);
237 run_test(fd, count);
238 }
239 }
240