1 /* Copyright 2016 The ChromiumOS Authors 2 * Use of this source code is governed by a BSD-style license that can be 3 * found in the LICENSE file. 4 */ 5 6 /* 7 * config.h - Top-level configuration Chrome EC 8 * 9 * All configuration settings (CONFIG_*) are defined in this file or in a 10 * sub-configuration file (config_chip.h, board.h, etc.) included by this file. 11 * 12 * Note that this file is included by assembly (.S) files. Any C-isms such as 13 * struct definitions or enums in a sub-configuration file MUST be guarded with 14 * #ifndef __ASSEMBLER__ to prevent those C-isms from being evaluated by the 15 * assembler. 16 */ 17 18 #ifndef __CROS_EC_CONFIG_H 19 #define __CROS_EC_CONFIG_H 20 21 #ifdef INCLUDE_ENV_CONFIG 22 /* 23 * When building for an EC target, pick up the .h file which allows to 24 * keep track of changing make variables. 25 */ 26 #include "env_config.h" 27 #endif 28 29 /* 30 * All config options are listed alphabetically and described here. 31 * 32 * If you add a new config option somewhere in the code, you must add a 33 * default value here and describe what it does. 34 * 35 * To get a list current list, run this command: 36 * git grep " CONFIG_" | grep -o "CONFIG_[A-Za-z0-9_]\+" | sort | uniq 37 * 38 * Some options are #defined here to enable them by default. Chips or boards 39 * may override this by #undef'ing them in config_chip.h or board.h, 40 * respectively. 41 * 42 * TODO(crosbug.com/p/23758): Describe all of these. Also describe the 43 * HAS_TASK_* macro and how/when it should be used vs. a config define. And 44 * BOARD_*, CHIP_*, and CHIP_FAMILY_*. 45 */ 46 47 /* Add support for sensor FIFO */ 48 #undef CONFIG_ACCEL_FIFO 49 50 /* Define the size of the global fifo, must be a power of 2. */ 51 #undef CONFIG_ACCEL_FIFO_SIZE 52 53 /* The amount of free entries that trigger an interrupt to the AP. */ 54 #undef CONFIG_ACCEL_FIFO_THRES 55 56 /* 57 * Sensors in this mask are in forced mode: they needed to be polled 58 * at their data rate frequency. 59 */ 60 #undef CONFIG_ACCEL_FORCE_MODE_MASK 61 62 /* Enable accelerometer interrupts. */ 63 #undef CONFIG_ACCEL_INTERRUPTS 64 65 /* 66 * Support "spoof" mode for sensors. This allows sensors to have their values 67 * spoofed to any arbitrary value. This is useful for testing. 68 */ 69 #define CONFIG_ACCEL_SPOOF_MODE 70 71 /* 72 * Some chips have a portion of memory which will remain powered even 73 * during a reset. This is called Always-On, or AON memory, and 74 * typically has a separate firmware to manage the memory. These 75 * values can be used to configure the RAM layout for Always-On. 76 * 77 * See chip/ish/ for an example implementation. 78 */ 79 #undef CONFIG_AON_PERSISTENT_BASE 80 #undef CONFIG_AON_PERSISTENT_SIZE 81 #undef CONFIG_AON_RAM_BASE 82 #undef CONFIG_AON_RAM_SIZE 83 84 /* Specify type of Magnetometer attached. */ 85 #undef CONFIG_MAG_BMM150 86 87 /* Presence of a Bosh Sensortec BMM150 magnetometer behind a BMI160. */ 88 #undef CONFIG_MAG_BMI160_BMM150 89 90 /* Presence of a ST LIS2MDL magnetometer behind a BMI160. */ 91 #undef CONFIG_MAG_BMI160_LIS2MDL 92 93 /* Specify barometer attached */ 94 #undef CONFIG_BARO_BMP280 95 96 /* When set, it indicates a secondary sensor is attached behind a BMI160. */ 97 #undef CONFIG_BMI160_SEC_I2C 98 99 /* Support for BMI160 hardware orientation sensor */ 100 #undef CONFIG_BMI160_ORIENTATION_SENSOR 101 102 /* Support for KIONIX KX022 hardware orientation sensor */ 103 #undef CONFIG_KX022_ORIENTATION_SENSOR 104 105 /* Define the i2c address of the sensor behind the main sensor, if present. */ 106 #undef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS 107 108 /* 109 * Define if either CONFIG_BMI160_ORIENTATION_SUPPORT or 110 * CONFIG_KX022_ORIENTATION_SUPPORT is set. 111 */ 112 #undef CONFIG_ORIENTATION_SENSOR 113 114 /* Support the orientation gesture */ 115 #undef CONFIG_GESTURE_ORIENTATION 116 117 /* 118 * Use the old standard reference frame for accelerometers. The old 119 * reference frame is: 120 * Z-axis: perpendicular to keyboard, pointing up, such that if the device 121 * is sitting flat on a table, the accel reads +G. 122 * X-axis: in the plane of the keyboard, pointing from the front lip to the 123 * hinge, such that if the device is oriented with the front lip touching 124 * the table and the hinge directly above, the accel reads +G. 125 * Y-axis: in the plane of the keyboard, pointing to the right, such that 126 * if the device is on it's left side, the accel reads +G. 127 * 128 * Also, in the old reference frame, the lid accel matches the base accel 129 * readings when lid is closed. 130 */ 131 #undef CONFIG_ACCEL_STD_REF_FRAME_OLD 132 133 /* Set when INT2 is an ouptut */ 134 #undef CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT 135 136 /* Specify type of Gyrometers attached. */ 137 #undef CONFIG_GYRO_L3GD20H 138 139 /* 140 * If this is defined, motion_sense sends sensor events to the AP in the format 141 * +-----------+ 142 * | Timestamp | 143 * | Payload | 144 * | Timestamp | 145 * | Payload | 146 * | ... | 147 * +-----------+ 148 * 149 * If this is not defined, the events will be sent in the format 150 * +-----------+ 151 * | Payload | 152 * | Payload | 153 * | Payload | 154 * | ... | 155 * | Timestamp | 156 * +-----------+ 157 * 158 * The former format enables improved filtering of sensor event timestamps on 159 * the AP, but comes with stricter jitter requirements. 160 */ 161 #define CONFIG_SENSOR_TIGHT_TIMESTAMPS 162 163 /* Sync event driver */ 164 #undef CONFIG_SYNC 165 166 /* 167 * How many sync events to buffer before motion_sense gets a chance to run. 168 * This is similar to sensor side fifos. 169 * Note: for vsync, anything above 2 is probably plenty. 170 */ 171 #define CONFIG_SYNC_QUEUE_SIZE 8 172 173 /* Simulate command for sync */ 174 #undef CONFIG_SYNC_COMMAND 175 176 /* 177 * Define the event to raise when the sync event happens. 178 * Must be within TASK_EVENT_MOTION_INTERRUPT_MASK. 179 */ 180 #undef CONFIG_SYNC_INT_EVENT 181 182 /* Compile chip support for analog-to-digital convertor */ 183 #undef CONFIG_ADC 184 185 /* 186 * ADC sample time selection. The value is chip-dependent. 187 * TODO: Replace this with CONFIG_ADC_PROFILE entries. 188 */ 189 #undef CONFIG_ADC_SAMPLE_TIME 190 191 /* Include the ADC analog watchdog feature in the ADC code */ 192 #define CONFIG_ADC_WATCHDOG 193 194 /* 195 * Chip-dependent ADC configuration - select one. 196 * SINGLE - Sample all inputs once when requested. 197 * FAST_CONTINUOUS - Sample all inputs continuously using DMA, with minimal 198 * sample time. 199 */ 200 #define CONFIG_ADC_PROFILE_SINGLE 201 #undef CONFIG_ADC_PROFILE_FAST_CONTINUOUS 202 203 /* Support AES symmetric-key algorithm */ 204 #undef CONFIG_AES 205 206 /* Support AES-GCM */ 207 #undef CONFIG_AES_GCM 208 209 /* 210 * Some ALS modules may be connected to the EC. We need the command, and 211 * specific drivers for each module. 212 */ 213 #ifdef HAS_TASK_ALS 214 #define CONFIG_ALS 215 #else 216 #undef CONFIG_ALS 217 #endif 218 #undef CONFIG_ALS_AL3010 219 #undef CONFIG_ALS_BH1730 220 /* 221 * If defined, BH1730 uses board specific lux calculation formula parameters. 222 * If not defined, BH1730 uses default parameters to calculate lux. 223 */ 224 #undef CONFIG_ALS_BH1730_LUXTH_PARAMS 225 #undef CONFIG_ALS_ISL29035 226 #undef CONFIG_ALS_OPT3001 227 /* Define the exact model ID present on the board: SI1141 = 41, SI1142 = 42, */ 228 #undef CONFIG_ALS_SI114X 229 /* Check if the device revision is supported */ 230 #undef CONFIG_ALS_SI114X_CHECK_REVISION 231 232 /* Define to include the clear channel driver for the tcs3400 light sensor */ 233 #undef CONFIG_ALS_TCS3400 234 235 /* 236 * Define to use atime tables in anti-saturation algos in the tcs3400 driver. 237 * Defining this for a board makes the anti-saturation algorithm much more 238 * efficient, but requires the board to have it's lens cover scale and k_channel 239 * scales to be determined. Define this for a board once it's added its 240 * cover_scale and k_channel scale factors. 241 */ 242 #undef CONFIG_TCS_USE_LUX_TABLE 243 244 /* 245 * Define the event to raise when a sensor interrupt triggers. 246 * Must be within TASK_EVENT_MOTION_INTERRUPT_MASK. 247 */ 248 #undef CONFIG_ALS_SI114X_INT_EVENT 249 #undef CONFIG_ALS_TCS3400_INT_EVENT 250 251 /* 252 * Enable Si114x to operate in polling mode. This config is used in conjunction 253 * with CONFIG_ALS_SI114X_INT_EVENT. When polling is enabled, the read is 254 * initiated in the same manner as when interrupts are used, but the event which 255 * triggers the irq_handler is generated by deferred call using a fixed delay. 256 */ 257 #undef CONFIG_ALS_SI114X_POLLING 258 259 /* 260 * Enable tcs3400 to operate without interrupt pin. This config is used in 261 * conjunction with CONFIG_ALS_TCS3400_INT_EVENT. When this option is enabled, 262 * the read is initiated in the same manner as when interrupts are used, but the 263 * event which triggers the irq_handler is generated by deferred call. 264 */ 265 #undef CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT 266 267 /* Define which ALS sensor is used for dimming the lightbar when dark */ 268 #undef CONFIG_ALS_LIGHTBAR_DIMMING 269 270 /* Link against third_party/cryptoc. */ 271 #undef CONFIG_LIBCRYPTOC 272 273 /* Support AP hang detection host command and state machine */ 274 #undef CONFIG_AP_HANG_DETECT 275 276 /* Support AP Warm reset Interrupt. */ 277 #undef CONFIG_AP_WARM_RESET_INTERRUPT 278 279 /* Support audio codec. */ 280 #undef CONFIG_AUDIO_CODEC 281 /* Audio codec caps. */ 282 #undef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM 283 #undef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM 284 /* Support audio codec on DMIC. */ 285 #undef CONFIG_AUDIO_CODEC_DMIC 286 /* Support audio codec software gain on DMIC. */ 287 #undef CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN 288 #undef CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN 289 /* Support audio codec on I2S RX. */ 290 #undef CONFIG_AUDIO_CODEC_I2S_RX 291 /* Support audio codec on WoV. */ 292 #undef CONFIG_AUDIO_CODEC_WOV 293 /* Audio codec buffers. */ 294 #undef CONFIG_AUDIO_CODEC_WOV_AUDIO_BUF_LEN 295 #undef CONFIG_AUDIO_CODEC_WOV_AUDIO_BUF_TYPE 296 #undef CONFIG_AUDIO_CODEC_WOV_LANG_BUF_LEN 297 #undef CONFIG_AUDIO_CODEC_WOV_LANG_BUF_TYPE 298 299 /* Allow proprietary communication protocols' extensions. */ 300 #undef CONFIG_EXTENSION_COMMAND 301 302 /* 303 * Support controlling the display backlight based on the state of the lid 304 * switch. The EC will disable the backlight when the lid is closed. 305 * 306 * The GPIO should be named GPIO_ENABLE_BACKLIGHT if active high, or 307 * GPIO_ENABLE_BACKLIGHT_L if active low. See CONFIG_BACKLIGHT_LID_ACTIVE_LOW. 308 */ 309 #undef CONFIG_BACKLIGHT_LID 310 311 /* 312 * The backlight GPIO pin is active low and named GPIO_BACKLIGHT_ENABLED_L 313 */ 314 #undef CONFIG_BACKLIGHT_LID_ACTIVE_LOW 315 316 /* 317 * If defined, EC will enable the backlight signal only if this GPIO is 318 * asserted AND the lid is open. This supports passing the backlight-enable 319 * signal from the AP through EC. 320 */ 321 #undef CONFIG_BACKLIGHT_REQ_GPIO 322 323 /* Support base32 text encoding */ 324 #undef CONFIG_BASE32 325 326 /* Support base64 text encoding */ 327 #undef CONFIG_BASE64 328 329 /*****************************************************************************/ 330 /* Battery config */ 331 332 /* Support a simple battery. */ 333 #undef CONFIG_BATTERY 334 335 /* 336 * Compile battery-specific code. 337 * 338 * Note that some boards have their own unique battery constants / functions. 339 * In this case, those are provided in board/(boardname)/battery.c, and none of 340 * these are defined. 341 * Defining one of these will automatically define CONFIG_BATTERY near the end 342 * of this file. If you add a new config here, you'll need to update that 343 * check. 344 */ 345 #undef CONFIG_BATTERY_BQ20Z453 346 #undef CONFIG_BATTERY_BQ27541 347 #undef CONFIG_BATTERY_BQ27621 348 #undef CONFIG_BATTERY_BQ4050 349 #undef CONFIG_BATTERY_MAX17055 350 #undef CONFIG_BATTERY_MM8013 351 352 /* 353 * MAX17055 support alert on voltage, current, temperature, and state-of-charge. 354 */ 355 #undef CONFIG_BATTERY_MAX17055_ALERT 356 357 /* 358 * Enable full model driver of MAX17055. 359 * 360 * It provides a better soc estimation. ocv_table needs to be supplied. 361 */ 362 #undef CONFIG_BATTERY_MAX17055_FULL_MODEL 363 364 /* Compile mock battery support; used by tests. */ 365 #undef CONFIG_BATTERY_MOCK 366 367 /* Maximum time to wake a non-responsive battery, in second */ 368 #define CONFIG_BATTERY_PRECHARGE_TIMEOUT 30 369 370 /* 371 * If defined, the charger will check a board specific function for battery hw 372 * presence as an additional condition to determine if power on is allowed for 373 * factory override, where allowing booting of a bare board with no battery and 374 * no power button press is required. 375 */ 376 #undef CONFIG_BATTERY_HW_PRESENT_CUSTOM 377 378 /* 379 * If defined, the charger will check for battery presence before attempting 380 * to communicate with it. This avoids the 30 second delay when booting 381 * without a battery present. Do not use with CONFIG_BATTERY_PRESENT_GPIO. 382 * 383 * Replace the default battery_is_present() function with a board-specific 384 * implementation in board.c 385 */ 386 #undef CONFIG_BATTERY_PRESENT_CUSTOM 387 388 /* 389 * If defined, GPIO which is driven low when battery is present. 390 * Charger will check for battery presence before attempting to communicate 391 * with it. This avoids the 30 second delay when booting without a battery 392 * present. Do not use with CONFIG_BATTERY_PRESENT_CUSTOM. 393 */ 394 #undef CONFIG_BATTERY_PRESENT_GPIO 395 396 /* 397 * Compile smart battery support 398 * 399 * For batteries which support this specification: 400 * http://sbs-forum.org/specs/sbdat110.pdf) 401 */ 402 #undef CONFIG_BATTERY_SMART 403 404 /* Chemistry of the battery device */ 405 #undef CONFIG_BATTERY_DEVICE_CHEMISTRY 406 407 /* 408 * If defined, the board must supply fuel gauge and battery information for 409 * each supported battery. This information is then used for battery cut off 410 * and to check the charge/discharge FET status. 411 */ 412 #undef CONFIG_BATTERY_FUEL_GAUGE 413 414 /* 415 * Critical battery shutdown timeout (seconds) 416 * 417 * If the battery is at extremely low charge (and discharging) or extremely 418 * high temperature, the EC will notify the AP and start a timer with the 419 * timeout defined here. If the critical condition is not corrected before 420 * the timeout expires, the EC will shut down the AP (if the AP is not already 421 * off) and then optionally hibernate or cut off battery. 422 */ 423 #define CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT 30 424 425 /* Perform a battery cut-off when we reach the battery critical level */ 426 #undef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF 427 428 /* If the battery is too hot or too cold, stop charging */ 429 #undef CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS 430 431 /* 432 * Support battery cut-off as host command and console command. 433 * 434 * Once defined, you have to implement a board_cut_off_battery() function 435 * in board/???/battery.c file. 436 */ 437 #undef CONFIG_BATTERY_CUT_OFF 438 439 /* 440 * The default delay is 1 second. Define this if a board prefers 441 * different delay. 442 */ 443 #undef CONFIG_BATTERY_CUTOFF_DELAY_US 444 445 /* 446 * The board-specific battery.c implements get and set functions to read and 447 * write arbirary vendor-specific parameters stored in the battery. 448 * See include/battery.h for prototypes. 449 */ 450 #undef CONFIG_BATTERY_VENDOR_PARAM 451 452 /* 453 * TODO(crosbug.com/p/29467): allows charging of a dead battery that 454 * requests nil for current and voltage. Remove this workaround when 455 * possible. 456 */ 457 #undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD 458 459 /* 460 * Check for battery in disconnect state (similar to cut-off state). If this 461 * battery is found to be in disconnect state, take it out of this state by 462 * force-applying a charge current. This option requires 463 * battery_get_disconnect_state() to be defined. 464 */ 465 #undef CONFIG_BATTERY_REVIVE_DISCONNECT 466 467 /* 468 * Specify the battery percentage at which the host is told it is full. 469 * If this value is not specified the default is 97% set in battery.h. 470 */ 471 #undef CONFIG_BATTERY_LEVEL_NEAR_FULL 472 473 /* 474 * Use an alternative method to store battery information: Instead of writing 475 * directly to host memory mapped region, this keeps the battery information in 476 * ec_response_battery_static/dynamic_info structures, that can then be fetched 477 * using host commands, or via EC_ACPI_MEM_BATTERY_INDEX command, which tells 478 * the EC to update the shared memory. 479 * 480 * This is required on dual-battery systems, and on on hostless bases with a 481 * battery. 482 */ 483 #undef CONFIG_BATTERY_V2 484 485 /* 486 * Some fuel gauges in battery take some time to return valid battery params 487 * when wake form dead battery. 488 * It need to do precharge to take valid battery params. 489 */ 490 #undef CONFIG_BATTERY_DEAD_UNTIL_VALUE 491 492 /* 493 * Number of batteries, only matters when CONFIG_BATTERY_V2 is used. 494 */ 495 #undef CONFIG_BATTERY_COUNT 496 497 /* 498 * Smart battery driver should measure the voltage cell imbalance in the battery 499 * pack. This requires a battery driver capable of the measurement. 500 */ 501 #undef CONFIG_BATTERY_MEASURE_IMBALANCE 502 503 /* 504 * If remaining capacity is x% of full capacity, remaining capacity is set 505 * equal to full capacity. 506 * 507 * Some batteries don't update full capacity timely or don't update it at all. 508 * On such systems, compensation is required to guarantee remaining_capacity 509 * will be equal to full_capacity eventually. This used to be done in ACPI. 510 */ 511 #define CONFIG_BATT_FULL_FACTOR 98 512 #define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 513 514 /* 515 * Powerd's full_factor. It has to be 100(%) to get display battery percentage. 516 * Otherwise, display percentages will be always zero. 517 */ 518 #define CONFIG_BATT_HOST_FULL_FACTOR 94 519 520 /* 521 * Expose some data when it is needed. 522 * For example, battery disconnect state 523 */ 524 #undef CONFIG_CHARGE_STATE_DEBUG 525 526 /* Include debugging support for the Bluetooth link layer */ 527 #undef CONFIG_BLUETOOTH_LL_DEBUG 528 529 /* Include debugging support for Bluetooth HCI */ 530 #undef CONFIG_BLUETOOTH_HCI_DEBUG 531 532 /* Boot header storage offset. */ 533 #undef CONFIG_BOOT_HEADER_STORAGE_OFF 534 535 /* Size of boot header in storage. */ 536 #undef CONFIG_BOOT_HEADER_STORAGE_SIZE 537 538 /*****************************************************************************/ 539 /* Bootblock config */ 540 541 /* Pack AP-FW bootblock in EC image. */ 542 #undef CONFIG_BOOTBLOCK 543 544 /*****************************************************************************/ 545 546 /* EC has GPIOs to allow board to reset RTC */ 547 #undef CONFIG_BOARD_HAS_RTC_RESET 548 549 /* 550 * Call board_before_rsmrst(state) before passing RSMRST# to the AP. 551 * This is for board workarounds that are required after rails are up 552 * but before the AP is out of reset. 553 */ 554 #undef CONFIG_BOARD_HAS_BEFORE_RSMRST 555 556 /* 557 * Call board_config_post_gpio_init() after GPIOs are initialized. See 558 * include/board_config.h for more information. 559 */ 560 #undef CONFIG_BOARD_POST_GPIO_INIT 561 562 /* 563 * Call board_config_pre_init() before any inits are called. See 564 * include/board_config.h for more information. 565 */ 566 #undef CONFIG_BOARD_PRE_INIT 567 568 /* EC has GPIOs attached to board version stuffing resistors */ 569 #undef CONFIG_BOARD_VERSION 570 /* The decoding of the GPIOs defining board version is defined in board code */ 571 #undef CONFIG_BOARD_SPECIFIC_VERSION 572 573 /* 574 * The board is unable to distinguish EC reset from power-on so it should treat 575 * all resets as triggered by RESET_PIN even if it is a POWER_ON reset. 576 */ 577 #undef CONFIG_BOARD_FORCE_RESET_PIN 578 579 /* Permanent LM4 boot configuration */ 580 #undef CONFIG_BOOTCFG_VALUE 581 582 /*****************************************************************************/ 583 /* Modify the default behavior to make system bringup easier. */ 584 #undef CONFIG_BRINGUP 585 586 /* 587 * Enable debug prints / asserts that may helpful for debugging board bring-up, 588 * but probably shouldn't be enabled for production for performance reasons. 589 */ 590 #undef CONFIG_DEBUG_BRINGUP 591 592 /*****************************************************************************/ 593 594 /* 595 * Support for entering recovery mode using the volume buttons or a dedicated 596 * recovery button. Note that these are *buttons* and not keys in the keyboard 597 * matrix. 598 */ 599 #undef CONFIG_BUTTON_TRIGGERED_RECOVERY 600 601 /* 602 * Compile detachable base support 603 * 604 * Enabled on all boards that have a detachable base. 605 */ 606 #undef CONFIG_DETACHABLE_BASE 607 608 /* 609 * Indicates there is a dedicated recovery button. Note, that if there are 610 * volume buttons, a dedicated recovery button is not needed. This is intended 611 * because if a board has volume buttons, they can do everything a dedicated 612 * recovery button can do. 613 */ 614 #undef CONFIG_DEDICATED_RECOVERY_BUTTON 615 616 /* 617 * The board has volume up and volume down buttons. Note, these are *buttons* 618 * and not keys in the keyboard matrix. 619 */ 620 #undef CONFIG_VOLUME_BUTTONS 621 622 /* Support V1 CCD configuration */ 623 #undef CONFIG_CASE_CLOSED_DEBUG_V1 624 /* Allow unsafe debugging functionality in V1 configuration */ 625 #undef CONFIG_CASE_CLOSED_DEBUG_V1_UNSAFE 626 /* Enable ITE EC programming by CCD using the INA i2c interface. */ 627 #undef CONFIG_CCD_ITE_PROGRAMMING 628 /* Loosen Open restrictions for prePVT devices */ 629 #undef CONFIG_CCD_OPEN_PREPVT 630 631 /* 632 * Capsense chip has buttons, too. 633 */ 634 #undef CONFIG_CAPSENSE 635 636 /*****************************************************************************/ 637 /* Support CEC */ 638 #undef CONFIG_CEC 639 640 /*****************************************************************************/ 641 642 /* Compile charge manager */ 643 #undef CONFIG_CHARGE_MANAGER 644 645 /* 646 * Number of charge ports excluding type-c ports 647 * 648 * If defined, the board must define a macro DEDICATED_CHARGE_PORT indicates 649 * the dedicated port number. 650 * 651 * See include/charge_manager.h for more details about dedicated port. 652 */ 653 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 0 654 655 /* Allow charge manager to default to charging from dual-role partners */ 656 #undef CONFIG_CHARGE_MANAGER_DRP_CHARGING 657 658 /* Handle the external power limit host command in charge manager */ 659 #undef CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT 660 661 /* Initially enter safe mode, with relaxed port / current selection rules */ 662 #define CONFIG_CHARGE_MANAGER_SAFE_MODE 663 664 /* Leave safe mode when battery pct meets or exceeds this value */ 665 #define CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT 2 666 667 /* The hardware has some input current ramping/back-off mechanism */ 668 #undef CONFIG_CHARGE_RAMP_HW 669 670 /* Compile input current ramping support using software control */ 671 #undef CONFIG_CHARGE_RAMP_SW 672 673 /*****************************************************************************/ 674 /* Charger config */ 675 676 /* Compile common charge state code. */ 677 #undef CONFIG_CHARGER 678 679 /* Compile charger-specific code for these chargers (pick at most one) */ 680 #undef CONFIG_CHARGER_BD9995X 681 #undef CONFIG_CHARGER_BQ24707A 682 #undef CONFIG_CHARGER_BQ24715 683 #undef CONFIG_CHARGER_BQ24725 684 #undef CONFIG_CHARGER_BQ24735 685 #undef CONFIG_CHARGER_BQ24738 686 #undef CONFIG_CHARGER_BQ24770 687 #undef CONFIG_CHARGER_BQ24773 688 #undef CONFIG_CHARGER_BQ25703 689 #undef CONFIG_CHARGER_BQ25710 690 #undef CONFIG_CHARGER_BQ25890 691 #undef CONFIG_CHARGER_BQ25892 692 #undef CONFIG_CHARGER_BQ25895 693 #undef CONFIG_CHARGER_ISL9237 694 #undef CONFIG_CHARGER_ISL9238 695 #undef CONFIG_CHARGER_ISL9241 696 #undef CONFIG_CHARGER_MT6370 697 #undef CONFIG_CHARGER_RT9466 698 #undef CONFIG_CHARGER_RT9467 699 #undef CONFIG_CHARGER_SY21612 700 701 /* 702 * Enable the CHG_EN at initialization to turn-on the BGATE which allows voltage 703 * to be applied to the battery PACK & wakes the battery if it is in shipmode. 704 */ 705 #undef CONFIG_CHARGER_BD9995X_CHGEN 706 707 /* 708 * BD9995X Power Save Mode 709 * 710 * Which power save mode should the charger enter when VBUS is removed. Check 711 * driver/bd9995x.h for the power save settings. By default, no power save mode 712 * is enabled. 713 */ 714 #undef CONFIG_BD9995X_POWER_SAVE_MODE 715 716 /* 717 * If the battery temperature sense pin is connected to charger, 718 * get the battery temperature from the charger. 719 */ 720 #undef CONFIG_CHARGER_BATTERY_TSENSE 721 722 /* 723 * BQ2589x IR Compensation settings. 724 * Should be the combination of BQ2589X_IR_TREG_xxxC, BQ2589X_IR_VCLAMP_yyyMV 725 * and BQ2589X_IR_BAT_COMP_zzzMOHM. 726 */ 727 #undef CONFIG_CHARGER_BQ2589X_IR_COMP 728 /* 729 * BQ2589x 5V boost current limit and voltage. 730 * Should be the combination of BQ2589X_BOOSTV_MV(voltage) and 731 * BQ2589X_BOOST_LIM_xxxMA. 732 */ 733 #undef CONFIG_CHARGER_BQ2589X_BOOST 734 735 /* 736 * Board specific charging current limit, in mA. If defined, the charge state 737 * machine will not allow the battery to request more current than this. 738 */ 739 #undef CONFIG_CHARGER_CURRENT_LIMIT 740 741 /* 742 * MT6370 backlight control settings. 743 * If defined, Panel backlight power is controlled by MT6370. 744 */ 745 #undef CONFIG_CHARGER_MT6370_BACKLIGHT 746 747 /* 748 * MT6370 BC1.2 USB-PHY control. 749 * If defined, USB-PHY connection is controlled by GPIO_BC12_DET_EN. 750 * Assert GPIO_BC12_DET_EN to detect BC1.2 device, and deassert 751 * GPIO_BC12_DET_EN to mux USB-PHY back. 752 */ 753 #undef CONFIG_CHARGER_MT6370_BC12_GPIO 754 755 /* 756 * Enable/disable system power monitor PSYS function: this enables output 757 * from charger chip to SoC. 758 */ 759 #undef CONFIG_CHARGER_PSYS 760 761 /* 762 * Enable reading PSYS (system power) value, either via "psys" console command, 763 * or via charger_get_system_power function. 764 */ 765 #undef CONFIG_CHARGER_PSYS_READ 766 767 /* 768 * Board specific charging current termination limit, in mA. If defined and 769 * charger supports setting termination current it should be set during charger 770 * init. 771 * 772 * TODO(tbroch): Only valid for bq2589x currently. Configure defaults for other 773 * charger ICs that support termination currents. 774 */ 775 #undef CONFIG_CHARGER_TERM_CURRENT_LIMIT 776 777 /* 778 * Board supports discharge mode. In this mode, the battery will discharge 779 * even if AC is present. Used for testing. 780 */ 781 #undef CONFIG_CHARGER_DISCHARGE_ON_AC 782 783 /* Board has a custom discharge mode. */ 784 #undef CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM 785 786 /* 787 * Board specific flag used to disable external ILIM pin used to determine input 788 * current limit. When defined, the input current limit is decided only by 789 * the software register value. 790 */ 791 #undef CONFIG_CHARGER_ILIM_PIN_DISABLED 792 793 /* 794 * Default input current for the board, in mA. Many boards also use this as the 795 * least maximum input current during transients. 796 * 797 * This value should depend on external power adapter, designed charging 798 * voltage, and the maximum power of the running system. For type-C chargers, 799 * this should be set to 512 mA in order to not brown-out low-current USB 800 * charge ports in accordance with USB-PD r3.0 Sec. 7.3 801 */ 802 #undef CONFIG_CHARGER_INPUT_CURRENT 803 804 /* 805 * This config option is used to enable IDCHG trigger for prochot. This macro 806 * should be set to the desired current limit to draw from the battery before 807 * triggering prochot. Note that is has a 512 mA granularity. The function that 808 * sets the limit will mask of the lower 10 bits. For this check to be active 809 * the bq25710 must be in performance mode and this config option is also used 810 * to keep the bq25710 in performance mode when the AP is in S0. 811 */ 812 #undef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 813 814 /* 815 * Board specific maximum input current limit, in mA. 816 */ 817 #undef CONFIG_CHARGER_MAX_INPUT_CURRENT 818 819 /* 820 * Leave charger VBAT configured to battery-requested voltage under all 821 * conditions, even when AC is not present. This may be necessary to work 822 * around quirks of certain charger chips, such as the BD9995X. 823 */ 824 #undef CONFIG_CHARGER_MAINTAIN_VBAT 825 826 /* 827 * Power thresholds for AP boot 828 * 829 * If one of the following conditions is met, EC boots AP: 830 * 831 * 1. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 832 * 2. AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 833 * 3. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 834 * and 835 * AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 836 * 837 * Note that CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT/_CHG_MW are thresholds 838 * for the OS boot used by Depthcharge. The OS has higher power requirement 839 * but PD power is also available. 840 * 841 * WARNING: Locked RO firmware does not negotiate power greater than 15W via 842 * analog signaling. If the AP requires greater than 15W to boot, then see 843 * CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW. 844 */ 845 #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 846 #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 847 /* Default: 15000 */ 848 #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 849 /* Default: Disabled */ 850 #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 851 852 /* Minimum battery percentage for power on with an imbalanced pack */ 853 #undef CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON 854 855 /* 856 * Maximum battery cell imbalance to accept before considering the pack to be 857 * imbalanced, in millivolts. 858 */ 859 #undef CONFIG_BATTERY_MAX_IMBALANCE_MV 860 861 /* Set this option when using a Narrow VDC (NVDC) charger, such as ISL9237/8. */ 862 #undef CONFIG_CHARGER_NARROW_VDC 863 864 /* 865 * Low energy thresholds - when battery level is below BAT_PCT and an external 866 * charger provides less than CHG_MW of power, inform the AP of the situation 867 * through the LIMIT_POWER charge state parameter. Depthcharge will hold off on 868 * the boot for up to 3 seconds while waiting for either condition to clear 869 * before starting the kernel. This wait happens after sw sync in RW mode, so 870 * the firmware may set it high enough that PD negotiation is required to clear 871 * it. 872 * 873 * Default: Disabled. Depthcharge is immediately released to boot the kernel. 874 * 875 * Setting this value to 15001 will require PD negotiation to be complete prior 876 * to releasing depthcharge. During PD negotiation, the charger will be briefly 877 * reduced to about 2.5W for a few hundred ms. 878 */ 879 #undef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 880 /* Default: CHARGER_MIN_BAT_PCT_FOR_POWER_ON */ 881 #undef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 882 883 /* 884 * Enable charger's OTG functions, i.e. make it possible to supply output power 885 * from battery. 886 */ 887 #undef CONFIG_CHARGER_OTG 888 889 /* 890 * Charger should call battery_override_params() to limit/correct the voltage 891 * and current requested by the battery pack before acting on the request. 892 */ 893 #undef CONFIG_CHARGER_PROFILE_OVERRIDE 894 895 /* 896 * Common code for charger profile override. Should be used with 897 * CONFIG_CHARGER_PROFILE_OVERRIDE. 898 */ 899 #undef CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON 900 901 /* 902 * Battery voltage threshold ranges for charge profile override. 903 * Override it in board.h if battery has multiple threshold ranges. 904 */ 905 #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 2 906 907 /* Value of the charge sense resistor, in mOhms */ 908 #undef CONFIG_CHARGER_SENSE_RESISTOR 909 910 /* Value of the input current sense resistor, in mOhms */ 911 #undef CONFIG_CHARGER_SENSE_RESISTOR_AC 912 913 /* 914 * Board has an GPIO pin to enable or disable charging. 915 * 916 * This GPIO should be named GPIO_CHARGER_EN, if active high. Or 917 * GPIO_CHARGER_EN_L if active low. 918 */ 919 #undef CONFIG_CHARGER_EN_GPIO 920 921 /* Charger enable GPIO is active low */ 922 #undef CONFIG_CHARGER_EN_ACTIVE_LOW 923 924 /* Enable trickle charging */ 925 #undef CONFIG_TRICKLE_CHARGING 926 927 /* Wireless chargers */ 928 #undef CONFIG_WIRELESS_CHARGER_P9221_R7 929 930 /*****************************************************************************/ 931 932 /* 933 * Chip needs to do pre-init very early in main(), and provides chip_pre_init() 934 * to do so. 935 */ 936 #undef CONFIG_CHIP_PRE_INIT 937 938 /*****************************************************************************/ 939 /* Chipset config */ 940 941 /* AP chipset support; pick at most one */ 942 #undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */ 943 #undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */ 944 #undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */ 945 #undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */ 946 #undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), \ 947 * discrete EC control \ 948 */ 949 #undef CONFIG_CHIPSET_ECDRIVEN /* Placeholder power module */ 950 #undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */ 951 #undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */ 952 #undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */ 953 #undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */ 954 #undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */ 955 #undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */ 956 #undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ 957 #undef CONFIG_CHIPSET_SC7180 /* Qualcomm SC7180 */ 958 #undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */ 959 #undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/ 960 #undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */ 961 962 /* Shared chipset support; automatically gets defined below. */ 963 #undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */ 964 #undef CONFIG_CHIPSET_ICL_TGL /* Icelake & Tigerlake */ 965 966 /* Support chipset throttling */ 967 #undef CONFIG_CHIPSET_CAN_THROTTLE 968 969 /* Enable additional chipset debugging */ 970 #undef CONFIG_CHIPSET_DEBUG 971 972 /* Enable chipset reset hook, requires a deferrable function */ 973 #undef CONFIG_CHIPSET_RESET_HOOK 974 975 /* 976 * Enable turning on PP3300_A rail before PP5000_A rail on the Ice Lake 977 * and Tiger Lake chipsets. Enable this option if there is leakage from PP5000_A 978 * resources into PP3300_A resources. 979 */ 980 #undef CONFIG_CHIPSET_PP3300_RAIL_FIRST 981 982 /* 983 * Enable if chipset requires delay between power signals going high 984 * and deasserting RSMRST to PCH. 985 */ 986 #undef CONFIG_CHIPSET_X86_RSMRST_DELAY 987 988 /* Support PMIC reset(using LDO_EN) in chipset */ 989 #undef CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET 990 991 /* Board requires chipset pre-init callback */ 992 #undef CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK 993 994 /* Redefine when we need a different power-on sequence on the same chipset. */ 995 #define CONFIG_CHIPSET_POWER_SEQ_VERSION 0 996 997 /*****************************************************************************/ 998 /* 999 * Chip config for clock circuitry 1000 * define = crystal / undef = oscillator 1001 */ 1002 #undef CONFIG_CLOCK_CRYSTAL 1003 1004 /* 1005 * Indicate if a clock source is connected to stm32f4's high speed external 1006 * clock signal (HSE) specific input 1007 */ 1008 #undef CONFIG_STM32_CLOCK_HSE_HZ 1009 1010 /* 1011 * Indicate if a clock source is connected to low speed external (LSE) specific 1012 * input 1013 */ 1014 #undef CONFIG_STM32_CLOCK_LSE 1015 1016 /* 1017 * Chip config for clock source 1018 * define = external crystal oscillator / undef = internal clock source 1019 */ 1020 #undef CONFIG_CLOCK_SRC_EXTERNAL 1021 1022 /*****************************************************************************/ 1023 /* Support curve25519 public key cryptography */ 1024 #undef CONFIG_CURVE25519 1025 1026 /*****************************************************************************/ 1027 /* PMIC config */ 1028 1029 /* Support firmware long press power-off timer */ 1030 #undef CONFIG_PMIC_FW_LONG_PRESS_TIMER 1031 1032 /* Support PMIC power control */ 1033 #undef CONFIG_PMIC 1034 1035 /*****************************************************************************/ 1036 /* 1037 * Optional console commands 1038 * 1039 * Defining these options will enable the corresponding command on the EC 1040 * console. 1041 */ 1042 1043 #undef CONFIG_CMD_ACCELS 1044 #undef CONFIG_CMD_ACCEL_FIFO 1045 #undef CONFIG_CMD_ACCEL_INFO 1046 #define CONFIG_CMD_ACCELSPOOF 1047 #define CONFIG_CMD_ADC 1048 #undef CONFIG_CMD_ALS 1049 #define CONFIG_CMD_APTHROTTLE 1050 #undef CONFIG_CMD_BATDEBUG 1051 #define CONFIG_CMD_BATTFAKE 1052 #undef CONFIG_CMD_BATT_MFG_ACCESS 1053 #define CONFIG_CMD_RETIMER 1054 #undef CONFIG_CMD_BUTTON 1055 #define CONFIG_CMD_CBI 1056 #undef CONFIG_CMD_CCD_DISABLE /* 'ccd disable' subcommand */ 1057 #undef CONFIG_CMD_CHARGEN 1058 #define CONFIG_CMD_CHARGER 1059 #undef CONFIG_CMD_CHARGER_ADC_AMON_BMON 1060 #undef CONFIG_CMD_CHARGER_DUMP 1061 #undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE 1062 #undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST 1063 #define CONFIG_CMD_CHARGE_SUPPLIER_INFO 1064 #undef CONFIG_CMD_CHGRAMP 1065 #undef CONFIG_CMD_CLOCKGATES 1066 #undef CONFIG_CMD_COMXTEST 1067 #define CONFIG_CMD_CRASH 1068 #define CONFIG_CMD_DEVICE_EVENT 1069 #undef CONFIG_CMD_DLOG 1070 #define CONFIG_CMD_DUMP_NVMEM 1071 #define CONFIG_CMD_ECRST 1072 #undef CONFIG_CMD_ECTEMP 1073 #define CONFIG_CMD_FASTCHARGE 1074 #undef CONFIG_CMD_FLASH 1075 #define CONFIG_CMD_FLASHINFO 1076 #undef CONFIG_CMD_FLASH_LOG 1077 #undef CONFIG_CMD_FLASH_TRISTATE 1078 #undef CONFIG_CMD_FORCETIME 1079 #undef CONFIG_CMD_GPIO_EXTENDED 1080 #define CONFIG_CMD_GPIOCFG 1081 #undef CONFIG_CMD_GSV 1082 #undef CONFIG_CMD_GT7288 1083 #define CONFIG_CMD_HASH 1084 #define CONFIG_CMD_HCDEBUG 1085 #undef CONFIG_CMD_HOSTCMD 1086 #undef CONFIG_CMD_I2CWEDGE 1087 #undef CONFIG_CMD_I2C_PROTECT 1088 #define CONFIG_CMD_I2C_SCAN 1089 #undef CONFIG_CMD_I2C_STRESS_TEST 1090 #undef CONFIG_CMD_I2C_STRESS_TEST_ACCEL 1091 #undef CONFIG_CMD_I2C_STRESS_TEST_ALS 1092 #undef CONFIG_CMD_I2C_STRESS_TEST_BATTERY 1093 #undef CONFIG_CMD_I2C_STRESS_TEST_CHARGER 1094 #undef CONFIG_CMD_I2C_STRESS_TEST_TCPC 1095 #define CONFIG_CMD_I2C_XFER 1096 #define CONFIG_CMD_IDLE_STATS 1097 #undef CONFIG_CMD_ILIM 1098 #define CONFIG_CMD_INA 1099 #undef CONFIG_CMD_JUMPTAGS 1100 #define CONFIG_CMD_KEYBOARD 1101 #undef CONFIG_CMD_LEDTEST 1102 #undef CONFIG_CMD_LID_ANGLE 1103 #undef CONFIG_CMD_MCDP 1104 #define CONFIG_CMD_MD 1105 #define CONFIG_CMD_MEM 1106 #define CONFIG_CMD_MMAPINFO 1107 #define CONFIG_CMD_PD 1108 #undef CONFIG_CMD_PD_CONTROL 1109 #undef CONFIG_CMD_PD_DEV_DUMP_INFO 1110 #undef CONFIG_CMD_PD_FLASH 1111 #define CONFIG_CMD_PECI 1112 #define CONFIG_CMD_PINMUX 1113 #undef CONFIG_CMD_PLL 1114 #undef CONFIG_CMD_PMU 1115 #define CONFIG_CMD_POWERINDEBUG 1116 #undef CONFIG_CMD_POWERLED 1117 #define CONFIG_CMD_PWR_AVG 1118 #define CONFIG_CMD_POWER_AP 1119 #undef CONFIG_CMD_PPC_DUMP 1120 #undef CONFIG_CMD_RAND 1121 #define CONFIG_CMD_REGULATOR 1122 #undef CONFIG_CMD_ROLLBACK 1123 #undef CONFIG_CMD_RTC 1124 #undef CONFIG_CMD_RTC_ALARM 1125 #define CONFIG_CMD_RW 1126 #undef CONFIG_CMD_SCRATCHPAD 1127 #undef CONFIG_CMD_SEVEN_SEG_DISPLAY 1128 #define CONFIG_CMD_SHMEM 1129 #undef CONFIG_CMD_SLEEP 1130 #define CONFIG_CMD_SLEEPMASK 1131 #define CONFIG_CMD_SLEEPMASK_SET 1132 #undef CONFIG_CMD_SPI_FLASH 1133 #undef CONFIG_CMD_SPI_NOR 1134 #undef CONFIG_CMD_SPI_XFER 1135 #undef CONFIG_CMD_STACKOVERFLOW 1136 #define CONFIG_CMD_SYSINFO 1137 #define CONFIG_CMD_SYSJUMP 1138 #define CONFIG_CMD_SYSLOCK 1139 #define CONFIG_CMD_SYSRST 1140 #undef CONFIG_CMD_TASKREADY 1141 #define CONFIG_CMD_TEMP_SENSOR 1142 #define CONFIG_CMD_TIMERINFO 1143 #define CONFIG_CMD_TYPEC 1144 #undef CONFIG_CMD_USART_INFO 1145 #define CONFIG_CMD_USBMUX 1146 #undef CONFIG_CMD_USB_PD_CABLE 1147 #undef CONFIG_CMD_USB_PD_PE 1148 #define CONFIG_CMD_WAITMS 1149 #define CONFIG_CMD_WP 1150 #undef CONFIG_CMD_AP_RESET_LOG 1151 1152 /*****************************************************************************/ 1153 1154 /* Provide common core code to output panic information without interrupts. */ 1155 #define CONFIG_COMMON_PANIC_OUTPUT 1156 1157 /* 1158 * Store a panic log and halt the system for a software-related reasons, such as 1159 * stack overflow or assertion failure. 1160 */ 1161 #undef CONFIG_SOFTWARE_PANIC 1162 1163 /* 1164 * Certain platforms(e.g. eve, poppy) cannot retain panic info in data ram since 1165 * VCC is powered down on EC reset. On such platforms, panic data needs to be 1166 * saved/restored to persistent storage by using chip specific 1167 * implementations. This option can be enabled by those platforms that have and 1168 * wish to use chip-implemented panic backup/restore functions. 1169 */ 1170 #undef CONFIG_CHIP_PANIC_BACKUP 1171 1172 /* 1173 * Provide the default GPIO abstraction layer. 1174 * You want this unless you are doing a really tiny firmware. 1175 */ 1176 #define CONFIG_COMMON_GPIO 1177 1178 /* 1179 * Provides smaller GPIO names to reduce flash size. Instead of the 'name' 1180 * field in GPIO macro it will concat 'port' and 'pin' to reduce flash size. 1181 */ 1182 #undef CONFIG_COMMON_GPIO_SHORTNAMES 1183 1184 /* 1185 * Provide common runtime layer code (tasks, hooks ...) 1186 * You want this unless you are doing a really tiny firmware. 1187 */ 1188 #define CONFIG_COMMON_RUNTIME 1189 1190 /* Provide common core code to handle the operating system timers. */ 1191 #define CONFIG_COMMON_TIMER 1192 1193 /*****************************************************************************/ 1194 1195 /* 1196 * Provide additional help on console commands, such as the supported 1197 * options/usage. 1198 * 1199 * Boards may #undef this to reduce image size. 1200 */ 1201 #define CONFIG_CONSOLE_CMDHELP 1202 1203 /* 1204 * Add a .flags field to the console commands data structure, to distinguish 1205 * some commands from others. The available flags bits are defined in 1206 * include/console.h 1207 */ 1208 #undef CONFIG_CONSOLE_COMMAND_FLAGS 1209 1210 /* 1211 * One use of the .flags field is to make some console commands restricted, so 1212 * that they can be disabled or enabled at run time. 1213 */ 1214 #undef CONFIG_RESTRICTED_CONSOLE_COMMANDS 1215 1216 /* The default .flags field value is zero, unless overridden with this. */ 1217 #undef CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT 1218 1219 /* 1220 * Enable EC_CMD_CONSOLE_READ V1. One could disable this config to prevent 1221 * kernel from creating the `console_log` debugfs entry. 1222 */ 1223 #define CONFIG_CONSOLE_ENABLE_READ_V1 1224 1225 /* 1226 * Number of entries in console history buffer. 1227 * 1228 * Boards may #undef this to reduce memory usage. 1229 */ 1230 #define CONFIG_CONSOLE_HISTORY 8 1231 1232 /* Max length of a single line of input */ 1233 #define CONFIG_CONSOLE_INPUT_LINE_SIZE 80 1234 1235 /* Enable verbose output to UART console and extra timestamp print precision. */ 1236 #define CONFIG_CONSOLE_VERBOSE 1237 1238 /* Trigger building the image with all format strings extracted. */ 1239 #undef CONFIG_EXTRACT_PRINTF_STRINGS 1240 1241 /* Include AP RO verification support. */ 1242 #undef CONFIG_AP_RO_VERIFICATION 1243 1244 /* 1245 * Enable EC-CR50 communication (a.k.a. EC-EFS2). This is for CR50 config only. 1246 */ 1247 #undef CONFIG_EC_EFS_SUPPORT 1248 1249 /* 1250 * Version of EC-EFS: 0 (for 2.0) or 1 (for 2.1). 1251 * This is for CR50 config only 1252 */ 1253 #undef CONFIG_EC_EFS2_VERSION 1254 1255 /* 1256 * Enable the experimental console. 1257 * 1258 * NOTE: If you enable this experimental console, you will need to run the 1259 * EC-3PO interactive console in the util directory! Otherwise, you won't be 1260 * able to enter any commands. 1261 */ 1262 #undef CONFIG_EXPERIMENTAL_CONSOLE 1263 1264 /* Include CRC-8 utility function */ 1265 #undef CONFIG_CRC8 1266 1267 /* 1268 * When enabled, do not build RO image from the same set of files as the RW 1269 * image. Instead define a separate set of object files in the respective 1270 * build.mk files by adding the objects to the custom-ro_objs-y variable. 1271 */ 1272 #undef CONFIG_CUSTOMIZED_RO 1273 1274 /* 1275 * When enabled, build in support for software & hardware crypto; 1276 * only supported on CR50. 1277 * 1278 * If this is enabled on the host board, a minimal implementation is included to 1279 * allow fuzzing targets to fuzz code that depends on dcrypto. 1280 */ 1281 #undef CONFIG_DCRYPTO 1282 /* 1283 * Use dcrypto in the board directory instead of chip/g. 1284 */ 1285 #undef CONFIG_DCRYPTO_BOARD 1286 /* Build FIPS utils in the module */ 1287 #undef CONFIG_FIPS_UTIL 1288 /* Inject the fips checksum into the image. */ 1289 #undef CONFIG_FIPS_CHECKSUM 1290 /* 1291 * This provides struct definitions and function declarations that can be 1292 * implemented by unit tests for testing code that depends on dcrypto. 1293 * This should not be set at the same time as CONFIG_DCRYPTO. 1294 */ 1295 #undef CONFIG_DCRYPTO_MOCK 1296 1297 /* 1298 * When enabled, RSA 2048 bit keygen gets a 40% performance boost, 1299 * at the cost of 2184 bytes of image size increase. 1300 */ 1301 #undef CONFIG_DCRYPTO_RSA_SPEEDUP 1302 1303 /* 1304 * When enabled, accelerate sha512/384 using the generic crypto engine; 1305 * only supported on CR50. It is about 4x faster, but ~620 bytes larger. 1306 */ 1307 #undef CONFIG_DCRYPTO_SHA512 1308 1309 /* 1310 * When enabled build support for SHA-384/512, requires CONFIG_DCRYPTO or 1311 * CONFIG_DCRYPTO_BOARD. 1312 */ 1313 #undef CONFIG_UPTO_SHA512 1314 1315 /** 1316 * Make sw version of SHA2-512/384 equal to hw(dcrypto). 1317 * Unlike SHA2-256, dcrypto implementation of SHA2-512/384 allows to save 1318 * context, so can fully replace software implementation. 1319 */ 1320 #undef CONFIG_SHA512_HW_EQ_SW 1321 1322 /* 1323 * When enabled ignore version et al during fw upgrade for chip/g. 1324 */ 1325 #undef CONFIG_IGNORE_G_UPDATE_CHECKS 1326 1327 /* 1328 * When enabled hardware alerts statistics provided via VendorCommand extension. 1329 */ 1330 #undef CONFIG_ENABLE_H1_ALERTS 1331 1332 /* 1333 * Enable console shell command 'alerts' that prints chip alerts statistics. 1334 */ 1335 #undef CONFIG_ENABLE_H1_ALERTS_CONSOLE 1336 1337 /*****************************************************************************/ 1338 /* 1339 * Debugging config 1340 * 1341 * Note that these options are enabled by default, because they're really 1342 * handy for debugging systems during bringup and even at factory time. 1343 * 1344 * A board may undefine any or all of these to reduce image size and RAM usage, 1345 * at the cost of debuggability. 1346 */ 1347 1348 /* 1349 * ASSERT() macros are checked at runtime. See CONFIG_DEBUG_ASSERT_REBOOTS 1350 * to see what happens if one fails. 1351 * 1352 * Boards may #undef this to reduce image size. 1353 */ 1354 #define CONFIG_DEBUG_ASSERT 1355 1356 /* 1357 * Prints a message and reboots if an ASSERT() macro fails at runtime. When 1358 * enabled, an ASSERT() which fails will produce a message of the form: 1359 * 1360 * ASSERTION FAILURE '<expr>' in function() at file:line 1361 * 1362 * If this is not defined, failing ASSERT() will trigger a BKPT instruction 1363 * instead. 1364 * 1365 * Ignored if CONFIG_DEBUG_ASSERT is not defined. 1366 * 1367 * Boards may #undef this to reduce image size. 1368 */ 1369 #define CONFIG_DEBUG_ASSERT_REBOOTS 1370 1371 /* 1372 * On assertion failure, prints only the file name and the line number. 1373 * 1374 * Ignored if CONFIG_DEBUG_ASSERT_REBOOTS is not defined. 1375 * 1376 * Boards may define this to reduce image size. 1377 */ 1378 #undef CONFIG_DEBUG_ASSERT_BRIEF 1379 1380 /* 1381 * Disable the write buffer used for default memory map accesses. 1382 * This turns "Imprecise data bus errors" into "Precise" errors 1383 * in exception traces at the cost of some performance. 1384 * This may help identify the offending instruction causing an 1385 * exception. Supported on cortex-m. 1386 */ 1387 #undef CONFIG_DEBUG_DISABLE_WRITE_BUFFER 1388 1389 /* 1390 * Print additional information when exceptions are triggered, such as the 1391 * fault address, here shown as bfar. This shows the reason for the fault 1392 * and may help to determine the cause. 1393 * 1394 * === EXCEPTION: 03 ====== xPSR: 01000000 =========== 1395 * r0 :0000000b r1 :00000047 r2 :60000000 r3 :200013dd 1396 * r4 :00000000 r5 :080053f4 r6 :200013d0 r7 :00000002 1397 * r8 :00000000 r9 :200013de r10:00000000 r11:00000000 1398 * r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a 1399 * Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000 1400 * mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 1401 * 1402 * If this is not defined, only a register dump will be printed. 1403 * 1404 * Boards may #undef this to reduce image size. 1405 */ 1406 #define CONFIG_DEBUG_EXCEPTIONS 1407 1408 /* 1409 * Print orientation when device orientation changes 1410 * (requires CONFIG_SENSOR_ORIENTATION) 1411 */ 1412 #undef CONFIG_DEBUG_ORIENTATION 1413 1414 /* Support Synchronous UART debug printf. */ 1415 #undef CONFIG_DEBUG_PRINTF 1416 1417 /* Check for stack overflows on every context switch */ 1418 #define CONFIG_DEBUG_STACK_OVERFLOW 1419 1420 /*****************************************************************************/ 1421 1422 /* Support events from devices attached to the EC */ 1423 #undef CONFIG_DEVICE_EVENT 1424 1425 /* Monitor the states of other devices */ 1426 #undef CONFIG_DEVICE_STATE 1427 1428 /* Support DMA transfers inside the EC */ 1429 #undef CONFIG_DMA 1430 1431 /* Use the common interrupt handlers for DMA IRQs */ 1432 #define CONFIG_DMA_DEFAULT_HANDLERS 1433 1434 /* Compile extra debugging and tests for the DMA module */ 1435 #undef CONFIG_DMA_HELP 1436 1437 /* Usually, EC capable of sensor speeds up to 200000 mHz */ 1438 #define CONFIG_EC_MAX_SENSOR_FREQ_DEFAULT_MILLIHZ 200000 1439 1440 /* Support EC chip internal data EEPROM */ 1441 #undef CONFIG_EEPROM 1442 1443 /* Include code for handling external power */ 1444 #define CONFIG_EXTPOWER 1445 1446 /* Support detecting external power presence via a GPIO */ 1447 #undef CONFIG_EXTPOWER_GPIO 1448 1449 /* Default debounce time for external power signal */ 1450 #define CONFIG_EXTPOWER_DEBOUNCE_MS 30 1451 1452 /* Add support for CCD factory mode */ 1453 #undef CONFIG_FACTORY_MODE 1454 1455 /*****************************************************************************/ 1456 /* Number of cooling fans. Undef if none. */ 1457 #undef CONFIG_FANS 1458 1459 /* Percentage to which all fans are set at initiation */ 1460 #define CONFIG_FAN_INIT_SPEED 100 1461 1462 /* Support fan control while in low-power idle */ 1463 #undef CONFIG_FAN_DSLEEP 1464 1465 /* 1466 * Fans have non-const configuration. 1467 */ 1468 #undef CONFIG_FAN_DYNAMIC 1469 1470 /* 1471 * Replace the default fan_percent_to_rpm() function with a board-specific 1472 * implementation in board.c 1473 */ 1474 #undef CONFIG_FAN_RPM_CUSTOM 1475 1476 /* 1477 * We normally check and update the fans once per second (HOOK_SECOND). If this 1478 * is #defined to a postive integer N, we will only update the fans every N 1479 * seconds instead. 1480 */ 1481 #undef CONFIG_FAN_UPDATE_PERIOD 1482 1483 /*****************************************************************************/ 1484 /* Flash configuration */ 1485 1486 /* This enables console commands and higher-level features */ 1487 #define CONFIG_FLASH 1488 /* This enables chip-specific access functions */ 1489 #define CONFIG_FLASH_PHYSICAL 1490 #undef CONFIG_FLASH_BANK_SIZE 1491 /* Provide event log stored in flash memory. */ 1492 #undef CONFIG_FLASH_LOG 1493 #undef CONFIG_FLASH_LOG_BASE 1494 #undef CONFIG_FLASH_LOG_SPACE 1495 #undef CONFIG_FLASH_ERASED_VALUE32 1496 #undef CONFIG_FLASH_ERASE_SIZE 1497 #undef CONFIG_FLASH_ROW_SIZE 1498 /* Allow deferred (async) flash erase */ 1499 #undef CONFIG_FLASH_DEFERRED_ERASE 1500 /* Flash must be selected for write/erase operations to succeed. */ 1501 #undef CONFIG_FLASH_SELECT_REQUIRED 1502 1503 /* Base address of program memory */ 1504 #undef CONFIG_PROGRAM_MEMORY_BASE 1505 1506 /* 1507 * EC code can reside on internal or external storage. Only one of these 1508 * CONFIGs should be defined. CONFIG_INTERNAL_STORAGE implies XIP 1509 * (eXecute-In-Place) semantics. i.e. code is being fetched directly from 1510 * storage media. 1511 */ 1512 #undef CONFIG_EXTERNAL_STORAGE 1513 #undef CONFIG_INTERNAL_STORAGE 1514 1515 /* 1516 * Flash is directly mapped into the EC's address space. If this is not 1517 * defined, the flash driver must implement flash_physical_read(). 1518 */ 1519 #define CONFIG_MAPPED_STORAGE 1520 1521 /* 1522 * Base address of memory-mapped flash storage, for platforms which define 1523 * CONFIG_MAPPED_STORAGE. 1524 */ 1525 #undef CONFIG_MAPPED_STORAGE_BASE 1526 1527 #undef CONFIG_FLASH_PROTECT_NEXT_BOOT 1528 1529 /* 1530 * Some platforms need to write protect RW independently of all flash. 1531 */ 1532 #undef CONFIG_FLASH_PROTECT_RW 1533 1534 /* 1535 * Store persistent write protect for the flash inside the flash data itself. 1536 * This allows ECs with internal flash to emulate something closer to a SPI 1537 * flash write protect register. If this is not defined, write protect state 1538 * is maintained solely by the physical flash driver. 1539 */ 1540 #define CONFIG_FLASH_PSTATE 1541 1542 /* 1543 * Store the pstate data in its own dedicated bank of flash. This allows 1544 * disabling the protect-RO-at-boot flag without rewriting the RO firmware, 1545 * but costs a bank of flash. 1546 * 1547 * If this is not defined, the pstate data is stored inside the RO firmware 1548 * image itself. This is more space-efficient, but the only way to clear the 1549 * flag once it's set is to rewrite the RO firmware (after removing the WP 1550 * screw, of course). 1551 */ 1552 #define CONFIG_FLASH_PSTATE_BANK 1553 1554 /* 1555 * Lock the PSTATE by default (currently only supported when 1556 * CONFIG_FLASH_PSTATE_BANK is not defined). 1557 */ 1558 #undef CONFIG_FLASH_PSTATE_LOCKED 1559 1560 /* 1561 * Enable readout protection. 1562 */ 1563 #undef CONFIG_FLASH_READOUT_PROTECTION 1564 1565 /* 1566 * Use Read-out protection status as PSTATE, i.e. after RDP is enabled, we never 1567 * allow RO protection to be disabled. 1568 * 1569 * This is used when we want to prevent read-back of some critical region (e.g. 1570 * rollback), even in DFU/BOOT0 mode. 1571 * 1572 * Note that this significantly changes the behaviour or flash protection, 1573 * as this tie EC_FLASH_PROTECT_RO_AT_BOOT with RDP status: it makes no 1574 * sense to be able to unlock RO protection if RDP is enabled, as a custom RO 1575 * could allow protected regions readback. 1576 * 1577 * TODO(crbug.com/888109): Implementation is currently only available on 1578 * STM32H7 and STM32F4, and requires more documentation. 1579 */ 1580 #undef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE 1581 1582 /* 1583 * For flash that is segemented in different regions. 1584 */ 1585 #undef CONFIG_FLASH_MULTIPLE_REGION 1586 /* Number of regions of different size/type */ 1587 #undef CONFIG_FLASH_REGION_TYPE_COUNT 1588 1589 /* Total size of writable flash */ 1590 #undef CONFIG_FLASH_SIZE 1591 1592 /* Minimum flash write size (in bytes) */ 1593 #undef CONFIG_FLASH_WRITE_SIZE 1594 /* Most efficient flash write size (in bytes) */ 1595 #undef CONFIG_FLASH_WRITE_IDEAL_SIZE 1596 1597 /* Protected region of storage belonging to EC */ 1598 #undef CONFIG_EC_PROTECTED_STORAGE_OFF 1599 #undef CONFIG_EC_PROTECTED_STORAGE_SIZE 1600 1601 /* Writable region of storage belonging to EC */ 1602 #undef CONFIG_EC_WRITABLE_STORAGE_OFF 1603 #undef CONFIG_EC_WRITABLE_STORAGE_SIZE 1604 1605 /*****************************************************************************/ 1606 /* NvMem Configuration */ 1607 /* Enable NV Memory module within flash */ 1608 #undef CONFIG_FLASH_NVMEM 1609 /* Offset to start of NvMem area from base of flash */ 1610 #undef CONFIG_FLASH_NVMEM_OFFSET_A 1611 #undef CONFIG_FLASH_NVMEM_OFFSET_B 1612 /* Address of start of Nvmem area */ 1613 #undef CONFIG_FLASH_NVMEM_BASE_A 1614 #undef CONFIG_FLASH_NVMEM_BASE_B 1615 1616 /* Flash offsets for the 'new' (as of 1/2019) nvmem storage scheme. */ 1617 #undef CONFIG_FLASH_NEW_NVMEM_BASE_A 1618 #undef CONFIG_FLASH_NEW_NVMEM_BASE_B 1619 1620 /* Size in bytes of NvMem area */ 1621 #undef CONFIG_FLASH_NVMEM_SIZE 1622 1623 /* Enable <key,value> variable support (requires CONFIG_FLASH_NVMEM) */ 1624 #undef CONFIG_FLASH_NVMEM_VARS 1625 /* 1626 * We already have to define nvmem_user_sizes[] to specify the order and size 1627 * of the user regions. CONFIG_FLASH_NVMEM_VARS looks for two symbols to 1628 * specify the region number and size for the variable region. 1629 */ 1630 #undef CONFIG_FLASH_NVMEM_VARS_USER_NUM 1631 #undef CONFIG_FLASH_NVMEM_VARS_USER_SIZE 1632 1633 /*****************************************************************************/ 1634 1635 /* Include a flashmap in the compiled firmware image */ 1636 #define CONFIG_FMAP 1637 1638 /* Allow EC serial console input to wake up the EC from STOP mode */ 1639 #undef CONFIG_FORCE_CONSOLE_RESUME 1640 1641 /* Enable support for floating point unit */ 1642 #undef CONFIG_FPU 1643 1644 /*****************************************************************************/ 1645 /* Firmware region configuration */ 1646 1647 #undef CONFIG_FW_PSTATE_OFF 1648 #undef CONFIG_FW_PSTATE_SIZE 1649 1650 /* 1651 * Read-only / read-write image configuration. 1652 * Images may reside on storage (ex. external or internal SPI) at a different 1653 * offset than when copied to program memory. Hence, two sets of offsets, 1654 * for STORAGE and for MEMORY. 1655 */ 1656 #undef CONFIG_RO_MEM_OFF 1657 /* Offset relative to CONFIG_EC_PROTECTED_STORAGE_OFF */ 1658 #undef CONFIG_RO_STORAGE_OFF 1659 #undef CONFIG_RO_SIZE 1660 1661 #undef CONFIG_RW_MEM_OFF 1662 /* Some targets include two RW sections in the image. */ 1663 #undef CONFIG_RW_B 1664 /* This is the offset of the second RW section into the flash. */ 1665 #undef CONFIG_RW_B_MEM_OFF 1666 1667 /* Offset relative to CONFIG_EC_WRITABLE_STORAGE_OFF */ 1668 #undef CONFIG_RW_STORAGE_OFF 1669 #undef CONFIG_RW_SIZE 1670 1671 /* 1672 * NPCX-specific bootheader geometry. 1673 * TODO(crosbug.com/p/23796): Factor these CONFIGs out. 1674 */ 1675 #undef CONFIG_RO_HDR_MEM_OFF 1676 #undef CONFIG_RO_HDR_SIZE 1677 1678 /* 1679 * Write protect region offset / size. This region normally encompasses the 1680 * RO image, but may also contain additional images or data. 1681 */ 1682 #undef CONFIG_WP_STORAGE_OFF 1683 #undef CONFIG_WP_STORAGE_SIZE 1684 1685 /* 1686 * Rollback protect region. If CONFIG_ROLLBACK is defined to enable the rollback 1687 * protect region, CONFIG_ROLLBACK_OFF and CONFIG_ROLLBACK_SIZE must be defined 1688 * too. 1689 */ 1690 #undef CONFIG_ROLLBACK 1691 #undef CONFIG_ROLLBACK_OFF 1692 #undef CONFIG_ROLLBACK_SIZE 1693 1694 /* If defined, add support for storing some entropy in the rollback region. */ 1695 #undef CONFIG_ROLLBACK_SECRET_SIZE 1696 1697 /* If defined, protect rollback region readback using MPU. */ 1698 #undef CONFIG_ROLLBACK_MPU_PROTECT 1699 1700 /* 1701 * If defined, inject some locally generated entropy when secret is updated, 1702 * using board_get_entropy function. 1703 * Large values may take a long time to generate. 1704 * 1705 * This is only meant to add a little bit of extra entropy, when the hardware 1706 * lacks a random number generator (otherwise, the strong entropy can be 1707 * directly added to the secret, using rollback_add_entropy). 1708 */ 1709 #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE 1710 1711 /* If defined, we can update rollback information (RW can unset this). */ 1712 #define CONFIG_ROLLBACK_UPDATE 1713 1714 /* 1715 * Current rollback version. Meaningless for RO (but provides the minimum value 1716 * that will be written to the rollback protection at flash time). 1717 * 1718 * For RW, rollback version included in version structure, used by RO to 1719 * determine if the RW image is recent enough and can be jumped to. 1720 * 1721 * Valid values are >= 0, <= INT32_MAX (positive, 32-bit signed integer). 1722 */ 1723 #define CONFIG_ROLLBACK_VERSION 0 1724 1725 /* 1726 * Board Image ec.bin contains a RO firmware. If not defined, the image will 1727 * only contain the RW firmware. 1728 */ 1729 #define CONFIG_FW_INCLUDE_RO 1730 1731 /* If defined, another image (RW) exists with more features */ 1732 #undef CONFIG_FW_LIMITED_IMAGE 1733 1734 /* 1735 * If defined, we can use system_get_fw_reset_vector function to decide 1736 * reset vector of RO/RW firmware for sysjump. 1737 */ 1738 #undef CONFIG_FW_RESET_VECTOR 1739 1740 /*****************************************************************************/ 1741 /* Motion sensor based gesture recognition information */ 1742 /* These all require HAS_TASK_MOTIONSENSE to work */ 1743 1744 /* Do we want to detect gestures? */ 1745 #undef CONFIG_GESTURE_DETECTION 1746 1747 /* Mask of all sensors used for gesture dectections */ 1748 #undef CONFIG_GESTURE_DETECTION_MASK 1749 1750 /* some gesture recognition done in software */ 1751 #undef CONFIG_GESTURE_SW_DETECTION 1752 1753 /* enable gesture host interface */ 1754 #undef CONFIG_GESTURE_HOST_DETECTION 1755 1756 /* Sensor sampling interval for gesture recognition */ 1757 #undef CONFIG_GESTURE_SAMPLING_INTERVAL_MS 1758 1759 /* Which sensor to look for double tap recognition */ 1760 #undef CONFIG_GESTURE_SENSOR_DOUBLE_TAP 1761 1762 /* Use for waking up host */ 1763 #undef CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST 1764 1765 /* 1766 * Double tap detection parameters 1767 * Double tap works by looking for two isolated Z-axis accelerometer impulses 1768 * preceded and followed by relatively calm periods of accelerometer motion. 1769 * 1770 * Define an outer and inner window. The inner window specifies how 1771 * long the tap impulse is expected to last. The outer window specifies the 1772 * period before the initial tap impluse and after the final tap impulse for 1773 * which to check for relatively calm periods. In between the two impulses 1774 * there is a minimum and maximum interstice time allowed. 1775 * 1776 * Define an acceleration threshold to dectect a tap, in mg. 1777 */ 1778 #undef CONFIG_GESTURE_TAP_OUTER_WINDOW_T 1779 #undef CONFIG_GESTURE_TAP_INNER_WINDOW_T 1780 #undef CONFIG_GESTURE_TAP_MIN_INTERSTICE_T 1781 #undef CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 1782 #undef CONFIG_GESTURE_TAP_THRES_MG 1783 1784 /* Which sensor to look for significant motion activity */ 1785 #undef CONFIG_GESTURE_SIGMO 1786 1787 /* 1788 * Significant motion parameters 1789 * Sigmo state machine looks for movement, waits skip milli-seconds, 1790 * and check for movement again with proof milli-seconds. 1791 */ 1792 #undef CONFIG_GESTURE_SIGMO_PROOF_MS 1793 #undef CONFIG_GESTURE_SIGMO_SKIP_MS 1794 #undef CONFIG_GESTURE_SIGMO_THRES_MG 1795 1796 /* 1797 * Delay between power on and configuring GPIOs. 1798 * On power-on of some boards, H1 releases the EC from reset but then 1799 * quickly asserts and releases the reset a second time. This means the 1800 * EC sees 2 resets: (1) power-on reset, (2) reset-pin reset. If we add 1801 * a delay between reset (1) and configuring GPIO output levels, then 1802 * reset (2) will happen before the end of the delay so we avoid extra 1803 * output toggles. 1804 * 1805 * NOTE: Implemented only for npcx 1806 */ 1807 #undef CONFIG_GPIO_INIT_POWER_ON_DELAY_MS 1808 1809 /* Support getting gpio flags. */ 1810 #undef CONFIG_GPIO_GET_EXTENDED 1811 1812 /* Support disabling sleep with GPIO flags. */ 1813 #undef CONFIG_GPIO_DISABLE_SLEEP 1814 1815 /* Do we want to detect the lid angle? */ 1816 #undef CONFIG_LID_ANGLE 1817 1818 /* Which sensor is located on the base? */ 1819 #undef CONFIG_LID_ANGLE_SENSOR_BASE 1820 /* Which sensor is located on the lid? */ 1821 #undef CONFIG_LID_ANGLE_SENSOR_LID 1822 /* 1823 * Allows using the lid angle measurement to determine if peripheral devices 1824 * should be enabled or disabled, like key scanning, trackpad interrupt. 1825 */ 1826 #undef CONFIG_LID_ANGLE_UPDATE 1827 1828 /* 1829 * Defer the (re)configuration of motion sensors after the suspend event or 1830 * resume event. Sensor power rails may be powered up or down asynchronously 1831 * from the EC, so it may be necessary to wait some time period before 1832 * reconfiguring after a transition. 1833 */ 1834 #define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US 0 1835 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US 0 1836 1837 /* Define motion sensor count in board layer */ 1838 #undef CONFIG_DYNAMIC_MOTION_SENSOR_COUNT 1839 1840 /* Define when LPC memory space needs to be populated. */ 1841 #undef CONFIG_MOTION_FILL_LPC_SENSE_DATA 1842 1843 /******************************************************************************/ 1844 /* Host to RAM (H2RAM) Memory Mapping */ 1845 1846 /* H2RAM Base memory address */ 1847 #undef CONFIG_H2RAM_BASE 1848 1849 /* H2RAM Size */ 1850 #undef CONFIG_H2RAM_SIZE 1851 1852 /* H2RAM Host LPC I/O base memory address */ 1853 #undef CONFIG_H2RAM_HOST_LPC_IO_BASE 1854 1855 /* ISH boot start address */ 1856 #undef CONFIG_ISH_BOOT_START 1857 /* 1858 * Define the minimal amount of time (in ms) betwen running motion sense task 1859 * loop. 1860 */ 1861 #define CONFIG_MOTION_MIN_SENSE_WAIT_TIME 3 1862 1863 /*****************************************************************************/ 1864 /* 1865 * Support the host asking the EC about the status of the most recent host 1866 * command. 1867 * 1868 * When the AP is attached to the EC via a serialized bus such as I2C or SPI, 1869 * it needs a way to minimize the length of time an EC command will tie up the 1870 * bus (and the kernel driver on the AP). If this config is defined, the EC 1871 * may return an in-progress result code for slow commands such as flash 1872 * erase/write instead of stalling until the command finishes processing, and 1873 * the AP may then inquire the status of the current command and/or the result 1874 * of the previous command. 1875 */ 1876 #undef CONFIG_HOST_COMMAND_STATUS 1877 1878 /* clear bit(s) to mask reporting of an EC_HOST_EVENT_XXX event(s) */ 1879 #define CONFIG_HOST_EVENT_REPORT_MASK 0xffffffff 1880 #define CONFIG_HOST_EVENT64_REPORT_MASK 0xffffffffffffffffULL 1881 1882 /* Config option to support 64-bit hostevents and wake-masks. */ 1883 #define CONFIG_HOST_EVENT64 1884 1885 /* 1886 * The host commands are sorted in the .rodata.hcmds section so use the binary 1887 * search algorithm to match a command to its handler 1888 */ 1889 #undef CONFIG_HOSTCMD_SECTION_SORTED 1890 1891 /* 1892 * Host command parameters and response are 32-bit aligned. This generates 1893 * much more efficient code on ARM. 1894 */ 1895 #undef CONFIG_HOSTCMD_ALIGNED 1896 1897 /* 1898 * Include host commands to fetch battery information from 1899 * ec_response_battery_static/dynamic_info structures, only makes sense when 1900 * CONFIG_BATTERY_V2 is enabled. 1901 */ 1902 #undef CONFIG_HOSTCMD_BATTERY_V2 1903 1904 /* Default hcdebug mode, e.g. HCDEBUG_OFF or HCDEBUG_NORMAL */ 1905 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_NORMAL 1906 1907 /* If we have host command task, assume we also are using host events. */ 1908 #ifdef HAS_TASK_HOSTCMD 1909 #define CONFIG_HOSTCMD_EVENTS 1910 #else 1911 #undef CONFIG_HOSTCMD_EVENTS 1912 #endif 1913 1914 /* 1915 * Board supports host command to get EC SPI flash info. This is typically 1916 * only needed if the factory needs to determine which of several possible SPI 1917 * flash chips is attached to the EC on a given board. 1918 */ 1919 #undef CONFIG_HOSTCMD_FLASH_SPI_INFO 1920 1921 /* 1922 * Host command rate limiting assures EC will have time to process lower 1923 * priority tasks even if the AP is hammering the EC with host commands. 1924 * If there is less than CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST between 1925 * host commands for CONFIG_HOSTCMD_RATE_LIMITING_PERIOD, then a 1926 * recess period of CONFIG_HOSTCMD_RATE_LIMITING_RECESS will be 1927 * enforced. 1928 */ 1929 #define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC) 1930 #define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC) 1931 #define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC) 1932 1933 /* PD MCU supports host commands */ 1934 #undef CONFIG_HOSTCMD_PD 1935 1936 /* EC supports EC_CMD_PD_CHIP_INFO */ 1937 #define CONFIG_EC_CMD_PD_CHIP_INFO 1938 1939 /* 1940 * Use if PD MCU controls charging (selecting charging port and input 1941 * current limit). 1942 */ 1943 #undef CONFIG_HOSTCMD_PD_CHG_CTRL 1944 1945 /* Panic when status of PD MCU reflects that it has crashed */ 1946 #undef CONFIG_HOSTCMD_PD_PANIC 1947 1948 /* Board supports RTC host commands*/ 1949 #undef CONFIG_HOSTCMD_RTC 1950 1951 /* Command to issue AP reset */ 1952 #undef CONFIG_HOSTCMD_AP_RESET 1953 1954 /* Flash commands over PD */ 1955 #define CONFIG_HOSTCMD_FLASHPD 1956 1957 /* Set entry in PD MCU's device rw_hash table */ 1958 #define CONFIG_HOSTCMD_RWHASHPD 1959 1960 /* List of host commands whose debug output will be suppressed */ 1961 #undef CONFIG_SUPPRESSED_HOST_COMMANDS 1962 1963 /*****************************************************************************/ 1964 1965 /* Enable debugging and profiling statistics for hook functions */ 1966 #undef CONFIG_HOOK_DEBUG 1967 1968 /*****************************************************************************/ 1969 /* CRC configuration */ 1970 1971 /* Enable the hardware accelerator for CRC computation */ 1972 #undef CONFIG_HW_CRC 1973 1974 /* Enable the software routine for CRC computation */ 1975 #undef CONFIG_SW_CRC 1976 1977 /*****************************************************************************/ 1978 1979 /* Enable system hibernate */ 1980 #define CONFIG_HIBERNATE 1981 1982 /* Default delay after shutting down before hibernating */ 1983 #define CONFIG_HIBERNATE_DELAY_SEC 3600 1984 1985 /* 1986 * Use to define going in to hibernate early if low on battery. 1987 * CONFIG_HIBERNATE_BATT_PCT specifies the low battery threshold 1988 * for going into hibernate early, and CONFIG_HIBERNATE_BATT_SEC defines 1989 * the minimum amount of time to stay in G3 before checking for low 1990 * battery hibernate. 1991 */ 1992 #undef CONFIG_HIBERNATE_BATT_PCT 1993 #undef CONFIG_HIBERNATE_BATT_SEC 1994 1995 /* For ECs with multiple wakeup pins, define enabled wakeup pins */ 1996 #undef CONFIG_HIBERNATE_WAKEUP_PINS 1997 1998 /* 1999 * If defined, chip hibernation is used. Your board needs to define wake-up 2000 * signals. Undefine this to use board hibernation capability. 2001 */ 2002 #define CONFIG_SUPPORT_CHIP_HIBERNATION 2003 2004 /* Use a hardware specific udelay(). */ 2005 #undef CONFIG_HW_SPECIFIC_UDELAY 2006 2007 /*****************************************************************************/ 2008 /* I2C configuration */ 2009 2010 #undef CONFIG_I2C 2011 #undef CONFIG_I2C_DEBUG 2012 #undef CONFIG_I2C_DEBUG_PASSTHRU 2013 #undef CONFIG_I2C_PASSTHROUGH 2014 #undef CONFIG_I2C_PASSTHRU_RESTRICTED 2015 #undef CONFIG_I2C_VIRTUAL_BATTERY 2016 2017 /* 2018 * Define this option if an i2c bus may be unpowered at a certain point during 2019 * runtime. An example could be, a sensor bus which is not needed in lower 2020 * power states so the power rail for those sensors is completely disabled. 2021 * 2022 * If defined, your board must provide a board_is_i2c_port_powered() function. 2023 */ 2024 #undef CONFIG_I2C_BUS_MAY_BE_UNPOWERED 2025 2026 /* 2027 * Conservative I2C reading size per single transaction. For example, register 2028 * of stm32f0 and stm32l4 are limited to be 8 bits for this field. 2029 */ 2030 #define CONFIG_I2C_CHIP_MAX_READ_SIZE 255 2031 2032 /* 2033 * Enable i2c_xfer() for receiving request larger than 2034 * CONFIG_I2C_CHIP_MAX_READ_SIZE. 2035 */ 2036 #undef CONFIG_I2C_XFER_LARGE_READ 2037 2038 /* 2039 * If defined, makes i2c_xfer callback into board-provided functions before the 2040 * start and after the end of every I2C transaction. This can be used by boards 2041 * to implement any I2C device specific quirks e.g. requiring minimum bus-free 2042 * time between every I2C transaction with a device. 2043 */ 2044 #undef CONFIG_I2C_XFER_BOARD_CALLBACK 2045 2046 /* 2047 * EC uses an I2C controller interface. 2048 * Note: if this is defined, i2c_init() will be called 2049 * automatically at board boot. 2050 */ 2051 #undef CONFIG_I2C_CONTROLLER 2052 2053 /* EC uses an I2C peripheral interface */ 2054 #undef CONFIG_I2C_PERIPH 2055 2056 /* Defines I2C operation retry count when peripheral nack'd(EC_ERROR_BUSY) */ 2057 #define CONFIG_I2C_NACK_RETRY_COUNT 0 2058 /* 2059 * I2C SCL gating. 2060 * 2061 * If CONFIG_I2C_SCL_GATE_ADDR/PORT is defined, whenever the defined address 2062 * is addressed, CONFIG_I2C_SCL_GATE_GPIO is set to high. When the I2C 2063 * transaction is done, the pin is set back to low. 2064 */ 2065 #undef CONFIG_I2C_SCL_GATE_PORT 2066 #undef CONFIG_I2C_SCL_GATE_ADDR_FLAGS 2067 #undef CONFIG_I2C_SCL_GATE_GPIO 2068 2069 /* 2070 * Some chip supports two owned peripheral address. The second peripheral 2071 * address is used for other purpose such as board specific i2c commands. This 2072 * option can be set if user of the second peripheral address requires larger 2073 * host packet buffer size. 2074 */ 2075 #define CONFIG_I2C_EXTRA_PACKET_SIZE 0 2076 2077 /* 2078 * I2C multi-port controller. 2079 * 2080 * If CONFIG_I2C_MULTI_PORT_CONTROLLER is defined, a single on-chip I2C 2081 * controller may have multiple I2C ports attached. Therefore, I2c operations 2082 * must lock the controller (not just the port) to prevent hardware access 2083 * conflicts. 2084 */ 2085 #undef CONFIG_I2C_MULTI_PORT_CONTROLLER 2086 2087 /* 2088 * Packet error checking support for SMBus. 2089 * 2090 * If defined, adds error checking support for i2c_readN, i2c_writeN, 2091 * i2c_read_string and i2c_write_block. Where 2092 * - write operation appends an error checking byte at end of transfer, and 2093 * - read operatoin verifies the correctness of error checking byte from the 2094 * peripheral. 2095 * Set I2C_FLAG on addr_flags parameter to use this feature. 2096 * 2097 * This option also enables error checking function on smart batteries. 2098 */ 2099 #undef CONFIG_SMBUS_PEC 2100 2101 /*****************************************************************************/ 2102 /* IPI configuration. Support mt_scp only for now. */ 2103 2104 /* EC support Inter-Processor Interrupt. */ 2105 #undef CONFIG_IPI 2106 2107 /* 2108 * IPC0/IPI shared object address. This is the starting address of the send 2109 * object and the receive object. Each object contains a buffer. 2110 */ 2111 #undef CONFIG_IPC_SHARED_OBJ_ADDR 2112 2113 /* "buffer" size of ipc_shared_obj. */ 2114 #undef CONFIG_IPC_SHARED_OBJ_BUF_SIZE 2115 2116 /* EC support rpmsg name service over IPI. */ 2117 #undef CONFIG_RPMSG_NAME_SERVICE 2118 2119 /*****************************************************************************/ 2120 /* Current/Power monitor */ 2121 2122 /* 2123 * Compile driver for INA219 or INA231 or INA3221. 2124 * Only one of these may be defined (if any). 2125 */ 2126 #undef CONFIG_INA219 2127 #undef CONFIG_INA231 2128 #undef CONFIG_INA3221 2129 2130 /*****************************************************************************/ 2131 /* Inductive charging */ 2132 2133 /* Enable inductive charging support */ 2134 #undef CONFIG_INDUCTIVE_CHARGING 2135 2136 /******************************************************************************/ 2137 2138 /* Support IT8801 I/O expander. */ 2139 #undef CONFIG_IO_EXPANDER_IT8801 2140 2141 /* Support Nuvoton NCT38xx I/O expander. */ 2142 #undef CONFIG_IO_EXPANDER_NCT38XX 2143 2144 /* Support NXP PCA9534 I/O expander. */ 2145 #undef CONFIG_IO_EXPANDER_PCA9534 2146 2147 /*****************************************************************************/ 2148 2149 /* Number of IRQs supported on the EC chip */ 2150 #undef CONFIG_IRQ_COUNT 2151 2152 /* Enable LDN for KBC mouse */ 2153 #undef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE 2154 2155 /* 2156 * The IT8320 supports e-flash clock up to 48 MHz (IT8390 maximum is 32 MHz). 2157 * Enable it if we want better performance of fetching instruction from e-flash. 2158 * 2159 * This is valid with PLL frequency equal to 48/96MHz only. 2160 */ 2161 #undef CONFIG_IT83XX_FLASH_CLOCK_48MHZ 2162 2163 /* To define it, if I2C channel C and PECI used at the same time. */ 2164 #undef CONFIG_IT83XX_SMCLK2_ON_GPC7 2165 2166 /* 2167 * If this is not defined, the firmware will revert the JTAG selection 2168 * triggered by the hardware strap pin. 2169 * Un-define this flag by default for all real platforms. see (b/129908668) 2170 * If some boards (Ex:EVB) require JTAG function, they can define it in 2171 * their board.h 2172 */ 2173 #undef CONFIG_ENABLE_JTAG_SELECTION 2174 2175 /*****************************************************************************/ 2176 /* Keyboard config */ 2177 2178 /* 2179 * The Silego reset chip sits in between the EC and the physical keyboard on 2180 * column 2. To save power in low-power modes, some Silego variants require 2181 * the signal to be inverted so that the open-drain output from the EC isn't 2182 * costing power due to the pull-up resistor in the Silego. 2183 */ 2184 #undef CONFIG_KEYBOARD_COL2_INVERTED 2185 2186 /* 2187 * Keyboards with the assistant key also move the refresh key matrix to row 3 2188 * instead of row 2. This is used by the boot key detection code to determine 2189 * if the refresh key is held down at boot. 2190 */ 2191 #undef CONFIG_KEYBOARD_REFRESH_ROW3 2192 2193 /* 2194 * Config KSO to start from a different KSO pin. This is to allow some chips 2195 * to use alternate functions on KSO pins. 2196 */ 2197 #define CONFIG_KEYBOARD_KSO_BASE 0 2198 2199 /* 2200 * For certain board configurations, KSI2 or KSI3 will be stuck asserted for all 2201 * scan columns if the power button is held. We must be aware of this case 2202 * in order to correctly handle recovery mode key combinations. 2203 */ 2204 #undef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 2205 #undef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3 2206 2207 /* Enable extra debugging output from keyboard modules */ 2208 #undef CONFIG_KEYBOARD_DEBUG 2209 2210 /* 2211 * Disables the directly connected keyboard pins and drivers on a particular 2212 * chip. You might want this enabled if the keyboard is indirectly connected 2213 * to the EC, perhaps through an I2C controller. 2214 */ 2215 #undef CONFIG_KEYBOARD_NOT_RAW 2216 2217 /* The board uses a negative edge-triggered GPIO for keyboard interrupts. */ 2218 #undef CONFIG_KEYBOARD_IRQ_GPIO 2219 2220 /* Compile code for 8042 keyboard protocol */ 2221 #undef CONFIG_KEYBOARD_PROTOCOL_8042 2222 2223 /* Compile code for MKBP keyboard protocol */ 2224 #undef CONFIG_KEYBOARD_PROTOCOL_MKBP 2225 2226 /* Support keyboard factory test scanning */ 2227 #undef CONFIG_KEYBOARD_FACTORY_TEST 2228 2229 /* 2230 * Keyboard config (struct keyboard_scan_config) is in board.c. If this is 2231 * not defined, default values from common/keyboard_scan.c will be used. 2232 */ 2233 #undef CONFIG_KEYBOARD_BOARD_CONFIG 2234 2235 /* 2236 * Support for boot key combinations (e.g. refresh key being held on boot to 2237 * trigger recovery). 2238 */ 2239 #define CONFIG_KEYBOARD_BOOT_KEYS 2240 2241 /* Add support for the assistant key. */ 2242 #undef CONFIG_KEYBOARD_ASSISTANT_KEY 2243 2244 /* Add support for a switch that indicates if the device is in tablet mode. */ 2245 #undef CONFIG_KEYBOARD_TABLET_MODE_SWITCH 2246 2247 /* 2248 * Minimum CPU clocks between scans. This ensures that keyboard scanning 2249 * doesn't starve the other EC tasks of CPU when running at a decreased system 2250 * clock. 2251 */ 2252 #undef CONFIG_KEYBOARD_POST_SCAN_CLOCKS 2253 2254 /* Print keyboard scan time intervals. */ 2255 #undef CONFIG_KEYBOARD_PRINT_SCAN_TIMES 2256 2257 /* 2258 * Support for extra runtime key combinations (e.g. alt+volup+h/r for hibernate 2259 * and warm reboot, respectively). 2260 */ 2261 #define CONFIG_KEYBOARD_RUNTIME_KEYS 2262 2263 /* 2264 * Allow the keyboard scan code set tables to be modified at runtime. 2265 */ 2266 #undef CONFIG_KEYBOARD_SCANCODE_MUTABLE 2267 2268 /* 2269 * Allow board-specific 8042 keyboard callback when a key state is changed. 2270 */ 2271 #undef CONFIG_KEYBOARD_SCANCODE_CALLBACK 2272 2273 /* 2274 * Call board-supplied keyboard_suppress_noise() function when the debounced 2275 * keyboard state changes. Some boards use this to send a signal to the audio 2276 * codec to suppress typing noise picked up by the microphone. 2277 */ 2278 #undef CONFIG_KEYBOARD_SUPPRESS_NOISE 2279 2280 /* 2281 * Enable keyboard testing functionality. This enables a message which receives 2282 * a list of keyscan events from the AP and processes them. This will cause 2283 * keypresses to appear on the AP through the same mechanism as a normal 2284 * keyboard press. 2285 * 2286 * This can be used to spoof keyboard events, so is not normally defined, 2287 * except during internal testing. 2288 */ 2289 #undef CONFIG_KEYBOARD_TEST 2290 2291 /* 2292 * Enable quasi-bidirectional buffers for KSO pins. It has an open-drain output 2293 * and a low-impedance pull-up. The low-impedance pull-up is active when ec 2294 * changes the output data buffers from 0 to 1, thereby reducing the 2295 * low-to-high transition time. 2296 */ 2297 #undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE 2298 2299 /* 2300 * Add support for keyboards with language ID pins 2301 */ 2302 #undef CONFIG_KEYBOARD_LANGUAGE_ID 2303 2304 /* 2305 * Enable keypad (a palm-sized keyboard section usually placed on the far right) 2306 */ 2307 #undef CONFIG_KEYBOARD_KEYPAD 2308 2309 /*****************************************************************************/ 2310 2311 /*****************************************************************************/ 2312 2313 /* Support common LED interface */ 2314 #undef CONFIG_LED_COMMON 2315 2316 /* Standard LED behavior according to spec given that we have a red-green 2317 * bicolor led for charging and one power led 2318 */ 2319 #undef CONFIG_LED_POLICY_STD 2320 2321 /* 2322 * Support common PWM-controlled LEDs that conform to the Chrome OS LED 2323 * behaviour specification. 2324 */ 2325 #undef CONFIG_LED_PWM 2326 2327 /* 2328 * Here are some recommended color settings by default, but a board can change 2329 * the colors to one of "enum ec_led_colors" as they see fit. 2330 */ 2331 #define CONFIG_LED_PWM_CHARGE_COLOR EC_LED_COLOR_AMBER 2332 #define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_GREEN 2333 #define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_RED 2334 #define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_GREEN 2335 #define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_GREEN 2336 #define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER 2337 2338 /* 2339 * By default the PWM LED behaviour is reflected on both LEDs and includes the 2340 * chipset state, battery state, as well as the charging state. Enable 2341 * this CONFIG_* option to show only the charging state on the LEDs. 2342 */ 2343 #undef CONFIG_LED_PWM_CHARGE_STATE_ONLY 2344 2345 /* 2346 * By default the PWM LED behaviour is reflected on both LEDs and includes the 2347 * chipset state, battery state, as well as the charging state. Enable 2348 * this CONFIG_* option to show only the charging state, and only on the LED of 2349 * the active charge port. 2350 */ 2351 #undef CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY 2352 2353 /* 2354 * How many PWM LEDs does the system have that will be controlled by the common 2355 * PWM LED policy? Currently, this may be at most 2. 2356 */ 2357 #undef CONFIG_LED_PWM_COUNT 2358 2359 /* 2360 * Support GPIO-controlled LEDs for common battery/power 2361 * states through a board-defined lookup table. 2362 */ 2363 #undef CONFIG_LED_ONOFF_STATES 2364 2365 /* 2366 * Set the battery charge percentage for optional STATE_DISCHARGE_S0_BAT_LOW 2367 * provided by CONFIG_LED_ONOFF_STATES. 2368 */ 2369 #undef CONFIG_LED_ONOFF_STATES_BAT_LOW 2370 2371 /* 2372 * Adds a power LED under the control of the board-defined lookup table. 2373 * Must be used with the CONFIG_LED_ONOFF_STATES option. 2374 */ 2375 #undef CONFIG_LED_POWER_LED 2376 2377 /* 2378 * LEDs for LED_POLICY STD may be inverted. In this case they are active low 2379 * and the GPIO names will be GPIO_LED..._L. 2380 */ 2381 #undef CONFIG_LED_BAT_ACTIVE_LOW 2382 #undef CONFIG_LED_POWER_ACTIVE_LOW 2383 2384 /* Support for LED driver chip(s) */ 2385 #undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */ 2386 #undef CONFIG_LED_DRIVER_LM3509 /* LM3509, on I2C interface */ 2387 #undef CONFIG_LED_DRIVER_LM3630A /* LM3630A, on I2C interface */ 2388 #undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */ 2389 #undef CONFIG_LED_DRIVER_OZ554 /* O2Micro OZ554, on I2C */ 2390 2391 /* Offset in flash where little firmware will live. */ 2392 #undef CONFIG_LFW_OFFSET 2393 2394 /* 2395 * Compile lid switch support. 2396 * 2397 * This is enabled by default because all boards other than reference boards 2398 * are for laptops with lid switchs. Reference boards #undef it. 2399 */ 2400 #define CONFIG_LID_SWITCH 2401 2402 /* 2403 * GPIOs to use to detect that the lid is opened. 2404 * 2405 * This is a X-macro composed of a list of LID_OPEN(GPIO_xxx) elements defining 2406 * all the GPIOs to check to find whether the lid is currently opened. 2407 * If not defined, it is using GPIO_LID_OPEN. 2408 */ 2409 #undef CONFIG_LID_SWITCH_GPIO_LIST 2410 2411 /* 2412 * Support for turning the lightbar power rails on briefly when the AP is off. 2413 * Enabling this requires implementing the board-specific lb_power() function 2414 * to do it (see lb_common.h). 2415 */ 2416 #undef CONFIG_LIGHTBAR_POWER_RAILS 2417 2418 /* 2419 * For tap sequence, show the last segment in dim to give a better idea of 2420 * battery percentage. 2421 */ 2422 #undef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT 2423 2424 /* 2425 * Adds a console command for testing the long long shift right ABI on Cortex-m4 2426 * (Cr50). 2427 */ 2428 #undef CONFIG_LLSR_TEST 2429 2430 /* Program memory offset for little firmware loader. */ 2431 #undef CONFIG_LOADER_MEM_OFF 2432 2433 /* Size of little firmware loader. */ 2434 #undef CONFIG_LOADER_SIZE 2435 2436 /* Little firmware loader storage offset. */ 2437 #undef CONFIG_LOADER_STORAGE_OFF 2438 2439 /* 2440 * Low power idle options. These are disabled by default and all boards that 2441 * want to use low power idle must define it. When using the LFIOSC, the low 2442 * frequency clock will be used to conserve even more power when possible. 2443 * 2444 * GPIOs which need to trigger interrupts in low power idle must specify the 2445 * GPIO_INT_DSLEEP flag in gpio_list[]. 2446 * 2447 * Note that for some processors (e.g. LM4), an active JTAG connection will 2448 * prevent the EC from using low-power idle. 2449 */ 2450 #undef CONFIG_LOW_POWER_IDLE 2451 #undef CONFIG_LOW_POWER_USE_LFIOSC 2452 2453 /* 2454 * Enable deep sleep during S0 (ignores SLEEP_MASK_AP_RUN). 2455 */ 2456 #undef CONFIG_LOW_POWER_S0 2457 2458 /* DMA paging between SRAM and DRAM */ 2459 #undef CONFIG_DMA_PAGING 2460 2461 /* 2462 * Enable HID subsystem using HECI on Intel ISH (Integrated Sensor Hub) 2463 */ 2464 #undef CONFIG_HID_HECI 2465 2466 /* Support host command interface over HECI */ 2467 #undef CONFIG_HOSTCMD_HECI 2468 2469 /* 2470 * EC supports x86 host communication with AP. This can either be through LPC 2471 * or eSPI. The CONFIG_HOSTCMD_X86 will get automatically defined if either 2472 * CONFIG_HOSTCMD_LPC or CONFIG_HOSTCMD_ESPI are defined. LPC and eSPI are 2473 * mutually exclusive. 2474 */ 2475 #undef CONFIG_HOSTCMD_X86 2476 /* Support host command interface over LPC bus. */ 2477 #undef CONFIG_HOSTCMD_LPC 2478 /* Support host command interface over eSPI bus. */ 2479 #undef CONFIG_HOSTCMD_ESPI 2480 2481 /* 2482 * SLP signals (SLP_S3 and SLP_S4) use virtual wires intead of physical pins 2483 * with eSPI interface. 2484 */ 2485 #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 2486 #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 2487 2488 /* MCHP next two items are EC eSPI peripheral configuration */ 2489 /* Maximum clock frequence eSPI EC peripheral advertises 2490 * Values in MHz are 20, 25, 33, 50, and 66 2491 */ 2492 #undef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ 2493 2494 /* EC eSPI peripheral advertises IO lanes 2495 * 0 = Single 2496 * 1 = Single and Dual 2497 * 2 = Single and Quad 2498 * 3 = Single, Dual, and Quad 2499 */ 2500 #undef CONFIG_HOSTCMD_ESPI_EC_MODE 2501 2502 /* Bit map of eSPI channels EC advertises 2503 * bit[0] = 1 Peripheral channel 2504 * bit[1] = 1 Virtual Wire channel 2505 * bit[2] = 1 OOB channel 2506 * bit[3] = 1 Flash channel 2507 */ 2508 #undef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP 2509 2510 /* Base address of low power RAM. */ 2511 #undef CONFIG_LPRAM_BASE 2512 2513 /* Size of low power RAM. */ 2514 #undef CONFIG_LPRAM_SIZE 2515 2516 /* Use Link-Time Optimizations to try to reduce the firmware code size */ 2517 #undef CONFIG_LTO 2518 2519 /* Provide rudimentary malloc/free like services for shared memory. */ 2520 #undef CONFIG_MALLOC 2521 2522 /* Need for a math library */ 2523 #undef CONFIG_MATH_UTIL 2524 2525 /* Include code to do online compass calibration */ 2526 #undef CONFIG_MAG_CALIBRATE 2527 2528 /* Microchip EC SRAM start address */ 2529 #undef CONFIG_MEC_SRAM_BASE_START 2530 2531 /* Microchip EC SRAM end address */ 2532 #undef CONFIG_MEC_SRAM_BASE_END 2533 2534 /* Microchip EC SRAM size */ 2535 #undef CONFIG_MEC_SRAM_SIZE 2536 2537 /* 2538 * Define Megachips DisplayPort to HDMI protocol converter/level shifter serial 2539 * interface. 2540 */ 2541 #undef CONFIG_MCDP28X0 2542 2543 /* Define clock input to MFT module. */ 2544 #undef CONFIG_MFT_INPUT_LFCLK 2545 2546 /* Minute-IA watchdog timer vector number. */ 2547 #define CONFIG_MIA_WDT_VEC 0xFF 2548 2549 /* Support MKBP event */ 2550 #undef CONFIG_MKBP_EVENT 2551 2552 /* MKBP events are sent by using host event */ 2553 #undef CONFIG_MKBP_USE_HOST_EVENT 2554 2555 /* MKBP events are sent by using GPIO */ 2556 #undef CONFIG_MKBP_USE_GPIO 2557 2558 /* 2559 * MKBP events are notified by using both a GPIO and a host event. 2560 * 2561 * You should use this if you are using a GPIO to notify the AP of an MKBP 2562 * event, and you need an MKBP event to wake the AP in suspend and the AP cannot 2563 * wake from the GPIO. Since you are using both a GPIO and a hostevent for the 2564 * notification, make sure that the S0 hostevent mask does NOT include MKBP 2565 * events. Otherwise, you will have multiple consumers for a single event. 2566 * However, make sure to configure the host event *sleep* mask in coreboot to 2567 * include MKBP events. In order to prevent all MKBP events from waking the AP, 2568 * use CONFIG_MKBP_EVENT_WAKEUP_MASK to filter the events. 2569 */ 2570 #undef CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT 2571 2572 /* MKBP events are sent by using HECI on an ISH */ 2573 #undef CONFIG_MKBP_USE_HECI 2574 2575 /* MKBP events are sent by using custom method */ 2576 #undef CONFIG_MKBP_USE_CUSTOM 2577 2578 /* 2579 * If using MKBP to send host events, with this option, we can define the host 2580 * events that should wake the system in suspend. Some examples are: 2581 * 2582 * EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) 2583 * EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) 2584 * 2585 * The only things that should be in this mask are: 2586 * EC_HOST_EVENT_MASK(EC_HOST_EVENT_*) 2587 */ 2588 #undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK 2589 2590 /* 2591 * Define which MKBP events should wakeup the system in suspend. Some examples 2592 * are: 2593 * 2594 * EC_MKBP_EVENT_KEY_MATRIX 2595 * EC_MKBP_EVENT_SWITCH 2596 * 2597 * The only things that should be in this mask are EC_MKBP_EVENT_*. 2598 */ 2599 #undef CONFIG_MKBP_EVENT_WAKEUP_MASK 2600 2601 /* Support memory protection unit (MPU) */ 2602 #undef CONFIG_MPU 2603 2604 /* Do not try hold I/O pins at frozen level during deep sleep */ 2605 #undef CONFIG_NO_PINHOLD 2606 2607 /* Support one-wire interface */ 2608 #undef CONFIG_ONEWIRE 2609 2610 /* Support PECI interface to x86 processor */ 2611 #undef CONFIG_PECI 2612 2613 /* Common code for PECI interface to x86 processor */ 2614 #undef CONFIG_PECI_COMMON 2615 2616 /* 2617 * Maximum operating temperature in degrees Celcius used on some x86 2618 * processors. CPU chip temperature is reported relative to this value and 2619 * is never reported greater than this value. Processor asserts PROCHOT# 2620 * and starts throttling frequency and voltage at this temp. Operation may 2621 * become unreliable if temperature exceeds this limit. 2622 */ 2623 #undef CONFIG_PECI_TJMAX 2624 2625 /* Support physical presence detection (via a physical button) */ 2626 #undef CONFIG_PHYSICAL_PRESENCE 2627 2628 /* Enable (unsafe!) developer debug features for physical presence */ 2629 #undef CONFIG_PHYSICAL_PRESENCE_DEBUG_UNSAFE 2630 2631 /*****************************************************************************/ 2632 /* PinWeaver config 2633 * A feature which exchanges a low entropy secret with rate limits for a high 2634 * entropy secret. This enables a set of vendor specific commands for Cr50. 2635 */ 2636 /* Use Cr50 pinweaver */ 2637 #undef CONFIG_PINWEAVER 2638 /* Use platform/pinweaver */ 2639 #undef CONFIG_PLATFORM_PINWEAVER 2640 2641 /*****************************************************************************/ 2642 /* PMU config */ 2643 2644 /* 2645 * Enable hard-resetting the PMU from the EC. The implementation is rather 2646 * hacky; it simply shorts out the 3.3V rail to force the PMIC to panic. We 2647 * need this unfortunate hack because it's the only way to reset the I2C engine 2648 * inside the PMU. 2649 */ 2650 #undef CONFIG_PMU_HARD_RESET 2651 2652 /* 2653 * Enable this config to make console UART self sufficient (no other 2654 * initialization required before uart_init(), no interrupts, uart_tx_char() 2655 * does not exit until character finished transmitting). 2656 * 2657 * This is useful during early hardware bringup, each platform needs to 2658 * implement its own code to support this. 2659 */ 2660 #undef CONFIG_POLLING_UART 2661 2662 /* Define length of history buffer for port80 messages. */ 2663 #define CONFIG_PORT80_HISTORY_LEN 128 2664 2665 /* 2666 * Enable/Disable printing of port80 messages in interrupt context. By default, 2667 * this is disabled. 2668 */ 2669 #define CONFIG_PORT80_PRINT_IN_INT 0 2670 2671 /* MAX695x 7 segment driver */ 2672 #undef CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY 2673 2674 /* Config for power states and port80 message to be displayed on 7 -segment */ 2675 #undef CONFIG_SEVEN_SEG_DISPLAY 2676 2677 /* Compile common code to support power button debouncing */ 2678 #undef CONFIG_POWER_BUTTON 2679 2680 /* Force the active state of the power button : 0(default if unset) or 1 */ 2681 #undef CONFIG_POWER_BUTTON_ACTIVE_STATE 2682 2683 /* Allow the power button to send events while the lid is closed */ 2684 #undef CONFIG_POWER_BUTTON_IGNORE_LID 2685 2686 /* Support sending the power button signal to x86 chipsets */ 2687 #undef CONFIG_POWER_BUTTON_X86 2688 2689 /* Set power button state idle at init. Implemented only for npcx. */ 2690 #undef CONFIG_POWER_BUTTON_INIT_IDLE 2691 2692 /* Timeout before power button task gives up starting system */ 2693 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 1 2694 2695 /* Compile common code for AP power state machine */ 2696 #undef CONFIG_POWER_COMMON 2697 2698 /* Enable a task-safe way to control the PP5000 rail. */ 2699 #undef CONFIG_POWER_PP5000_CONTROL 2700 2701 /* Support stopping in S5 on shutdown */ 2702 #undef CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 2703 2704 /* 2705 * Detect power signal interrupt storms, defined as more than 2706 * CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD occurences of a single 2707 * power signal interrupt within one second. 2708 */ 2709 #undef CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 2710 2711 /* Use part of the EC's data EEPROM to hold persistent storage for the AP. */ 2712 #undef CONFIG_PSTORE 2713 2714 /* Support S0ix */ 2715 #undef CONFIG_POWER_S0IX 2716 2717 /* Support detecting failure to enter S0ix */ 2718 #undef CONFIG_POWER_S0IX_FAILURE_DETECTION 2719 2720 /* 2721 * Allow the host to self-report its sleep state, in case there is some delay 2722 * between the host beginning to enter the sleep state and power signals 2723 * actually reflecting the new state. 2724 */ 2725 #undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE 2726 2727 /* 2728 * Implement the '%li' printf format as a *32-bit* integer format, 2729 * as it might be expected by non-EC code. 2730 */ 2731 #undef CONFIG_PRINTF_LEGACY_LI_FORMAT 2732 2733 /* 2734 * On x86 systems, define this option if the CPU_PROCHOT signal is active low. 2735 */ 2736 #undef CONFIG_CPU_PROCHOT_ACTIVE_LOW 2737 2738 /*****************************************************************************/ 2739 /* Support PWM control */ 2740 #undef CONFIG_PWM 2741 2742 /* Define clock input to PWM module. */ 2743 #undef CONFIG_PWM_INPUT_LFCLK 2744 2745 /*****************************************************************************/ 2746 /* Support PWM output to display backlight */ 2747 #undef CONFIG_PWM_DISPLIGHT 2748 2749 /* 2750 * Support keyboard backlight control 2751 * 2752 * You need to define board_kblight_init unless CONFIG_PWM_KBLIGHT is used. 2753 * For example, lm3509 can be registered as a driver in board_kblight_init. 2754 */ 2755 #undef CONFIG_KEYBOARD_BACKLIGHT 2756 2757 /* 2758 * Support PWM output to keyboard backlight 2759 * 2760 * This implies CONFIG_KEYBOARD_BACKLIGHT. 2761 */ 2762 #undef CONFIG_PWM_KBLIGHT 2763 2764 /* Size of each RAM bank in chip, default is CONFIG_RAM_SIZE */ 2765 #undef CONFIG_RAM_BANK_SIZE 2766 2767 /* 2768 * Number of RAM banks in chip, default is 2769 * CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE 2770 */ 2771 #undef CONFIG_RAM_BANKS 2772 2773 /* Base address of RAM for the chip */ 2774 #undef CONFIG_RAM_BASE 2775 2776 /* 2777 * CONFIG_DATA_RAM_SIZE and CONFIG_RAM_SIZE indicate size of all data RAM 2778 * available on the chip in bytes and size of data RAM available for EC in 2779 * bytes, respectively. 2780 * Usually, CONFIG_DATA_RAM_SIZE = CONFIG_RAM_SIZE but some chips need to 2781 * allocate RAM for the mask ROM. Then CONFIG_DATA_RAM_SIZE > CONFIG_RAM_SIZE. 2782 */ 2783 #undef CONFIG_DATA_RAM_SIZE 2784 #undef CONFIG_RAM_SIZE 2785 2786 /* Enable rbox peripheral */ 2787 #undef CONFIG_RBOX 2788 2789 /* Enable rbox wakeup */ 2790 #undef CONFIG_RBOX_WAKEUP 2791 2792 /* Enable RDD peripheral */ 2793 #undef CONFIG_RDD 2794 2795 /* Support IR357x Link voltage regulator debugging / reprogramming */ 2796 #undef CONFIG_REGULATOR_IR357X 2797 2798 /* Support RMA auth challenge-response */ 2799 #undef CONFIG_RMA_AUTH 2800 2801 /* 2802 * Use the p256 curve for RMA challenge-response calculations (x21559 is used 2803 * by default). 2804 */ 2805 #undef CONFIG_RMA_AUTH_USE_P256 2806 2807 /* Support verifying 2048-bit RSA signature */ 2808 #undef CONFIG_RSA 2809 2810 /* Define the RSA key size. */ 2811 #undef CONFIG_RSA_KEY_SIZE 2812 2813 /* Use RSA exponent 3 instead of F4 (65537) */ 2814 #undef CONFIG_RSA_EXPONENT_3 2815 2816 /* 2817 * Adjust the compiler optimization flags for the RSA code to get a speed-up 2818 * at the expense of a small code size delta. 2819 */ 2820 #undef CONFIG_RSA_OPTIMIZED 2821 2822 /* 2823 * Verify the RW firmware using the RSA signature. 2824 * (for accessories without software sync) 2825 */ 2826 #undef CONFIG_RWSIG 2827 2828 /* 2829 * When RWSIG verification is performed as a task, time to wait from signature 2830 * verification to an automatic jump to RW (if AP does not request the wait to 2831 * be interrupted). 2832 */ 2833 #define CONFIG_RWSIG_JUMP_TIMEOUT (1000 * MSEC) 2834 2835 /* 2836 * Defines what type of futility signature type should be used. 2837 * RWSIG should be used for new designs. 2838 * Old adapters use the USBPD1 futility signature type. 2839 */ 2840 #undef CONFIG_RWSIG_TYPE_RWSIG 2841 #undef CONFIG_RWSIG_TYPE_USBPD1 2842 2843 /* 2844 * By default the pubkey and sig are put at the end of the first and second 2845 * half of the total flash, and take up the minimum space possible. You can 2846 * override those defaults with these. 2847 */ 2848 #undef CONFIG_RO_PUBKEY_ADDR 2849 #undef CONFIG_RO_PUBKEY_SIZE 2850 #undef CONFIG_RW_SIG_ADDR 2851 #undef CONFIG_RW_SIG_SIZE 2852 2853 /****************************************************************************/ 2854 /* Shared objects library. */ 2855 2856 /* Support shared objects library between RO and RW. */ 2857 #undef CONFIG_SHAREDLIB 2858 2859 /* Size of shared objects library. */ 2860 #undef CONFIG_SHAREDLIB_SIZE 2861 2862 /* Program memory offset of shared objects library. */ 2863 #undef CONFIG_SHAREDLIB_MEM_OFF 2864 2865 /* Storage offset of sharedobjects library. */ 2866 #undef CONFIG_SHAREDLIB_STORAGE_OFF 2867 2868 /* 2869 * If defined, the hash module will save its last computed hash when jumping 2870 * between EC images. 2871 */ 2872 #undef CONFIG_SAVE_VBOOT_HASH 2873 2874 /* Allow the board to use a GPIO for the SCI# signal. */ 2875 #undef CONFIG_SCI_GPIO 2876 2877 /* Support computing SHA-1 hash */ 2878 #undef CONFIG_SHA1 2879 2880 /* Support computing of other hash sizes (without the VBOOT code) */ 2881 #undef CONFIG_SHA256 2882 2883 /* Unroll some loops in SHA256_transform for better performance. */ 2884 #undef CONFIG_SHA256_UNROLLED 2885 2886 /* Emulate the CLZ (Count Leading Zeros) in software for CPU lacking support */ 2887 #undef CONFIG_SOFTWARE_CLZ 2888 2889 /* Emulate the CLZ (Count Trailing Zeros) in software for CPU lacking support */ 2890 #undef CONFIG_SOFTWARE_CTZ 2891 2892 /* Support smbus interface */ 2893 /* 2894 * Deprecated in 2895 * https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704279 2896 * 2897 * It hasn't been used in over 2 years 2898 * https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/452459/ 2899 * and was only used by one board (pyro). 2900 * 2901 * I2C and SMBus are compatible at the physical layer. The data transfer 2902 * paradigm is different. Some of our batteries are using SMbus style 2903 * transfers now, they are just using i2cxfer directly to accomplish it. 2904 * 2905 * I doubt the SMBus code will get revived, but we do have it in revision 2906 * history if we ever need it. 2907 */ 2908 /* #undef CONFIG_SMBUS */ 2909 2910 /* Support SPI interfaces */ 2911 #undef CONFIG_SPI 2912 2913 /* Support deprecated SPI protocol version 2. */ 2914 #undef CONFIG_SPI_PROTOCOL_V2 2915 2916 /* 2917 * Support SPI periph interfaces. The first board supporting this is cr50 and 2918 * in its parlance SPI_PERIPH is called SPP. This convention might be 2919 * reconsidered later, and the use of "SPI" in different config options needs 2920 * to be cleaned up. (crbug.com/512613). 2921 */ 2922 #undef CONFIG_SPP 2923 2924 /* Define the SPI port to use to access SPI accelerometer */ 2925 #undef CONFIG_SPI_ACCEL_PORT 2926 2927 /* Support SPI flash */ 2928 #undef CONFIG_SPI_FLASH 2929 2930 /* Support SPI flash protection register translation */ 2931 #undef CONFIG_SPI_FLASH_REGS 2932 2933 /* Define the SPI port to use to access the flash */ 2934 #undef CONFIG_SPI_FLASH_PORT 2935 2936 /* Select any of the following SPI flash configs that your board uses. */ 2937 #undef CONFIG_SPI_FLASH_GD25LQ40 2938 #undef CONFIG_SPI_FLASH_GD25Q41B 2939 #undef CONFIG_SPI_FLASH_W25Q128 2940 #undef CONFIG_SPI_FLASH_W25Q40 2941 #undef CONFIG_SPI_FLASH_W25Q64 2942 #undef CONFIG_SPI_FLASH_W25Q80 2943 #undef CONFIG_SPI_FLASH_W25X40 2944 2945 /* SPI flash part supports SR2 register */ 2946 #undef CONFIG_SPI_FLASH_HAS_SR2 2947 2948 /* Define the SPI port to use to access the fingerprint sensor */ 2949 #undef CONFIG_SPI_FP_PORT 2950 2951 /* Support JEDEC SFDP based Serial NOR flash */ 2952 #undef CONFIG_SPI_NOR 2953 2954 /* Enable SPI_NOR debugging providing additional console output while 2955 * initializing Serial NOR Flash devices including SFDP discovery. */ 2956 #undef CONFIG_SPI_NOR_DEBUG 2957 2958 /* Maximum Serial NOR flash command size, in Bytes */ 2959 #undef CONFIG_SPI_NOR_MAX_MESSAGE_SIZE 2960 2961 /* Maximum Serial NOR flash read size, in Bytes */ 2962 #undef CONFIG_SPI_NOR_MAX_READ_SIZE 2963 2964 /* Maximum Serial NOR flash write size, in Bytes. Note this must be a power of 2965 * two. */ 2966 #undef CONFIG_SPI_NOR_MAX_WRITE_SIZE 2967 2968 /* If defined will enable block (64KiB) erase operations. */ 2969 #undef CONFIG_SPI_NOR_BLOCK_ERASE 2970 2971 /* If defined will read the sector/block to be erased first and only initiate 2972 * the erase operation if not already in an erased state. The read operation 2973 * (performed in CONFIG_SPI_NOR_MAX_READ_SIZE chunks) is aborted early if a 2974 * non "0xff" byte is encountered. 2975 * !! Make sure there is enough stack space to host a 2976 * !! CONFIG_SPI_NOR_MAX_READ_SIZE sized buffer before enabling. 2977 */ 2978 #undef CONFIG_SPI_NOR_SMART_ERASE 2979 2980 /* SPI controller feature */ 2981 #undef CONFIG_SPI_CONTROLLER 2982 2983 /* SPI controller halfduplex/3-wire mode */ 2984 #undef CONFIG_SPI_HALFDUPLEX 2985 2986 /* SPI controller configure gpios on init */ 2987 #undef CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS 2988 2989 /* 2990 * Support SPI controller's without GPIO-specified Chip Selects, instead rely on 2991 * the SPI controller port's hardwired CS pin. 2992 */ 2993 #undef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS 2994 2995 /* Add support for hashing AP RO */ 2996 #undef CONFIG_SPI_HASH 2997 2998 /* Support testing SPI periph interface driver. */ 2999 #undef CONFIG_SPP_TEST 3000 3001 /* Default stack size to use for tasks, in bytes */ 3002 #undef CONFIG_STACK_SIZE 3003 3004 /* Use 32-bit timer for clock source on stm32. */ 3005 #undef CONFIG_STM_HWTIMER32 3006 3007 /* Compile charger detect for STM32 */ 3008 #undef CONFIG_STM32_CHARGER_DETECT 3009 3010 /* Fake hibernate mode */ 3011 #undef CONFIG_STM32L_FAKE_HIBERNATE 3012 3013 /* 3014 * Compile common code to handle simple switch inputs such as the recovery 3015 * button input from the servo debug interface. 3016 */ 3017 #undef CONFIG_SWITCH 3018 3019 /* Support dedicated recovery signal from servo board */ 3020 #undef CONFIG_SWITCH_DEDICATED_RECOVERY 3021 3022 /* 3023 * System should remain unlocked even if write protect is enabled. 3024 * 3025 * NOTE: This should ONLY be defined during bringup, and should never be 3026 * defined on a shipping / released platform. 3027 * 3028 * When defined, CBI allows ectool to reprogram all the fields. Once undefined, 3029 * it refuses to change certain fields. (e.g. board version, OEM ID) 3030 */ 3031 #undef CONFIG_SYSTEM_UNLOCKED 3032 3033 /* 3034 * Device can be a tablet as well as a clamshell. 3035 */ 3036 #undef CONFIG_TABLET_MODE 3037 3038 /* 3039 * Add a virtual switch to indicate when we are in tablet mode. 3040 */ 3041 #undef CONFIG_TABLET_MODE_SWITCH 3042 3043 /* 3044 * Config to identify what devices use GMR sensor to detect tablet mode. If a 3045 * board selects this config, it also needs to provide GMR_TABLET_MODE_GPIO_L 3046 * and direct its interrupt to gmr_tablet_switch_isr. 3047 */ 3048 #undef CONFIG_GMR_TABLET_MODE 3049 3050 /* 3051 * Board provides board_sensor_at_360 method instead of GMR_TABLET_MODE_GPIO_L 3052 * as the means for determining the state of the flipped-360-degree mode. 3053 */ 3054 #undef CONFIG_GMR_TABLET_MODE_CUSTOM 3055 3056 /* 3057 * Add a virtual switch to indicate when detachable device has 3058 * base attached. 3059 */ 3060 #undef CONFIG_BASE_ATTACHED_SWITCH 3061 3062 /*****************************************************************************/ 3063 /* Task config */ 3064 3065 /* 3066 * List of enabled tasks in ascending priority order. This is normally 3067 * defined in each board's ec.tasklist file. 3068 * 3069 * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and 3070 * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, 3071 * where: 3072 * 'n' is the name of the task 3073 * 'r' is the main routine of the task 3074 * 'd' is an opaque parameter passed to the routine at startup 3075 * 's' is the stack size in bytes; must be a multiple of 8 3076 * 3077 * Some cores use TASK_ALWAYS(n, r, d, s, f), where: 3078 * 'f' is the bit flags for the platform specific information 3079 * - MIA_TASK_FLAG_USE_FPU : bit 0, task uses FPU H/W 3080 * 3081 * For USB PD tasks, IDs must be in consecutive order and correspond to 3082 * the port which they are for. See TASK_ID_TO_PD_PORT() macro. 3083 */ 3084 #undef CONFIG_TASK_LIST 3085 3086 /* 3087 * List of test tasks. Same format as CONFIG_TASK_LIST, but used to define 3088 * additional tasks for a unit test. Normally defined in 3089 * test/{testname}.tasklist. 3090 */ 3091 #undef CONFIG_TEST_TASK_LIST 3092 3093 /* 3094 * List of tasks used by CTS 3095 * 3096 * cts.tasklist contains tasks run only for CTS. These tasks are added to the 3097 * tasks registered in ec.tasklist with higher priority. 3098 * 3099 * If a CTS suite does not define its own cts.tasklist, the common list is used 3100 * (i.e. cts/cts.tasklist). 3101 */ 3102 #undef CONFIG_CTS_TASK_LIST 3103 3104 /* 3105 * Enable task profiling. 3106 * 3107 * Boards may #undef this to reduce image size and RAM usage. 3108 */ 3109 #define CONFIG_TASK_PROFILING 3110 3111 /*****************************************************************************/ 3112 /* Mock config */ 3113 3114 /* 3115 * List of mock implementations to pull into the build. 3116 * 3117 * This should contain a flat list of MOCK(the-mock-name) elements. 3118 * 3119 * This is defined in the following two files: 3120 * test/{testname}.mocklist 3121 * fuzz/{fuzzname}.mocklist 3122 */ 3123 #undef CONFIG_TEST_MOCK_LIST 3124 3125 /*****************************************************************************/ 3126 /* Temperature sensor config */ 3127 3128 /* Compile common code for temperature sensor support */ 3129 #undef CONFIG_TEMP_SENSOR 3130 3131 /* Support particular temperature sensor chips */ 3132 #undef CONFIG_TEMP_SENSOR_ADT7481 /* ADT 7481 sensor, on I2C bus */ 3133 #undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */ 3134 #undef CONFIG_TEMP_SENSOR_EC_ADC /* Thermistors on EC's own ADC */ 3135 #undef CONFIG_TEMP_SENSOR_G753 /* G753 sensor, on I2C bus */ 3136 #undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */ 3137 #undef CONFIG_TEMP_SENSOR_G782 /* G782 sensor, on I2C bus */ 3138 #undef CONFIG_TEMP_SENSOR_SB_TSI /* SB_TSI sensor, on I2C bus */ 3139 #undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */ 3140 #undef CONFIG_TEMP_SENSOR_TMP411 /* TI TMP411 sensor, on I2C bus */ 3141 #undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */ 3142 #undef CONFIG_TEMP_SENSOR_TMP468 /* TI TMP468 sensor, on I2C bus */ 3143 #undef CONFIG_TEMP_SENSOR_F75303 /* Fintek F75303 sensor, on I2C bus */ 3144 3145 /* Compile common code for thermistor support */ 3146 #undef CONFIG_THERMISTOR 3147 3148 /* Support particular thermistors */ 3149 #undef CONFIG_THERMISTOR_NCP15WB /* NCP15WB thermistor */ 3150 3151 /* 3152 * If defined, image includes lookup tables and helper functions that convert 3153 * thermistor ADC readings into degrees K based off of various circuit 3154 * configurations. 3155 */ 3156 #undef CONFIG_STEINHART_HART_3V0_22K6_47K_4050B 3157 #undef CONFIG_STEINHART_HART_3V3_13K7_47K_4050B 3158 #undef CONFIG_STEINHART_HART_3V3_51K1_47K_4050B 3159 #undef CONFIG_STEINHART_HART_6V0_51K1_47K_4050B 3160 #undef CONFIG_STEINHART_HART_3V3_30K9_47K_4050B 3161 3162 /* 3163 * If defined, active-high GPIO which indicates temperature sensor chips are 3164 * powered. If not defined, temperature sensors are assumed to be always 3165 * powered. 3166 */ 3167 #undef CONFIG_TEMP_SENSOR_POWER_GPIO 3168 3169 /* Compile common code for throttling the CPU based on the temp sensors */ 3170 #undef CONFIG_THROTTLE_AP 3171 3172 /* 3173 * Throttle the CPU when battery discharge current is too high. When 3174 * this feature is enabled, BAT_MAX_DISCHG_CURRENT must be defined in board.h. 3175 */ 3176 #undef CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT 3177 3178 /* 3179 * Throttle the CPU when battery voltage drops below a defined threshold 3180 * where the board still boots but some components don't function perfectly. 3181 * When this feature is enabled, BAT_LOW_VOLTAGE_THRESH must be defined in 3182 * board.h. 3183 */ 3184 #undef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE 3185 3186 /* 3187 * If defined, dptf is enabled to manage thermals. 3188 * 3189 * NOTE: This doesn't mean that thermal control is completely taken care by 3190 * DPTF. We have some hybrid solutions where the EC still manages the fans. 3191 */ 3192 #undef CONFIG_DPTF 3193 3194 /* 3195 * If defined, this indicates to the motion lid driver that the board does not 3196 * have any GMR sensor and hence DPTF profile selection is required to be done 3197 * based on lid angle. 3198 */ 3199 #undef CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR 3200 3201 /* 3202 * If defined, device supports multiple DPTF profiles depending upon device mode 3203 * e.g. clamshell v/s 360-degree flipped mode or base detached v/s attached 3204 * mode. 3205 * 3206 * This config can be used by any driver that does lid angle calculation or base 3207 * state detection to determine if different profile numbers need to be 3208 * indicated to the host. 3209 */ 3210 #undef CONFIG_DPTF_MULTI_PROFILE 3211 3212 /*****************************************************************************/ 3213 /* Touchpad config */ 3214 3215 /* Enable touchpad. (You must pick a driver from the options below.) */ 3216 #undef CONFIG_TOUCHPAD 3217 3218 /* Enable Elan driver */ 3219 #undef CONFIG_TOUCHPAD_ELAN 3220 3221 /* Enable Goodix GT7288 driver */ 3222 #undef CONFIG_TOUCHPAD_GT7288 3223 3224 /* Enable ST driver */ 3225 #undef CONFIG_TOUCHPAD_ST 3226 3227 /* Set I2C port and address (7-bit) */ 3228 #undef CONFIG_TOUCHPAD_I2C_PORT 3229 #undef CONFIG_TOUCHPAD_I2C_ADDR_FLAGS 3230 3231 /* 3232 * Enable touchpad FW update over USB update protocol, and define touchpad 3233 * virtual address and size. 3234 */ 3235 #undef CONFIG_TOUCHPAD_VIRTUAL_SIZE 3236 3237 /* 3238 * Include hashes of the touchpad FW in the EC image, passed as TOUCHPAD_FW 3239 * parameter to make command. 3240 */ 3241 #undef CONFIG_TOUCHPAD_HASH_FW 3242 3243 /*****************************************************************************/ 3244 /* TPM-like configuration */ 3245 3246 /* Speak the TPM SPI Hardware Protocol on the SPI peripheral interface */ 3247 #undef CONFIG_TPM_SPP 3248 /* Speak to the TPM 2.0 hardware protocol on the I2C periph interface */ 3249 #undef CONFIG_TPM_I2CP 3250 3251 /*****************************************************************************/ 3252 /* USART stream config */ 3253 #undef CONFIG_STREAM_USART 3254 3255 /* 3256 * Each USART stream can be individually enabled and accessible using the 3257 * stream interface provided in the usart_config struct. 3258 */ 3259 #undef CONFIG_STREAM_USART1 3260 #undef CONFIG_STREAM_USART2 3261 #undef CONFIG_STREAM_USART3 3262 #undef CONFIG_STREAM_USART4 3263 3264 /*****************************************************************************/ 3265 /* U2F config: second factor authentication */ 3266 #undef CONFIG_U2F 3267 3268 /*****************************************************************************/ 3269 /* USB stream config */ 3270 #undef CONFIG_STREAM_USB 3271 3272 /*****************************************************************************/ 3273 /* UART config */ 3274 3275 /* Baud rate for UARTs */ 3276 #define CONFIG_UART_BAUD_RATE 115200 3277 3278 /* Allow bit banging of a UARTs pins and bypassing the UART block. */ 3279 #undef CONFIG_UART_BITBANG 3280 3281 /* UART index (number) for EC console */ 3282 #undef CONFIG_UART_CONSOLE 3283 3284 /* UART index (number) for host UART, if present */ 3285 #undef CONFIG_UART_HOST 3286 3287 /* Use uart_input_filter() to filter UART input. See prototype in uart.h */ 3288 #undef CONFIG_UART_INPUT_FILTER 3289 3290 /* 3291 * UART receive buffer size in bytes. Must be a power of 2 for macros in 3292 * common/uart_buffering.c to work properly. Must be larger than 3293 * CONFIG_CONSOLE_INPUT_LINE_SIZE to copy and paste scripts. 3294 */ 3295 #define CONFIG_UART_RX_BUF_SIZE 128 3296 3297 /* Use DMA for UART input */ 3298 #undef CONFIG_UART_RX_DMA 3299 3300 /* 3301 * On some platforms, UART receive DMA can't trigger an interrupt when a single 3302 * character is received. Those platforms poll for characters every HOOK_TICK. 3303 * When a character is received, make this many additional checks between then 3304 * and the next HOOK_TICK, to increase responsiveness of the console to input. 3305 */ 3306 #define CONFIG_UART_RX_DMA_RECHECKS 5 3307 3308 /* 3309 * UART transmit buffer size in bytes. Must be a power of 2 for macros in 3310 * common/uart_buffering.c to work properly. 3311 */ 3312 #define CONFIG_UART_TX_BUF_SIZE 512 3313 3314 /* Use DMA for UART output */ 3315 #undef CONFIG_UART_TX_DMA 3316 3317 /* The DMA channel for UART. If not defined, default to UART1. */ 3318 #undef CONFIG_UART_TX_DMA_CH 3319 #undef CONFIG_UART_RX_DMA_CH 3320 3321 /* The DMA peripheral request signal for UART TX. STM32 only. */ 3322 #undef CONFIG_UART_TX_DMA_PH 3323 3324 /* The DMA channel mapping config for stm32f4. */ 3325 #undef CONFIG_UART_TX_REQ_CH 3326 #undef CONFIG_UART_RX_REQ_CH 3327 3328 /*****************************************************************************/ 3329 /* USB PD config */ 3330 3331 /* Include all USB Power Delivery modules */ 3332 #undef CONFIG_USB_POWER_DELIVERY 3333 3334 /* Support for USB PD alternate mode */ 3335 #undef CONFIG_USB_PD_ALT_MODE 3336 3337 /* Support for USB PD alternate mode of Downward Facing Port */ 3338 #undef CONFIG_USB_PD_ALT_MODE_DFP 3339 3340 /* Check if max voltage request is allowed before each request */ 3341 #undef CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED 3342 3343 /* Default state of PD communication disabled flag */ 3344 #undef CONFIG_USB_PD_COMM_DISABLED 3345 3346 /* 3347 * Do not enable PD communication in RO as a security measure. 3348 * We don't want to allow communication to outside world until 3349 * we jump to RW. This can by overridden with the removal of 3350 * the write protect screw to allow for easier testing. 3351 */ 3352 #undef CONFIG_USB_PD_COMM_LOCKED 3353 3354 /* Default USB data role when a USB PD debug accessory is seen */ 3355 #define CONFIG_USB_PD_DEBUG_DR PD_ROLE_DFP 3356 3357 /* 3358 * Define to have a fixed PD Task debug level. 3359 * Undef to allow runtime change via console command. 3360 */ 3361 #undef CONFIG_USB_PD_DEBUG_LEVEL 3362 3363 /* 3364 * Define if this board can enable VBUS discharge (eg. through a GPIO-controlled 3365 * discharge circuit, or through port controller registers) to discharge VBUS 3366 * rapidly on disconnect. Will be defined automatically when one of the below 3367 * options is defined. 3368 */ 3369 #undef CONFIG_USB_PD_DISCHARGE 3370 3371 /* Define if discharge circuit is EC GPIO-controlled. */ 3372 #undef CONFIG_USB_PD_DISCHARGE_GPIO 3373 3374 /* Define if discharge circuit is using PD discharge registers on TCPC. */ 3375 #undef CONFIG_USB_PD_DISCHARGE_TCPC 3376 3377 /* Define if discharge circuit is using PD discharge registers on PPC. */ 3378 #undef CONFIG_USB_PD_DISCHARGE_PPC 3379 3380 /* Define if this board can act as a dual-role PD port (source and sink) */ 3381 #undef CONFIG_USB_PD_DUAL_ROLE 3382 3383 /* Define if this board can used TCPC-controlled DRP toggle */ 3384 #undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE 3385 3386 /* Define to reduces VBUS droop caused by inrush current during charging */ 3387 #undef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT 3388 3389 /* Initial DRP / toggle policy */ 3390 #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_TOGGLE_OFF 3391 3392 /* 3393 * Define if VBUS source GPIOs (GPIO_USB_C*_5V_EN) are active-low (and named 3394 * (..._L) rather than default active-high. 3395 */ 3396 #undef CONFIG_USB_PD_5V_EN_ACTIVE_LOW 3397 3398 /* Ask charger if VBUS is enabled on a source port, instead of using GPIO */ 3399 #undef CONFIG_USB_PD_5V_CHARGER_CTRL 3400 3401 /* 3402 * If defined, use a custom function to determine if VBUS is enabled on a 3403 * source port. The custom function is board_is_sourcing_vbus(port). 3404 */ 3405 #undef CONFIG_USB_PD_5V_EN_CUSTOM 3406 3407 /* Dynamic USB PD source capability */ 3408 #undef CONFIG_USB_PD_DYNAMIC_SRC_CAP 3409 3410 /* Support USB PD flash. */ 3411 #undef CONFIG_USB_PD_FLASH 3412 3413 /* Check whether PD is the sole power source before flash erase operation */ 3414 #undef CONFIG_USB_PD_FLASH_ERASE_CHECK 3415 3416 /* Define if this board, operating as a sink, can give power back to a source */ 3417 #undef CONFIG_USB_PD_GIVE_BACK 3418 3419 /* Enable USB PD Rev3.0 features */ 3420 #undef CONFIG_USB_PD_REV30 3421 3422 /* Major and Minor ChromeOS specific PD device Hardware IDs. */ 3423 #undef CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR 3424 #undef CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 3425 3426 /* HW & SW version for alternate mode discover identity response (4bits each) */ 3427 #undef CONFIG_USB_PD_IDENTITY_HW_VERS 3428 #undef CONFIG_USB_PD_IDENTITY_SW_VERS 3429 3430 /* Define if using internal comparator for PD receive */ 3431 #undef CONFIG_USB_PD_INTERNAL_COMP 3432 3433 /* Record main PD events in a circular buffer */ 3434 #undef CONFIG_USB_PD_LOGGING 3435 3436 /* The size in bytes of the FIFO used for event logging */ 3437 #define CONFIG_EVENT_LOG_SIZE 512 3438 3439 /* Save power by waking up on VBUS rather than polling CC */ 3440 #define CONFIG_USB_PD_LOW_POWER 3441 3442 /* Allow chip to go into low power idle even when a PD device is attached */ 3443 #undef CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED 3444 3445 /* Number of USB PD ports */ 3446 #undef CONFIG_USB_PD_PORT_COUNT 3447 3448 /* Simple DFP, such as power adapter, will not send discovery VDM on connect */ 3449 #undef CONFIG_USB_PD_SIMPLE_DFP 3450 3451 /* Use comparator module for PD RX interrupt */ 3452 #define CONFIG_USB_PD_RX_COMP_IRQ 3453 3454 /* Use TCPC module (type-C port controller) */ 3455 #undef CONFIG_USB_PD_TCPC 3456 3457 /* Enable TCPC to enter low power mode */ 3458 #undef CONFIG_USB_PD_TCPC_LOW_POWER 3459 3460 /* Enable the encoding of msg SOP* in bits 31-28 of 32-bit msg header type */ 3461 #undef CONFIG_USB_PD_DECODE_SOP 3462 3463 /* 3464 * Track VBUS level in TCPC module. This will only be needed if we're acting 3465 * as an external TCPC. 3466 */ 3467 #undef CONFIG_USB_PD_TCPC_TRACK_VBUS 3468 3469 /* Enable runtime config the TCPC */ 3470 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG 3471 3472 /* 3473 * Choose one of the following TCPMs (type-C port manager) to manage TCPC. The 3474 * TCPM stub is used to make direct function calls to TCPC when TCPC is on 3475 * the same MCU. The TCPCI TCPM uses the standard TCPCI i2c interface to TCPC. 3476 */ 3477 #undef CONFIG_USB_PD_TCPM_STUB 3478 #undef CONFIG_USB_PD_TCPM_TCPCI 3479 #undef CONFIG_USB_PD_TCPM_FUSB302 3480 #undef CONFIG_USB_PD_TCPM_ITE83XX 3481 #undef CONFIG_USB_PD_TCPM_ANX3429 3482 #undef CONFIG_USB_PD_TCPM_ANX740X 3483 #undef CONFIG_USB_PD_TCPM_ANX741X 3484 #undef CONFIG_USB_PD_TCPM_ANX7447 3485 #undef CONFIG_USB_PD_TCPM_ANX7688 3486 #undef CONFIG_USB_PD_TCPM_NCT38XX 3487 #undef CONFIG_USB_PD_TCPM_PS8751 3488 #undef CONFIG_USB_PD_TCPM_PS8805 3489 #undef CONFIG_USB_PD_TCPM_MT6370 3490 #undef CONFIG_USB_PD_TCPM_TUSB422 3491 3492 /* 3493 * Type-C retimer mux configuration tends to be set on a specific 3494 * driver's need basis. After including the board/baseboard.h files 3495 * the drivers will be checked and if one of these are needed it will 3496 * automatically be included. This does not stop a board/basebord.h 3497 * configration from defining these as well. 3498 */ 3499 #undef CONFIG_USBC_MUX_RETIMER 3500 3501 /* 3502 * Type-C retimer drivers to be used. 3503 */ 3504 #undef CONFIG_USBC_RETIMER_INTEL_BB 3505 #undef CONFIG_USBC_RETIMER_PI3DPX1207 3506 3507 /* 3508 * Adds an EC console command to erase the ANX7447 OCM flash. 3509 * Note: this is intended to be a temporary option and 3510 * won't be needed when ANX7447 are put on boards with OCM already erased 3511 */ 3512 #undef CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND 3513 3514 /* 3515 * Use this config option to enable and internal pullup resistor on the AUX_N 3516 * and internal pulldown resistor on the AUX_P line. Only use this config 3517 * option if there are no external pu/pd resistors on these signals. This 3518 * configuration should be used to avoid noise issues on the DDI1_AUX_N & 3519 * DDI1_AUX_P signals (b/122873171) 3520 */ 3521 #undef CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD 3522 3523 /* 3524 * Use this option if the TCPC port controller supports the optional register 3525 * 18h CONFIG_STANDARD_OUTPUT to steer the high-speed muxes. 3526 */ 3527 #undef CONFIG_USB_PD_TCPM_MUX 3528 3529 /* 3530 * The TCPM must know whether VBUS is present in order to make proper state 3531 * transitions. In addition, charge_manager must know about VBUS presence in 3532 * order to make charging decisions. VBUS state can be determined by various 3533 * methods: 3534 * - Some TCPCs can detect and report the presence of VBUS. 3535 * - In some configurations, charger ICs can report the presence of VBUS. 3536 * - On some boards, dedicated VBUS interrupt pins are available. 3537 * - Some power path controllers (PPC) can report the presence of VBUS. 3538 * 3539 * Exactly one of these should be defined for all boards that run the PD 3540 * state machine. 3541 */ 3542 #undef CONFIG_USB_PD_VBUS_DETECT_TCPC 3543 #undef CONFIG_USB_PD_VBUS_DETECT_CHARGER 3544 #undef CONFIG_USB_PD_VBUS_DETECT_GPIO 3545 #undef CONFIG_USB_PD_VBUS_DETECT_PPC 3546 #undef CONFIG_USB_PD_VBUS_DETECT_NONE 3547 3548 /* Define if the there is a separate ADC channel for each USB-C Vbus voltage */ 3549 #undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT 3550 3551 /* Define if the there is no hardware to measure Vbus voltage */ 3552 #undef CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT 3553 3554 /* Define the type-c port controller I2C base address. */ 3555 #define CONFIG_TCPC_I2C_BASE_ADDR_FLAGS 0x4E 3556 3557 /* Use this option to enable Try.SRC mode for Dual Role devices */ 3558 #undef CONFIG_USB_PD_TRY_SRC 3559 3560 /* Set the default minimum battery percentage for Try.Src to be enabled */ 3561 #define CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC 1 3562 3563 /* 3564 * Set the minimum battery percentage to allow a PD port to send resets as a 3565 * sink (and risk a hard reset, losing Vbus). Note this may cause a high-power 3566 * charger to appear as only a low-power 15W charger until a reset is sent to 3567 * re-start PD negotiation. 3568 */ 3569 #undef CONFIG_USB_PD_RESET_MIN_BATT_SOC 3570 3571 /* Alternative configuration keeping only the TX part of PHY */ 3572 #undef CONFIG_USB_PD_TX_PHY_ONLY 3573 3574 /* Use DAC as reference for comparator at 850mV. */ 3575 #undef CONFIG_PD_USE_DAC_AS_REF 3576 3577 /* Type-C VCONN Powered Device */ 3578 #undef CONFIG_USB_TYPEC_VPD 3579 3580 /* Type-C Charge Through VCONN Powered Device */ 3581 #undef CONFIG_USB_TYPEC_CTVPD 3582 3583 /* Type-C DRP with Accessory and Try.SRC */ 3584 #undef CONFIG_USB_TYPEC_DRP_ACC_TRYSRC 3585 3586 /* Type-C Fast Role Swap */ 3587 #undef CONFIG_USB_TYPEC_PD_FAST_ROLE_SWAP 3588 3589 /* 3590 * USB Product ID. Each platform (e.g. baseboard set) should have a single 3591 * VID/PID combination. If there is a big enough change within a platform, 3592 * then we can differentiate USB topologies by varying the HW version field 3593 * in the Sink and Source Capabilities Extended messages. 3594 * 3595 * To reserve a new PID, use go/usb. 3596 */ 3597 #undef CONFIG_USB_PID 3598 3599 /* PPC needs to be informed of CC polarity */ 3600 #undef CONFIG_USBC_PPC_POLARITY 3601 3602 /* 3603 * Disable charging from Default(USB) Rp as a type-c supplier. If your device 3604 * can detect such a supplier by BC 1.2, define this to get more current 3605 * from a BC 1.2 supplier. 3606 */ 3607 #undef CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF 3608 3609 /* USB Type-C Power Path Controllers (PPC) */ 3610 #undef CONFIG_USBC_PPC_AOZ1380 3611 #undef CONFIG_USBC_PPC_NX20P3481 3612 #undef CONFIG_USBC_PPC_NX20P3483 3613 #undef CONFIG_USBC_PPC_SN5S330 3614 #undef CONFIG_USBC_PPC_SYV682X 3615 3616 /* PPC is capable of gating the SBU lines. */ 3617 #undef CONFIG_USBC_PPC_SBU 3618 3619 /* PPC is capable of providing VCONN */ 3620 #undef CONFIG_USBC_PPC_VCONN 3621 3622 /* PPC has level interrupts and has a dedicated interrupt pin to check */ 3623 #undef CONFIG_USBC_PPC_DEDICATED_INT 3624 3625 /* Support for USB type-c superspeed mux */ 3626 #undef CONFIG_USBC_SS_MUX 3627 3628 /* 3629 * Only configure USB type-c superspeed mux when DFP (for chipsets that 3630 * don't support being a UFP) 3631 */ 3632 #undef CONFIG_USBC_SS_MUX_DFP_ONLY 3633 3634 /* Support v1.1 type-C connection state machine */ 3635 #undef CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP 3636 3637 /* Support for USB type-c vconn. Not needed for captive cables. */ 3638 #undef CONFIG_USBC_VCONN 3639 3640 /* Support VCONN swap */ 3641 #undef CONFIG_USBC_VCONN_SWAP 3642 3643 /* USB Binary device Object Store support */ 3644 #undef CONFIG_USB_BOS 3645 3646 /* USB Device version of product */ 3647 #undef CONFIG_USB_BCD_DEV 3648 3649 /* 3650 * Used during generation of VIF for USB Type-C Compliance Testing. 3651 * Indicates whether the UUT can communicate with USB 2.0 or USB 3.1 as a host 3652 * or as the Downstream Facing Port of a hub. 3653 */ 3654 #undef CONFIG_VIF_TYPE_C_CAN_ACT_AS_HOST 3655 3656 /* 3657 * Used during generation of VIF for USB Type-C Compliance Testing. 3658 * Indicates whether the UUT has a captive cable. 3659 */ 3660 #undef CONFIG_VIF_CAPTIVE_CABLE 3661 3662 /*****************************************************************************/ 3663 3664 /* Compile chip support for the USB device controller */ 3665 #undef CONFIG_USB 3666 3667 /* Support USB isochronous handler */ 3668 #undef CONFIG_USB_ISOCHRONOUS 3669 3670 /* Support USB blob handler. */ 3671 #undef CONFIG_USB_BLOB 3672 3673 /* Common USB / BC1.2 charger detection routines */ 3674 #undef CONFIG_USB_CHARGER 3675 3676 /* 3677 * Used for bc1.2 chips that need to be triggered from data role swaps instead 3678 * of just VBUS changes. 3679 */ 3680 #undef CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER 3681 3682 /* External BC1.2 charger detection devices. */ 3683 #undef CONFIG_BC12_DETECT_MAX14637 3684 #undef CONFIG_BC12_DETECT_PI3USB9201 3685 #undef CONFIG_BC12_DETECT_PI3USB9281 3686 /* Number of Pericom PI3USB9281 chips present in system */ 3687 #undef CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 3688 3689 /* Enable USB serial console module. */ 3690 #undef CONFIG_USB_CONSOLE 3691 3692 /* Require explicit enable call vs. active at time zero. */ 3693 #undef CONFIG_USB_CONSOLE_DEFAULT_DISABLED 3694 3695 /* 3696 * Enable USB serial console module using usb stream config. 3697 * NOTE: CONFIG_USB_CONSOLE and CONFIG_USB_CONSOLE_STREAM should be defined 3698 * exclusively each other. 3699 */ 3700 #undef CONFIG_USB_CONSOLE_STREAM 3701 3702 /* USB serial console transmit buffer size in bytes. */ 3703 #define CONFIG_USB_CONSOLE_TX_BUF_SIZE 2048 3704 3705 /* 3706 * Enable USB serial console crc32 computation. 3707 * Also makes console output block on overrun. 3708 */ 3709 #undef CONFIG_USB_CONSOLE_CRC 3710 3711 /* Support USB HID interface. */ 3712 #undef CONFIG_USB_HID 3713 3714 /* Support USB HID touchpad interface. */ 3715 #undef CONFIG_USB_HID_TOUCHPAD 3716 3717 /* HID touchpad logical dimensions */ 3718 #undef CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3719 #undef CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 3720 #undef CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 3721 /* HID touchpad physical dimensions (tenth of mm) */ 3722 #undef CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 3723 #undef CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 3724 3725 /* USB device buffers and descriptors */ 3726 #undef CONFIG_USB_RAM_ACCESS_SIZE 3727 #undef CONFIG_USB_RAM_ACCESS_TYPE 3728 #undef CONFIG_USB_RAM_BASE 3729 #undef CONFIG_USB_RAM_SIZE 3730 3731 /* Disable automatic connection of USB peripheral */ 3732 #undef CONFIG_USB_INHIBIT_CONNECT 3733 3734 /* Disable automatic initialization of USB peripheral */ 3735 #undef CONFIG_USB_INHIBIT_INIT 3736 3737 /* Support control of multiple PHY */ 3738 #undef CONFIG_USB_SELECT_PHY 3739 /* Select which USB PHY will be used at startup */ 3740 #undef CONFIG_USB_SELECT_PHY_DEFAULT 3741 3742 /* Support simple control of power to the device's USB ports */ 3743 #undef CONFIG_USB_PORT_POWER_DUMB 3744 3745 /* 3746 * Support smart power control to the device's USB ports, using 3747 * dedicated power control chips. This potentially enables automatic 3748 * negotiation of supplying more power to peripherals. 3749 */ 3750 #undef CONFIG_USB_PORT_POWER_SMART 3751 3752 /* 3753 * Support smart power control to the device's USB ports, however only CDP and 3754 * SDP are supported. Usually this is the case if all the control lines to the 3755 * charging port controller are hard-wired. 3756 */ 3757 #undef CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY 3758 3759 /* 3760 * Override the default charging mode for USB smart power control. 3761 * Value is selected from usb_charge_mode in include/usb_charge.h 3762 */ 3763 #undef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE 3764 3765 /* 3766 * Smart USB power control can use a full set of control signals to the USB 3767 * port power chip, or a reduced set. If this is defined, use the reduced set. 3768 */ 3769 #undef CONFIG_USB_PORT_POWER_SMART_SIMPLE 3770 3771 /* Number of smart USB power ports. */ 3772 #define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 2 3773 3774 /* 3775 * Smart USB power control current limit pins may be inverted. In this case 3776 * they are active low and the GPIO names will be GPIO_USBn_ILIM_SEL_L. 3777 */ 3778 #undef CONFIG_USB_PORT_POWER_SMART_INVERTED 3779 3780 /* 3781 * Support waking up host by setting the K-state on the data lines (requires 3782 * CONFIG_USB_SUSPEND to be set as well). 3783 */ 3784 #undef CONFIG_USB_REMOTE_WAKEUP 3785 3786 /* Support programmable USB device iSerial field. */ 3787 #undef CONFIG_USB_SERIALNO 3788 3789 /* Support reporting of configuration bMaxPower in mA */ 3790 #define CONFIG_USB_MAXPOWER_MA 500 3791 3792 /* Support reporting as self powered in USB configuration. */ 3793 #undef CONFIG_USB_SELF_POWERED 3794 3795 /* Support correct handling of USB suspend (host-initiated). */ 3796 #undef CONFIG_USB_SUSPEND 3797 3798 /* Default pull-up value on the USB-C ports when they are used as source. */ 3799 #define CONFIG_USB_PD_PULLUP TYPEC_RP_1A5 3800 /* 3801 * Override the pull-up value when only zero or one port is actively sourcing 3802 * current and we can advertise more current than what is defined by 3803 * `CONFIG_USB_PD_PULLUP`. 3804 * Should be defined with one of the tcpc_rp_value. 3805 */ 3806 #undef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT 3807 3808 /* 3809 * Total current in mA the board can supply to external devices through 3810 * USB-C ports 3811 * 3812 * When a sink device is plugged or unplugged, source current redistribution 3813 * occurs. If this macro is defined, redistribution occurs in such a way 3814 * that there is no current drop (e.g. 3A -> 1.5A) on active source ports. 3815 */ 3816 #undef CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT 3817 3818 /******************************************************************************/ 3819 /* stm32f4 dwc usb configs. */ 3820 3821 /* Set USB speed to FS rather than HS */ 3822 #undef CONFIG_USB_DWC_FS 3823 3824 /******************************************************************************/ 3825 /* USB port switch */ 3826 3827 /* Support the AMD FP5 USB/DP Mux */ 3828 #undef CONFIG_USB_MUX_AMD_FP5 3829 3830 /* Support the ITE IT5205 Type-C USB alternate mode mux. */ 3831 #undef CONFIG_USB_MUX_IT5205 3832 3833 /* Support the Pericom PI3USB30532 USB3.0/DP1.2 Matrix Switch */ 3834 #undef CONFIG_USB_MUX_PI3USB30532 3835 3836 /* Support the Parade PS8740 Type-C Redriving Switch */ 3837 #undef CONFIG_USB_MUX_PS8740 3838 3839 /* Support the Parade PS8743 Type-C Redriving Switch */ 3840 #undef CONFIG_USB_MUX_PS8743 3841 3842 /* 'Virtual' USB mux under host (not EC) control */ 3843 #undef CONFIG_USB_MUX_VIRTUAL 3844 3845 /*****************************************************************************/ 3846 /* USB GPIO config */ 3847 #undef CONFIG_USB_GPIO 3848 3849 /*****************************************************************************/ 3850 /* USB SPI legacy protocol (V1). */ 3851 #undef CONFIG_USB_SPI 3852 /* USB_SPI protocol V2. */ 3853 #undef CONFIG_USB_SPI_V2 3854 3855 /*****************************************************************************/ 3856 /* USB I2C config */ 3857 #undef CONFIG_USB_I2C 3858 3859 /* Allowed read/write count for USB over I2C */ 3860 #define CONFIG_USB_I2C_MAX_WRITE_COUNT 60 3861 #define CONFIG_USB_I2C_MAX_READ_COUNT 60 3862 3863 /*****************************************************************************/ 3864 /* USB Power monitoring interface config */ 3865 #undef CONFIG_USB_POWER 3866 3867 /*****************************************************************************/ 3868 /* 3869 * USB stream signing config. This allows data read over UART or SPI 3870 * to have a signature generated that can be used to validate the data 3871 * offline based on H1's registered key. Used by mn50. 3872 */ 3873 #undef CONFIG_STREAM_SIGNATURE 3874 3875 /*****************************************************************************/ 3876 3877 /* Support computing hash of code for verified boot */ 3878 #undef CONFIG_VBOOT_HASH 3879 3880 /* Support for secure temporary storage for verified boot */ 3881 #undef CONFIG_VSTORE 3882 3883 /* Number of supported slots for secure temporary storage */ 3884 #undef CONFIG_VSTORE_SLOT_COUNT 3885 3886 /*****************************************************************************/ 3887 /* Watchdog config */ 3888 3889 /* 3890 * Compile watchdog timer support. The watchdog timer will reboot the system 3891 * if the hook task (which is the lowest-priority task on the system) gets 3892 * starved for CPU time and isn't able to fire its HOOK_TICK event. 3893 */ 3894 #define CONFIG_WATCHDOG 3895 3896 /* 3897 * Try to detect a watchdog that is about to fire, and print a trace. This is 3898 * required on chips such as STM32 where the watchdog timer simply reboots the 3899 * system without any early warning. 3900 */ 3901 #undef CONFIG_WATCHDOG_HELP 3902 3903 /* 3904 * The maximum number of times that the watchdog timer may reset 3905 * before halting the system (or taking some sort of other 3906 * chip-dependent corrective action). 3907 */ 3908 #define CONFIG_WATCHDOG_MAX_RETRIES 4 3909 3910 /* Watchdog period in ms; see also AUX_TIMER_PERIOD_MS */ 3911 #define CONFIG_WATCHDOG_PERIOD_MS 1600 3912 3913 /* 3914 * Fire auxiliary timer 500ms before watchdog timer expires. This leaves 3915 * some time for debug trace to be printed. 3916 */ 3917 #define CONFIG_AUX_TIMER_PERIOD_MS (CONFIG_WATCHDOG_PERIOD_MS - 500) 3918 3919 /*****************************************************************************/ 3920 /* WebUSB config */ 3921 3922 /* 3923 * Enable the WebUSB support and define its URL. 3924 * Export a WebUSB Platform Descriptor in the Binary Object Store descriptor. 3925 * The WebUSB landing page URL is equal to 'CONFIG_WEBUSB_URL' plus the 3926 * https:// prefix. 3927 * This requires CONFIG_USB_BOS. 3928 */ 3929 #undef CONFIG_WEBUSB_URL 3930 3931 /*****************************************************************************/ 3932 3933 /* 3934 * Support controlling power to WiFi, WWAN (3G/LTE), and/or bluetooth modules. 3935 */ 3936 #undef CONFIG_WIRELESS 3937 3938 /* 3939 * Support for WiFi devices that must remain powered in suspend. Set to the 3940 * combination of EC_WIRELESS_SWITCH flags (from ec_commands.h) which should 3941 * be set in suspend. 3942 */ 3943 #undef CONFIG_WIRELESS_SUSPEND 3944 3945 /* WiFi power control signal is active-low. */ 3946 #undef CONFIG_WLAN_POWER_ACTIVE_LOW 3947 3948 /* Support Wake-on-Voice */ 3949 #undef CONFIG_WAKE_ON_VOICE 3950 3951 /* 3952 * Write protect signal is active-high. If this is defined, there must be a 3953 * GPIO named GPIO_WP; if not defined, there must be a GPIO names GPIO_WP_L. 3954 */ 3955 #undef CONFIG_WP_ACTIVE_HIGH 3956 3957 /* 3958 * The write protect signal is always asserted, 3959 * independently of the GPIO existence or current value. 3960 */ 3961 #undef CONFIG_WP_ALWAYS 3962 3963 /* 3964 * If needed to allocate some free space in the base of the RO or RW section 3965 * of the image, define these to be equal the required size of the free space. 3966 */ 3967 #undef CONFIG_RO_HEAD_ROOM 3968 #undef CONFIG_RW_HEAD_ROOM 3969 3970 /* Firmware upgrade options. */ 3971 /* Firmware updates using other than HC channel(s). */ 3972 #undef CONFIG_NON_HC_FW_UPDATE 3973 #undef CONFIG_USB_FW_UPDATE 3974 3975 /* PDU size for fw update over USB (or TPM). */ 3976 #define CONFIG_UPDATE_PDU_SIZE 1024 3977 3978 /* 3979 * If defined, charge_get_state returns a special status if battery is 3980 * discharging and battery is nearly full. 3981 */ 3982 #undef CONFIG_PWR_STATE_DISCHARGE_FULL 3983 3984 /* 3985 * Define this if a chip needs to add some information to the common 'version' 3986 * command output. 3987 */ 3988 #undef CONFIG_EXTENDED_VERSION_INFO 3989 3990 /* 3991 * Define this if board ID support is required. For g chip based boards it 3992 * allows to nail different images to different boards. 3993 */ 3994 #undef CONFIG_BOARD_ID_SUPPORT 3995 3996 /* 3997 * Define this if serial number support is required. For g chip based boards 3998 * it allows a verifiable serial number to be stored / certified. 3999 */ 4000 #undef CONFIG_SN_BITS_SUPPORT 4001 4002 /* 4003 * Define this to enable Cros Board Info support. I2C_EEPROM_PORT and 4004 * I2C_EEPROM_ADDR must be defined as well. 4005 */ 4006 #undef CONFIG_CROS_BOARD_INFO 4007 4008 /*****************************************************************************/ 4009 /* 4010 * ISH config defaults 4011 */ 4012 /* 4013 * This will be automatically defined below if the board supports power 4014 * modes that will require the AONTASK functionality. 4015 */ 4016 #undef CONFIG_ISH_PM_AONTASK 4017 4018 /* 4019 * Define the following if the power state support is required. 4020 */ 4021 #undef CONFIG_ISH_PM_D0I1 4022 #undef CONFIG_ISH_PM_D0I2 4023 #undef CONFIG_ISH_PM_D0I3 4024 #undef CONFIG_ISH_PM_D3 4025 4026 /* 4027 * Define the following to the number of uSeconds of elapsed time that is 4028 * required to enter D0I2 and D0I3, if they are supported 4029 */ 4030 #undef CONFIG_ISH_D0I2_MIN_USEC 4031 #undef CONFIG_ISH_D0I3_MIN_USEC 4032 4033 /* 4034 * Define the following in order to perform power management reset 4035 * prep IRQ setup when entering a new state 4036 */ 4037 #undef CONFIG_ISH_PM_RESET_PREP 4038 4039 /* 4040 * Define the following if combined ISR is required for ipc communication 4041 * between host and ISH. 4042 */ 4043 #undef CONFIG_ISH_HOST2ISH_COMBINED_ISR 4044 4045 /* 4046 * Define the following if there is need to clear ISH fabric error. 4047 */ 4048 #undef CONFIG_ISH_CLEAR_FABRIC_ERRORS 4049 4050 /* 4051 * Define the following if the version of ISH uses Synopsys Designware uart. 4052 */ 4053 #undef CONFIG_ISH_DW_UART 4054 4055 /* 4056 * On Intel devices EC's USB-C port numbers may not be physically equal to 4057 * AP's USB3 & USB2 port number. Because there can be MAX 15 USB2 ports on 4058 * PCH and MAX 15 USB3 ports on SOC, based on the complexity of the physical 4059 * layout of the board, USB3 & USB2 port signals of AP are routed to respective 4060 * USB-C port of EC. Hence, to configure the Intel Virtual MUX, information of 4061 * USB3 and USB2 port numbers of the respective USB-C port is needed. 4062 */ 4063 #undef CONFIG_INTEL_VIRTUAL_MUX 4064 4065 /*****************************************************************************/ 4066 /* 4067 * Include board and core configs, since those hold the CONFIG_ constants for a 4068 * given configuration. This guarantees they get included everywhere, and 4069 * fixes a fairly common bug where we gate out code with #ifndef 4070 * CONFIG_SOMETHING and but forget to include both of these. 4071 * 4072 * Board is included after chip, so that chip defaults can be overridden on a 4073 * per-board basis as needed. 4074 */ 4075 #ifdef __CROS_EC_CONFIG_CHIP_H 4076 #error Include config.h instead of config_chip.h! 4077 #endif 4078 #ifdef __BOARD_H 4079 #error Include config.h instead of board.h! 4080 #endif 4081 4082 #include "config_chip.h" 4083 #include "board.h" 4084 4085 /* 4086 * Define CONFIG_HOST_ESPI_VW_POWER_SIGNAL if any power signals from the host 4087 * are configured as virtual wires. 4088 */ 4089 #if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) || \ 4090 defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S4) 4091 #define CONFIG_HOST_ESPI_VW_POWER_SIGNAL 4092 #endif 4093 4094 #if defined(CONFIG_HOST_ESPI_VW_POWER_SIGNAL) && !defined(CONFIG_HOSTCMD_ESPI) 4095 #error Must enable eSPI to enable virtual wires. 4096 #endif 4097 4098 /******************************************************************************/ 4099 /* 4100 * Automatically define CONFIG_HOSTCMD_X86 if either child option is defined. 4101 * Ensure LPC and eSPI are mutually exclusive 4102 */ 4103 #if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI) 4104 #define CONFIG_HOSTCMD_X86 4105 #endif 4106 4107 #if defined(CONFIG_HOSTCMD_LPC) && defined(CONFIG_HOSTCMD_ESPI) 4108 #error Must select only one type of host communication bus. 4109 #endif 4110 4111 #if defined(CONFIG_HOSTCMD_X86) && !defined(CONFIG_HOSTCMD_LPC) && \ 4112 !defined(CONFIG_HOSTCMD_ESPI) 4113 #error Must select one type of host communication bus. 4114 #endif 4115 4116 /******************************************************************************/ 4117 /* 4118 * Set default data ram size unless it's customized by the chip. 4119 */ 4120 #ifndef CONFIG_DATA_RAM_SIZE 4121 #define CONFIG_DATA_RAM_SIZE CONFIG_RAM_SIZE 4122 #endif 4123 4124 /* Automatic configuration of RAM banks **************************************/ 4125 /* Assume one RAM bank if not specified, auto-compute number of banks */ 4126 #ifndef CONFIG_RAM_BANK_SIZE 4127 #define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE 4128 #endif 4129 4130 #ifndef CONFIG_RAM_BANKS 4131 #define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE) 4132 #endif 4133 4134 /******************************************************************************/ 4135 /* 4136 * Set minimum shared memory size, unless it is defined in board file. 4137 */ 4138 #ifndef CONFIG_SHAREDMEM_MINIMUM_SIZE 4139 #ifdef CONFIG_COMMON_RUNTIME 4140 /* If RWSIG is used, we may need more space. */ 4141 #if defined(CONFIG_RWSIG) 4142 #define CONFIG_SHAREDMEM_MINIMUM_SIZE_RWSIG (CONFIG_RSA_KEY_SIZE / 8 * 3) 4143 #else 4144 #define CONFIG_SHAREDMEM_MINIMUM_SIZE_RWSIG 0 4145 #endif 4146 4147 /* 4148 * We can't use the "MAX" function here, as it is too smart and BUILD_ASSERT 4149 * calls do not allow it as parameter. BUILD_MAX below works for both compiler 4150 * and linker. 4151 */ 4152 #define BUILD_MAX(x, y) ((x) > (y) ? (x) : (y)) 4153 4154 /* Minimum: 1kb */ 4155 #define CONFIG_SHAREDMEM_MINIMUM_SIZE \ 4156 BUILD_MAX(1024, CONFIG_SHAREDMEM_MINIMUM_SIZE_RWSIG) 4157 #else /* !CONFIG_COMMON_RUNTIME */ 4158 /* Without common runtime, we do not have support for shared memory. */ 4159 #define CONFIG_SHAREDMEM_MINIMUM_SIZE 0 4160 #endif 4161 #endif /* !CONFIG_SHAREDMEM_MINIMUM_SIZE */ 4162 4163 /******************************************************************************/ 4164 /* 4165 * Disable the built-in console history if using the experimental console. 4166 * 4167 * The experimental console keeps its own session-persistent history which 4168 * survives EC reboot. It also requires CRC8 for command integrity. 4169 */ 4170 #ifdef CONFIG_EXPERIMENTAL_CONSOLE 4171 #undef CONFIG_CONSOLE_HISTORY 4172 #define CONFIG_CRC8 4173 #endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */ 4174 4175 /******************************************************************************/ 4176 /* 4177 * Thermal throttling AP must have temperature sensor enabled to get 4178 * the temperature readings. 4179 */ 4180 #if defined(CONFIG_THROTTLE_AP) && !defined(CONFIG_TEMP_SENSOR) 4181 #define CONFIG_TEMP_SENSOR 4182 #endif 4183 4184 /******************************************************************************/ 4185 /* 4186 * DPTF must have temperature sensor enabled to get the readings for 4187 * generating DPTF thresholds events. 4188 */ 4189 #if defined(CONFIG_DPTF) && !defined(CONFIG_TEMP_SENSOR) 4190 #define CONFIG_TEMP_SENSOR 4191 #endif 4192 4193 /******************************************************************************/ 4194 /* The Matrix Keyboard Protocol depends on MKBP events. */ 4195 #ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP 4196 #define CONFIG_MKBP_EVENT 4197 #endif 4198 4199 /******************************************************************************/ 4200 /* MKBP events delivery methods. */ 4201 #ifdef CONFIG_MKBP_EVENT 4202 #if !defined(CONFIG_MKBP_USE_CUSTOM) && \ 4203 !defined(CONFIG_MKBP_USE_HOST_EVENT) && \ 4204 !defined(CONFIG_MKBP_USE_GPIO) && \ 4205 !defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT) && \ 4206 !defined(CONFIG_MKBP_USE_HECI) 4207 #error Please define one of CONFIG_MKBP_USE_* macro. 4208 #endif 4209 4210 #if defined(CONFIG_MKBP_USE_CUSTOM) + defined(CONFIG_MKBP_USE_GPIO) + \ 4211 defined(CONFIG_MKBP_USE_HOST_EVENT) + \ 4212 defined(CONFIG_MKBP_USE_HOST_HECI) > \ 4213 1 4214 #error Must select only one type of MKBP event delivery method. 4215 #endif 4216 #endif /* CONFIG_MKBP_EVENT */ 4217 4218 /******************************************************************************/ 4219 /* Set generic orientation config if a specific orientation config is set. */ 4220 #if defined(CONFIG_KX022_ORIENTATION_SENSOR) || \ 4221 defined(CONFIG_BMI160_ORIENTATION_SENSOR) 4222 #ifndef CONFIG_ACCEL_FIFO 4223 #error CONFIG_ACCEL_FIFO must be defined to use hw orientation sensor support 4224 #endif 4225 #define CONFIG_ORIENTATION_SENSOR 4226 #endif 4227 4228 /*****************************************************************************/ 4229 /* Define CONFIG_BATTERY if board has a battery. */ 4230 #if defined(CONFIG_BATTERY_BQ20Z453) || defined(CONFIG_BATTERY_BQ27541) || \ 4231 defined(CONFIG_BATTERY_BQ27621) || defined(CONFIG_BATTERY_BQ4050) || \ 4232 defined(CONFIG_BATTERY_MAX17055) || defined(CONFIG_BATTERY_MM8013) || \ 4233 defined(CONFIG_BATTERY_SMART) 4234 #define CONFIG_BATTERY 4235 #endif 4236 4237 /*****************************************************************************/ 4238 /* Define CONFIG_USBC_PPC if board has a USB Type-C Power Path Controller. */ 4239 #if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3483) || \ 4240 defined(CONFIG_USBC_PPC_SN5S330) 4241 #define CONFIG_USBC_PPC 4242 #endif /* "has a PPC" */ 4243 4244 /* The TI SN5S330 supports VCONN and needs to be informed of CC polarity */ 4245 #if defined(CONFIG_USBC_PPC_SN5S330) 4246 #define CONFIG_USBC_PPC_POLARITY 4247 #define CONFIG_USBC_PPC_SBU 4248 #define CONFIG_USBC_PPC_VCONN 4249 #endif 4250 4251 /*****************************************************************************/ 4252 /* 4253 * Define CONFIG_USB_PD_VBUS_MEASURE_CHARGER if the charger on the board 4254 * supports VBUS measurement. 4255 */ 4256 #if defined(CONFIG_CHARGER_BD9995X) || defined(CONFIG_CHARGER_RT9466) || \ 4257 defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_MT6370) || \ 4258 defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_ISL9241) 4259 #define CONFIG_USB_PD_VBUS_MEASURE_CHARGER 4260 #endif 4261 4262 /*****************************************************************************/ 4263 /* 4264 * Define CONFIG_CHARGER_NARROW_VDC for chargers that use a Narrow VDC power 4265 * architecture. 4266 */ 4267 #if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) || \ 4268 defined(CONFIG_CHARGER_ISL9241) 4269 #define CONFIG_CHARGER_NARROW_VDC 4270 #endif 4271 4272 /*****************************************************************************/ 4273 /* 4274 * Define CONFIG_BUTTON_TRIGGERED_RECOVERY if a board has a dedicated recovery 4275 * button. 4276 */ 4277 #ifdef CONFIG_DEDICATED_RECOVERY_BUTTON 4278 #define CONFIG_BUTTON_TRIGGERED_RECOVERY 4279 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */ 4280 4281 #ifdef CONFIG_LED_PWM_COUNT 4282 #define CONFIG_LED_PWM 4283 #endif /* defined(CONFIG_LED_PWM_COUNT) */ 4284 4285 #ifdef CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY 4286 #define CONFIG_LED_PWM_CHARGE_STATE_ONLY 4287 #endif 4288 4289 /*****************************************************************************/ 4290 /* Define derived USB PD Discharge common path */ 4291 #if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \ 4292 defined(CONFIG_USB_PD_DISCHARGE_TCPC) || \ 4293 defined(CONFIG_USB_PD_DISCHARGE_PPC) 4294 #define CONFIG_USB_PD_DISCHARGE 4295 #endif 4296 4297 /*****************************************************************************/ 4298 /* Define derived thermistor common path */ 4299 #ifdef CONFIG_THERMISTOR_NCP15WB 4300 #define CONFIG_THERMISTOR 4301 #endif 4302 4303 /*****************************************************************************/ 4304 /* Define derived config options for BC1.2 detection */ 4305 #ifdef CONFIG_BC12_DETECT_PI3USB9201 4306 #define CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER 4307 #endif 4308 4309 /*****************************************************************************/ 4310 /* 4311 * Define derived config options for Retimer chips. There are 4312 * for convenience. Any retimer driver that also needs USBC MUX Retimers 4313 * will not have to include it in their own board/baseboard.h file. 4314 */ 4315 #if defined(CONFIG_USBC_RETIMER_INTEL_BB) || \ 4316 defined(CONFIG_USBC_RETIMER_PI3DPX1207) 4317 #define CONFIG_USBC_MUX_RETIMER 4318 #endif 4319 4320 /*****************************************************************************/ 4321 /* 4322 * Define CONFIG_LIBCRYPTOC if a board needs to read secret data from the 4323 * anti-rollback block. 4324 */ 4325 #ifdef CONFIG_ROLLBACK_SECRET_SIZE 4326 #define CONFIG_LIBCRYPTOC 4327 #endif 4328 4329 /*****************************************************************************/ 4330 /* 4331 * Handle task-dependent configs. 4332 * 4333 * This prevent sub-modules from being compiled when the task and parent module 4334 * are not present. 4335 */ 4336 4337 #ifndef HAS_TASK_CHIPSET 4338 #undef CONFIG_CHIPSET_APOLLOLAKE 4339 #undef CONFIG_CHIPSET_BRASWELL 4340 #undef CONFIG_CHIPSET_CANNONLAKE 4341 #undef CONFIG_CHIPSET_COMETLAKE 4342 #undef CONFIG_CHIPSET_GEMINILAKE 4343 #undef CONFIG_CHIPSET_ICELAKE 4344 #undef CONFIG_CHIPSET_MT817X 4345 #undef CONFIG_CHIPSET_MT8183 4346 #undef CONFIG_CHIPSET_RK3399 4347 #undef CONFIG_CHIPSET_RK3288 4348 #undef CONFIG_CHIPSET_SDM845 4349 #undef CONFIG_CHIPSET_SKYLAKE 4350 #undef CONFIG_CHIPSET_STONEY 4351 #undef CONFIG_CHIPSET_TIGERLAKE 4352 #undef CONFIG_POWER_COMMON 4353 #endif 4354 4355 /* 4356 * If a board has a chipset task, set the minimum charger power required for 4357 * powering on to 15W. This is also the highest power discovered over Type-C by 4358 * analog signaling. The EC normally does not communicate using USB PD when the 4359 * system is locked and in RO, so it would not be able to tell if higher power 4360 * is available. However, if a 15W charger is discovered, it's likely that the 4361 * charger does speak USB PD and we would be able to negotiate more power after 4362 * booting the AP and jumping to EC RW. 4363 * 4364 * If a board needs more or less power to power on, they can re-define this 4365 * value in their board.h file. 4366 */ 4367 #ifdef HAS_TASK_CHIPSET 4368 #ifndef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 4369 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15000 4370 #endif /* !defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) */ 4371 #endif /* defined(HAS_TASK_CHIPSET) */ 4372 4373 #ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 4374 #ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 4375 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \ 4376 (CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) 4377 #endif 4378 #endif 4379 4380 #ifndef CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON 4381 /* 4382 * The function of MEASURE_BATTERY_IMBALANCE and these variables is to prevent a 4383 * battery brownout when the management IC reports a state of charge that is 4384 * higher than CHARGER_MIN_BAT_PCT_FOR_POWER_ON, but an individual cell is lower 4385 * than the rest of the pack. The critical term is MAX_IMBALANCE_MV, which must 4386 * be small enough to ensure that the system can reliably boot even when the 4387 * battery total state of charge barely passes the 4388 * CHARGER_MIN_BAT_PCT_FOR_POWER_ON threshold. 4389 * 4390 * Lowering CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON below 4391 * CHARGER_MIN_BAT_PCT_FOR_POWER_ON disables this check. Raising it too high 4392 * may needlessly prevent boot when the lowest cell can still support the 4393 * system. 4394 * 4395 * As this term is lowered and BATTERY_MAX_IMBALANCE_MV is raised, the risk of 4396 * cell-undervoltage brownout during startup increases. Raising this term and 4397 * lowering MAX_IMBALANCE_MV increases the risk of poor UX when the user must 4398 * wait longer to turn on their device. 4399 */ 4400 #define CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON 5 4401 #endif 4402 4403 #ifndef CONFIG_BATTERY_MAX_IMBALANCE_MV 4404 /* 4405 * WAG. Imbalanced battery packs in this situation appear to have balanced 4406 * charge very quickly after beginning the charging cycle, since dV/dQ rapidly 4407 * decreases as the cell is charged out of deep discharge. Increasing the value 4408 * of CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON will make a system tolerant of 4409 * larger values of BATTERY_MAX_IMBALANCE_MV. 4410 */ 4411 #define CONFIG_BATTERY_MAX_IMBALANCE_MV 200 4412 #endif 4413 4414 #ifndef HAS_TASK_KEYPROTO 4415 #undef CONFIG_KEYBOARD_PROTOCOL_8042 4416 /* 4417 * Note that we don't undef CONFIG_KEYBOARD_PROTOCOL_MKBP, because it doesn't 4418 * have its own task. 4419 */ 4420 #endif 4421 4422 #ifndef HAS_TASK_PDCMD 4423 #undef CONFIG_HOSTCMD_PD 4424 #endif 4425 4426 /* Certain console cmds are irrelevant without parent modules. */ 4427 #ifndef CONFIG_BATTERY 4428 #undef CONFIG_CMD_PWR_AVG 4429 #endif 4430 4431 #ifndef CONFIG_ADC 4432 #undef CONFIG_CMD_ADC 4433 #endif 4434 4435 /*****************************************************************************/ 4436 /* Define derived Chipset configs */ 4437 #if defined(CONFIG_CHIPSET_APOLLOLAKE) || defined(CONFIG_CHIPSET_GEMINILAKE) 4438 #define CONFIG_CHIPSET_APL_GLK 4439 #endif 4440 4441 #if defined(CONFIG_CHIPSET_ICELAKE) || defined(CONFIG_CHIPSET_TIGERLAKE) 4442 #define CONFIG_CHIPSET_ICL_TGL 4443 #endif 4444 4445 #if defined(CONFIG_CHIPSET_APL_GLK) 4446 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK 4447 #endif 4448 4449 #if defined(CONFIG_CHIPSET_APOLLOLAKE) || defined(CONFIG_CHIPSET_BRASWELL) || \ 4450 defined(CONFIG_CHIPSET_CANNONLAKE) || \ 4451 defined(CONFIG_CHIPSET_COMETLAKE) || \ 4452 defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE) || \ 4453 defined(CONFIG_CHIPSET_GEMINILAKE) || \ 4454 defined(CONFIG_CHIPSET_ICELAKE) || defined(CONFIG_CHIPSET_SKYLAKE) || \ 4455 defined(CONFIG_CHIPSET_TIGERLAKE) 4456 #define CONFIG_POWER_COMMON 4457 #endif 4458 4459 #if defined(CONFIG_CHIPSET_CANNONLAKE) || defined(CONFIG_CHIPSET_ICELAKE) || \ 4460 defined(CONFIG_CHIPSET_SKYLAKE) || defined(CONFIG_CHIPSET_TIGERLAKE) 4461 #define CONFIG_CHIPSET_X86_RSMRST_DELAY 4462 #endif 4463 4464 /*****************************************************************************/ 4465 /* Define derived seven segment display common path */ 4466 #ifdef CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY 4467 #define CONFIG_SEVEN_SEG_DISPLAY 4468 #endif /* CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY */ 4469 4470 /* 4471 * Apply fuzzer and test config overrides last, since fuzzers and tests need to 4472 * override some of the config flags in non-standard ways to mock only parts of 4473 * the system. 4474 */ 4475 #include "fuzz_config.h" 4476 #include "test_config.h" 4477 4478 /* 4479 * Validity checks to make sure some of the configs above make sense. 4480 */ 4481 4482 #if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS) * 2) 4483 #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS" 4484 #endif 4485 4486 /* Enable BMI160 secondary port if needed. */ 4487 #if defined(CONFIG_MAG_BMI160_BMM150) || defined(CONFIG_MAG_BMI160_LIS2MDL) 4488 #define CONFIG_BMI160_SEC_I2C 4489 #endif 4490 4491 /* Load LIS2MDL driver if needed */ 4492 #if defined(CONFIG_MAG_BMI160_LIS2MDL) 4493 #define CONFIG_MAG_LIS2MDL 4494 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS 4495 #error "The i2c address of the magnetometer is not set." 4496 #endif 4497 #endif 4498 4499 /* Load BMM150 driver if needed */ 4500 #if defined(CONFIG_MAG_BMI160_BMM150) 4501 #define CONFIG_MAG_BMM150 4502 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS 4503 #error "The i2c address of the magnetometer is not set." 4504 #endif 4505 #endif 4506 4507 /* Fill LPC sense data on X86 architecture. */ 4508 #ifdef CONFIG_HOSTCMD_X86 4509 #define CONFIG_MOTION_FILL_LPC_SENSE_DATA 4510 #endif 4511 4512 /* 4513 * TODO(crbug.com/888109): Makes sure RDP as PSTATE is only enabled where it 4514 * makes sense. 4515 */ 4516 #ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE 4517 #ifdef CONFIG_FLASH_PSTATE 4518 #error "Flash readout protection and PSTATE may not work as intended." 4519 #endif 4520 4521 #if !defined(CHIP_FAMILY_STM32H7) && !defined(CHIP_FAMILY_STM32F4) 4522 #error "Flash readout protection only implemented on STM32H7 and STM32F4." 4523 #endif 4524 #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ 4525 4526 #if defined(CONFIG_USB_PD_TCPM_ANX3429) || \ 4527 defined(CONFIG_USB_PD_TCPM_ANX740X) || \ 4528 defined(CONFIG_USB_PD_TCPM_ANX7471) 4529 /* Note: ANX7447 is handled by its own driver, not ANX74XX. */ 4530 #define CONFIG_USB_PD_TCPM_ANX74XX 4531 #endif 4532 4533 #if defined(CONFIG_DPTF_MULTI_PROFILE) && !defined(CONFIG_DPTF) 4534 #error "CONFIG_DPTF_MULTI_PROFILE can be set only when CONFIG_DPTF is set." 4535 #endif /* CONFIG_DPTF_MULTI_PROFILE && !CONFIG_DPTF */ 4536 4537 /* 4538 * Define the timeout in milliseconds between when the EC receives a suspend 4539 * command and when the EC times out and asserts wake because the sleep signal 4540 * SLP_S0 did not assert. 4541 */ 4542 #ifndef CONFIG_SLEEP_TIMEOUT_MS 4543 #define CONFIG_SLEEP_TIMEOUT_MS 10000 4544 #endif 4545 4546 #ifdef CONFIG_PWM_KBLIGHT 4547 #define CONFIG_KEYBOARD_BACKLIGHT 4548 #endif 4549 4550 /*****************************************************************************/ 4551 /* ISH power management related definitions */ 4552 #if defined(CONFIG_ISH_PM_D0I2) || defined(CONFIG_ISH_PM_D0I3) || \ 4553 defined(CONFIG_ISH_PM_D3) || defined(CONFIG_ISH_PM_RESET_PREP) 4554 4555 #ifndef CONFIG_LOW_POWER_IDLE 4556 #error "Must define CONFIG_LOW_POWER_IDLE if enable ISH low power states" 4557 #endif 4558 4559 #define CONFIG_ISH_PM_AONTASK 4560 4561 #endif 4562 4563 #ifdef CONFIG_ACCEL_FIFO 4564 #if !defined(CONFIG_ACCEL_FIFO_SIZE) || !defined(CONFIG_ACCEL_FIFO_THRES) 4565 #error "Using CONFIG_ACCEL_FIFO, must define _SIZE and _THRES" 4566 #endif 4567 #endif /* CONFIG_ACCEL_FIFO */ 4568 4569 /* 4570 * If USB PD Discharge is enabled, verify that CONFIG_USB_PD_DISCHARGE_GPIO 4571 * and CONFIG_USB_PD_PORT_COUNT, CONFIG_USB_PD_DISCHARGE_TCPC, or 4572 * CONFIG_USB_PD_DISCHARGE_PPC is defined. 4573 */ 4574 #ifdef CONFIG_USB_PD_DISCHARGE 4575 #ifdef CONFIG_USB_PD_DISCHARGE_GPIO 4576 #if !defined(CONFIG_USB_PD_PORT_COUNT) 4577 #error "PD discharge port not defined" 4578 #endif 4579 #else 4580 #if !defined(CONFIG_USB_PD_DISCHARGE_TCPC) && \ 4581 !defined(CONFIG_USB_PD_DISCHARGE_PPC) 4582 #error "PD discharge implementation not defined" 4583 #endif 4584 #endif /* CONFIG_USB_PD_DISCHARGE_GPIO */ 4585 #endif /* CONFIG_USB_PD_DISCHARGE */ 4586 4587 /* EC Codec Wake-on-Voice related definitions */ 4588 #ifdef CONFIG_AUDIO_CODEC_WOV 4589 #define CONFIG_SHA256 4590 #endif 4591 4592 #ifdef CONFIG_SMBUS_PEC 4593 #define CONFIG_CRC8 4594 #endif 4595 4596 /* Don't run RSA 2048 known-answer test (+30 ms). */ 4597 #undef CONFIG_FIPS_RSA2048 4598 /* Don't run software HMAC_DRBG-SHA256 known-answer test (+30 ms). */ 4599 #undef CONFIG_FIPS_SW_HMAC_DRBG 4600 /* Don't run AES CBC 256 test (not used for U2F anymore). */ 4601 #undef CONFIG_FIPS_AES_CBC_256 4602 /* Don't use ECDSA pair-wise consistency test. We verify sign/verify. */ 4603 #undef CONFIG_FIPS_ECDSA_PWCT 4604 4605 #endif /* __CROS_EC_CONFIG_H */ 4606