xref: /aosp_15_r20/external/gmmlib/Source/GmmLib/ULT/GmmGen9ResourceULT.h (revision 35ffd701415c9e32e53136d61a677a8d0a8fc4a5)
1 /*==============================================================================
2 Copyright(c) 2017 Intel Corporation
3 
4 Permission is hereby granted, free of charge, to any person obtaining a
5 copy of this software and associated documentation files(the "Software"),
6 to deal in the Software without restriction, including without limitation
7 the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 and / or sell copies of the Software, and to permit persons to whom the
9 Software is furnished to do so, subject to the following conditions:
10 
11 The above copyright notice and this permission notice shall be included
12 in all copies or substantial portions of the Software.
13 
14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 OTHER DEALINGS IN THE SOFTWARE.
21 ============================================================================*/
22 
23 #pragma once
24 
25 #include "GmmResourceULT.h"
26 
27 class CTestGen9Resource : public CTestResource
28 {
29 protected:
30     void                FillExpectedPitch();
31     void                FillExpectedPitchInTiles();
32     void                FillExpectedHAlign();
33     void                FillExpectedVAlign();
34     void                FillExpectedDAlign();
35     void                FillExpectedSize();
36     void                FillExpectedQPitch();
37 
38     void                FillExpectedMipOffsets();
39 
40 public:
41     static void SetUpTestCase();
42     static void TearDownTestCase();
43 
44     /////////////////////////////////////////////////////////////////////////////////////
45     /// Get the Tile dimension and RT->CCS downscale factor
46     ///
47     /// @param[in]  Bpp: bits per pixel
48     /// @param[in]  Tiling: Tile Type
49     /// @param[in]  ResType: Resource Type
50     /// @param[out] TileDimX: Tile Width for given Tile, Resource, bpp
51     /// @param[out] TileDimY: Tile Height for given Tile, Resource, bpp
52     /// @param[out] TileDimZ: Tile Depth for given Tile, Resource, bpp
53     /// @param[out] WidthDivisor: RT->CCS width downscale factor
54     /// @param[out] HeightDivisor: RT->CCS height downscale factor
55     ///
56     /////////////////////////////////////////////////////////////////////////////////////
GetAlignmentAndTileDimensionsForCCS(TEST_BPP Bpp,TEST_TILE_TYPE Tiling,TEST_RESOURCE_TYPE ResType,uint32_t & TileDimX,uint32_t & TileDimY,uint32_t & TileDimZ,uint32_t & WidthDivisor,uint32_t & HeightDivisor)57     void GetAlignmentAndTileDimensionsForCCS(TEST_BPP Bpp, TEST_TILE_TYPE Tiling, TEST_RESOURCE_TYPE ResType,
58                                         uint32_t &TileDimX, uint32_t &TileDimY, uint32_t & TileDimZ,
59                                         uint32_t &WidthDivisor, uint32_t &HeightDivisor)
60     {
61         const uint32_t RT2DTileSize[TEST_TILE_MAX][TEST_BPP_MAX][3] = {
62             { { 64, 1, 1 },{ 64, 1, 1 },{ 64, 1, 1 },{ 64, 1, 1 },{ 64, 1, 1 } },                  //Linear - no Tile Size, but min PitchAlign = 64 (cacheLine size)
63             { { 512, 8, 1 },{ 512, 8,1 },{ 512, 8,1 },{ 512, 8, 1 },{ 512, 8, 1 } },                //TileX
64             { { 128, 32, 1 },{ 128, 32, 1 },{ 128, 32, 1 },{ 128, 32, 1 },{ 128, 32, 1 } },        //TileY
65             { { 256, 256, 1 },{ 512, 128, 1 },{ 512, 128, 1 },{ 1024, 64, 1 },{ 1024, 64, 1 } },   //TileYs
66             { { 64, 64, 1 },{ 128, 32, 1 },{ 128, 32,1 },{ 256, 16, 1 },{ 256, 16, 1 } }           //TileYf
67         };
68 
69         const uint32_t RT3DTileSize[TEST_TILE_MAX][TEST_BPP_MAX][3] = {
70             { { 64, 1, 1 },{ 64, 1, 1 },{ 64, 1, 1 },{ 64, 1, 1 },{ 64, 1, 1 } },                 //Linear - no Tile Size, but min PitchAlign = 64 (cacheLine size)
71             { { 512, 8, 1 },{ 512, 8, 1 },{ 512, 8, 1 },{ 512, 8, 1 },{ 512, 8, 1 } },            //TileX
72             { { 128, 32, 1 },{ 128, 32, 1 },{ 128, 32, 1 },{ 128, 32, 1 },{ 128, 32, 1 } },       //TileY
73             { { 64, 32, 32 },{ 64, 32, 32 },{ 128, 32, 16 },{ 256, 16, 16 },{ 512, 16, 16 } },    //TileYs
74             { { 16, 16, 16 },{ 16, 16, 16 },{ 32, 16, 8 },{ 64, 8, 8 },{ 64, 8, 8 } }             //TileYf
75         };
76         uint32_t TileDim[3] = { RT2DTileSize[Tiling][Bpp][0], RT2DTileSize[Tiling][Bpp][1], RT2DTileSize[Tiling][Bpp][2] };
77         if (ResType == TEST_RESOURCE_3D)
78         {
79             TileDim[0] = RT3DTileSize[Tiling][Bpp][0];
80             TileDim[1] = RT3DTileSize[Tiling][Bpp][1];
81             TileDim[2] = RT3DTileSize[Tiling][Bpp][2];
82         }
83         TileDimX = TileDim[0];
84         TileDimY = TileDim[1];
85         TileDimZ = TileDim[2];
86 
87         uint32_t ExpectedCCSBpp = 1;              //1 byte per pixel (contains 4 2b-CCS,
88                                                //Each 2b covers 2CLs = 128B RT)
89         /***
90         2b-CCS  per 2CLs of RT (2:1 compression ie 2CL->1CL)
91         1B-CCS covers 4x2 RT CLs (as square as possible in px)
92 
93         CL Byte size 16 x 4
94         8CLs could cover {(16x32), (128x4), (64x8), (32x16)} Byte-blocks, of which last one is most-square hence should be used
95         ie RT coverage by 1B CCS is 32x16, taking RT-bpp into account:
96 
97         bpp         RT-coverage in pixel by 1B CCS
98         32         32/4  x 16 = 8x16
99         64         32/8  x 16 = 4x16
100         128        32/16 x 16 = 2x16
101 
102         Finally CCS needs to be Tile-aligned (TileY)
103         ***/
104         const uint32_t RTWidthDivisor[2][TEST_BPP_MAX] = { { 1, 1, 16, 8, 4 },{ 1, 1, 8, 4, 2 } }; //Divisor for TileX, TileY
105         const uint32_t RTHeightDivisor[2] = { 8, 16 };
106         uint32_t Idx = (Tiling == TEST_TILEX) ? 0 : 1;
107 
108         WidthDivisor = RTWidthDivisor[Idx][Bpp];
109         HeightDivisor = RTHeightDivisor[Idx];
110     }
111 
112     /////////////////////////////////////////////////////////////////////////////////////
113     /// Verifies if Mip tail start Lod matches the expected value. Fails test if value
114     /// doesn't match
115     ///
116     /// @param[in]  ResourceInfo: ResourceInfo returned by GmmLib
117     /// @param[in]  ExpectedValue: expected value to check against
118     /////////////////////////////////////////////////////////////////////////////////////
119     template <bool Verify>
VerifyResourceMipTailStartLod(GMM_RESOURCE_INFO * ResourceInfo,uint32_t ExpectedValue)120     void VerifyResourceMipTailStartLod(GMM_RESOURCE_INFO *ResourceInfo, uint32_t ExpectedValue)
121     {
122         if (Verify)
123         {
124             EXPECT_EQ(ExpectedValue, ResourceInfo->GetMipTailStartLodSurfaceState());
125         }
126     }
127 
128     CTestGen9Resource();
129     ~CTestGen9Resource();
130 };
131 
132