1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <stdlib.h>
18 #include "flash.h"
19 #include "programmer.h"
20 #include "hwaccess_x86_io.h"
21 #include "platform/pci.h"
22
23 #define PCI_VENDOR_ID_REALTEK 0x10ec
24 #define PCI_VENDOR_ID_SMC1211 0x1113
25
26 struct nicrealtek_data {
27 uint32_t io_base_addr;
28 int bios_rom_addr;
29 int bios_rom_data;
30 };
31
32 static const struct dev_entry nics_realtek[] = {
33 {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
34 {0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
35 {0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
36
37 {0},
38 };
39
nicrealtek_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)40 static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
41 {
42 struct nicrealtek_data *data = flash->mst->par.data;
43
44 /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
45 * enable software access.
46 */
47 OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
48 data->io_base_addr + data->bios_rom_addr);
49 /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
50 * enable software access.
51 */
52 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
53 data->io_base_addr + data->bios_rom_addr);
54 }
55
nicrealtek_chip_readb(const struct flashctx * flash,const chipaddr addr)56 static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
57 {
58 struct nicrealtek_data *data = flash->mst->par.data;
59 uint8_t val;
60
61 /* FIXME: Can we skip reading the old data and simply use 0? */
62 /* Read old data. */
63 val = INB(data->io_base_addr + data->bios_rom_data);
64 /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
65 * enable software access.
66 */
67 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
68 data->io_base_addr + data->bios_rom_addr);
69
70 /* Read new data. */
71 val = INB(data->io_base_addr + data->bios_rom_data);
72 /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
73 * enable software access.
74 */
75 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
76 data->io_base_addr + data->bios_rom_addr);
77
78 return val;
79 }
80
nicrealtek_shutdown(void * data)81 static int nicrealtek_shutdown(void *data)
82 {
83 /* FIXME: We forgot to disable software access again. */
84 free(data);
85 return 0;
86 }
87
88 static const struct par_master par_master_nicrealtek = {
89 .chip_readb = nicrealtek_chip_readb,
90 .chip_writeb = nicrealtek_chip_writeb,
91 .shutdown = nicrealtek_shutdown,
92 };
93
nicrealtek_init(const struct programmer_cfg * cfg)94 static int nicrealtek_init(const struct programmer_cfg *cfg)
95 {
96 struct pci_dev *dev = NULL;
97 uint32_t io_base_addr = 0;
98 int bios_rom_addr;
99 int bios_rom_data;
100
101 if (rget_io_perms())
102 return 1;
103
104 dev = pcidev_init(cfg, nics_realtek, PCI_BASE_ADDRESS_0);
105 if (!dev)
106 return 1;
107
108 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
109 if (!io_base_addr)
110 return 1;
111
112 /* Beware, this ignores the vendor ID! */
113 switch (dev->device_id) {
114 case 0x8139: /* RTL8139 */
115 case 0x1211: /* SMC 1211TX */
116 default:
117 bios_rom_addr = 0xD4;
118 bios_rom_data = 0xD7;
119 break;
120 case 0x8169: /* RTL8169 */
121 bios_rom_addr = 0x30;
122 bios_rom_data = 0x33;
123 break;
124 }
125
126 struct nicrealtek_data *data = calloc(1, sizeof(*data));
127 if (!data) {
128 msg_perr("Unable to allocate space for PAR master data\n");
129 return 1;
130 }
131 data->io_base_addr = io_base_addr;
132 data->bios_rom_addr = bios_rom_addr;
133 data->bios_rom_data = bios_rom_data;
134
135 return register_par_master(&par_master_nicrealtek, BUS_PARALLEL, data);
136 }
137
138 const struct programmer_entry programmer_nicrealtek = {
139 .name = "nicrealtek",
140 .type = PCI,
141 .devs.dev = nics_realtek,
142 .init = nicrealtek_init,
143 };
144