1 /* 2 * This file is part of the flashrom project. 3 * 4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> 5 * Copyright (c) 2011 Stefan Tauner 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #ifndef __ICH_DESCRIPTORS_H__ 19 #define __ICH_DESCRIPTORS_H__ 1 20 21 #include <sys/types.h> 22 #include <stdint.h> 23 #include <stdbool.h> 24 #include "programmer.h" /* for enum ich_chipset */ 25 26 /* FIXME: Replace with generic return codes */ 27 #define ICH_RET_OK 0 28 #define ICH_RET_ERR -1 29 #define ICH_RET_WARN -2 30 #define ICH_RET_PARAM -3 31 #define ICH_RET_OOB -4 32 33 #define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ 34 #define PCH100_REG_FDOC 0xB4 /* New offset from Sunrise Point on */ 35 /* 0-1: reserved */ 36 #define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ 37 #define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) 38 #define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ 39 #define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) 40 /* 15-31: reserved */ 41 42 #define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ 43 #define PCH100_REG_FDOD 0xB8 /* New offset from Sunrise Point on */ 44 45 /* Field locations and semantics for LVSCC, UVSCC and related words in the flash 46 * descriptor are equal therefore they all share the same macros below. */ 47 #define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ 48 #define VSCC_BES (0x3 << VSCC_BES_OFF) 49 #define VSCC_WG_OFF 2 /* 2: Write Granularity */ 50 #define VSCC_WG (0x1 << VSCC_WG_OFF) 51 #define VSCC_WSR_OFF 3 /* 3: Write Status Required */ 52 #define VSCC_WSR (0x1 << VSCC_WSR_OFF) 53 #define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ 54 #define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) 55 /* 5-7: reserved */ 56 #define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ 57 #define VSCC_EO (0xff << VSCC_EO_OFF) 58 /* 16-22: reserved */ 59 #define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ 60 #define VSCC_VCL (0x1 << VSCC_VCL_OFF) 61 /* 24-31: reserved */ 62 63 #define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x07fff000) 64 #define ICH_FREG_LIMIT(flreg) ((((flreg) >> 4) & 0x07fff000) | 0x00000fff) 65 66 void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl); 67 68 struct ich_desc_content { 69 uint32_t FLVALSIG; /* 0x00 */ 70 union { /* 0x04 */ 71 uint32_t FLMAP0; 72 struct { 73 uint32_t FCBA :8, /* Flash Component Base Address */ 74 NC :2, /* Number Of Components */ 75 :6, 76 FRBA :8, /* Flash Region Base Address */ 77 NR :3, /* Number Of Regions (reserved from Skylake on) */ 78 :5; 79 }; 80 }; 81 union { /* 0x08 */ 82 uint32_t FLMAP1; 83 struct { 84 uint32_t FMBA :8, /* Flash Master Base Address */ 85 NM :3, /* Number Of Masters */ 86 :5, 87 FISBA :8, /* Flash ICH Strap Base Address */ 88 ISL :8; /* ICH Strap Length */ 89 }; 90 }; 91 union { /* 0x0c */ 92 uint32_t FLMAP2; 93 struct { 94 uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ 95 MSL :8, /* MCH Strap Length */ 96 ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */ 97 RIL :8; /* Register Init Length (new since Hawell) */ 98 }; 99 struct { /* new since Tiger Point */ 100 uint32_t :2, 101 CSSO :10, /* CPU Soft Strap Offset from PMC Base */ 102 :4, 103 CSSL :8, /* CPU Soft Strap Length */ 104 :8; 105 }; 106 }; 107 }; 108 109 struct ich_desc_component { 110 union { /* 0x00 */ 111 uint32_t FLCOMP; /* Flash Components Register */ 112 /* FLCOMP encoding on various generations: 113 * 114 * Chipset/Generation max_speed dual_output density 115 * [MHz] bits max. bits 116 * ICH8: 33 N/A 5 0:2, 3:5 117 * ICH9: 33 N/A 5 0:2, 3:5 118 * ICH10: 33 N/A 5 0:2, 3:5 119 * Ibex Peak/5: 50 N/A 5 0:2, 3:5 120 * Cougar Point/6: 50 30 5 0:2, 3:5 121 * Patsburg: 50 30 5 0:2, 3:5 122 * Panther Point/7 50 30 5 0:2, 3:5 123 * Lynx Point/8: 50 30 7 0:3, 4:7 124 * Wildcat Point/9: 50 30 (multi I/O) 7 0:3, 4:7 125 * Sunrise Point/100: 48 30 7 0:3, 4:7 126 */ 127 struct { 128 uint32_t :17, 129 freq_read :3, 130 fastread :1, 131 freq_fastread :3, 132 freq_write :3, 133 freq_read_id :3, 134 dual_output :1, /* new since Cougar Point/6 */ 135 :1; 136 } modes; 137 struct { 138 uint32_t comp1_density :3, 139 comp2_density :3, 140 :26; 141 } dens_old; 142 struct { 143 uint32_t comp1_density :4, /* new since Lynx Point/8 */ 144 comp2_density :4, 145 :24; 146 } dens_new; 147 }; 148 union { /* 0x04 */ 149 uint32_t FLILL; /* Flash Invalid Instructions Register */ 150 struct { 151 uint32_t invalid_instr0 :8, 152 invalid_instr1 :8, 153 invalid_instr2 :8, 154 invalid_instr3 :8; 155 }; 156 }; 157 union { /* 0x08 */ 158 uint32_t FLPB; /* Flash Partition Boundary Register, until Panther Point/7 */ 159 struct { 160 uint32_t FPBA :13, /* Flash Partition Boundary Addr */ 161 :19; 162 }; 163 uint32_t FLILL1; /* Flash Invalid Instructions Register, new since Sunrise Point/100 */ 164 struct { 165 uint32_t invalid_instr4 :8, 166 invalid_instr5 :8, 167 invalid_instr6 :8, 168 invalid_instr7 :8; 169 }; 170 }; 171 }; 172 173 #define MAX_NUM_FLREGS 16 174 struct ich_desc_region { 175 /* 176 * Number of entries and width differ on various generations: 177 * 178 * Chipset/Generation #FLREGs width (bits) 179 * ICH8 .. Panther Point/7 5 13 180 * Lynx Point/8 .. Wildcat Point/9 7 15 181 * Sunrise Point/100 .. 200 Series 10 15 182 * Lewisburg/100 .. 16 15 183 * Cannon Point/300 .. 16 15 184 */ 185 union { 186 uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */ 187 188 /* only used for bit-field check */ 189 struct { 190 uint32_t base :13, 191 :3, 192 limit :13, 193 :3; 194 } old_reg[MAX_NUM_FLREGS]; 195 }; 196 }; 197 198 #define MAX_NUM_MASTERS 6 /* 5 prior to C620/Lewisburg PCH */ 199 struct ich_desc_master { 200 union { 201 uint32_t FLMSTRs[MAX_NUM_MASTERS]; /* Flash Masters */ 202 /* For pre-Skylake platforms */ 203 struct { 204 uint32_t BIOS_req_ID :16, 205 BIOS_descr_r :1, 206 BIOS_BIOS_r :1, 207 BIOS_ME_r :1, 208 BIOS_GbE_r :1, 209 BIOS_plat_r :1, 210 :3, 211 BIOS_descr_w :1, 212 BIOS_BIOS_w :1, 213 BIOS_ME_w :1, 214 BIOS_GbE_w :1, 215 BIOS_plat_w :1, 216 :3; 217 uint32_t ME_req_ID :16, 218 ME_descr_r :1, 219 ME_BIOS_r :1, 220 ME_ME_r :1, 221 ME_GbE_r :1, 222 ME_plat_r :1, 223 :3, 224 ME_descr_w :1, 225 ME_BIOS_w :1, 226 ME_ME_w :1, 227 ME_GbE_w :1, 228 ME_plat_w :1, 229 :3; 230 uint32_t GbE_req_ID :16, 231 GbE_descr_r :1, 232 GbE_BIOS_r :1, 233 GbE_ME_r :1, 234 GbE_GbE_r :1, 235 GbE_plat_r :1, 236 :3, 237 GbE_descr_w :1, 238 GbE_BIOS_w :1, 239 GbE_ME_w :1, 240 GbE_GbE_w :1, 241 GbE_plat_w :1, 242 :3; 243 }; 244 /* From Skylake on */ 245 struct { 246 uint32_t ext_read :4, 247 ext_write :4, 248 read :12, 249 write :12; 250 } mstr[MAX_NUM_MASTERS]; 251 }; 252 }; 253 254 struct ich_desc_north_strap { 255 union { 256 uint32_t STRPs[1]; /* current maximum: ich8 */ 257 struct { /* ich8 */ 258 struct { /* STRP2 (in the datasheet) */ 259 uint32_t MDB :1, 260 :31; 261 }; 262 } ich8; 263 }; 264 }; 265 266 struct ich_desc_south_strap { 267 union { 268 uint32_t STRPs[23]; /* current maximum: gemini lake */ 269 struct { /* ich8 */ 270 struct { /* STRP1 */ 271 uint32_t ME_DISABLE :1, 272 :6, 273 TCOMODE :1, 274 ASD :7, 275 BMCMODE :1, 276 :3, 277 GLAN_PCIE_SEL :1, 278 GPIO12_SEL :2, 279 SPICS1_LANPHYPC_SEL :1, 280 MESM2SEL :1, 281 :1, 282 ASD2 :7; 283 }; 284 } ich8; 285 struct { /* ibex peak */ 286 struct { /* STRP0 */ 287 uint32_t :1, 288 cs_ss2 :1, 289 :5, 290 SMB_EN :1, 291 SML0_EN :1, 292 SML1_EN :1, 293 SML1FRQ :2, 294 SMB0FRQ :2, 295 SML0FRQ :2, 296 :4, 297 LANPHYPC_GP12_SEL :1, 298 cs_ss1 :1, 299 :2, 300 DMI_REQID_DIS :1, 301 :4, 302 BBBS :2, 303 :1; 304 }; 305 struct { /* STRP1 */ 306 uint32_t cs_ss3 :4, 307 :28; 308 }; 309 struct { /* STRP2 */ 310 uint32_t :8, 311 MESMASDEN :1, 312 MESMASDA :7, 313 :8, 314 MESMI2CEN :1, 315 MESMI2CA :7; 316 }; 317 struct { /* STRP3 */ 318 uint32_t :32; 319 }; 320 struct { /* STRP4 */ 321 uint32_t PHYCON :2, 322 :6, 323 GBEMAC_SMBUS_ADDR_EN :1, 324 GBEMAC_SMBUS_ADDR :7, 325 :1, 326 GBEPHY_SMBUS_ADDR :7, 327 :8; 328 }; 329 struct { /* STRP5 */ 330 uint32_t :32; 331 }; 332 struct { /* STRP6 */ 333 uint32_t :32; 334 }; 335 struct { /* STRP7 */ 336 uint32_t MESMA2UDID_VENDOR :16, 337 MESMA2UDID_DEVICE :16; 338 }; 339 struct { /* STRP8 */ 340 uint32_t :32; 341 }; 342 struct { /* STRP9 */ 343 uint32_t PCIEPCS1 :2, 344 PCIEPCS2 :2, 345 PCIELR1 :1, 346 PCIELR2 :1, 347 DMILR :1, 348 :1, 349 PHY_PCIEPORTSEL :3, 350 PHY_PCIE_EN :1, 351 :20; 352 }; 353 struct { /* STRP10 */ 354 uint32_t :1, 355 ME_BOOT_FLASH :1, 356 cs_ss5 :1, 357 VE_EN :1, 358 :4, 359 MMDDE :1, 360 MMADDR :7, 361 cs_ss7 :1, 362 :1, 363 ICC_SEL :3, 364 MER_CL1 :1, 365 :10; 366 }; 367 struct { /* STRP11 */ 368 uint32_t SML1GPAEN :1, 369 SML1GPA :7, 370 :16, 371 SML1I2CAEN :1, 372 SML1I2CA :7; 373 }; 374 struct { /* STRP12 */ 375 uint32_t :32; 376 }; 377 struct { /* STRP13 */ 378 uint32_t :32; 379 }; 380 struct { /* STRP14 */ 381 uint32_t :8, 382 VE_EN2 :1, 383 :5, 384 VE_BOOT_FLASH :1, 385 :1, 386 BW_SSD :1, 387 NVMHCI_EN :1, 388 :14; 389 }; 390 struct { /* STRP15 */ 391 uint32_t :3, 392 cs_ss6 :2, 393 :1, 394 IWL_EN :1, 395 :1, 396 t209min :2, 397 :22; 398 }; 399 } ibex; 400 struct { /* cougar point */ 401 struct { /* STRP0 */ 402 uint32_t :1, 403 cs_ss1 :1, 404 :5, 405 SMB_EN :1, 406 SML0_EN :1, 407 SML1_EN :1, 408 SML1FRQ :2, 409 SMB0FRQ :2, 410 SML0FRQ :2, 411 :4, 412 LANPHYPC_GP12_SEL :1, 413 LINKSEC_DIS :1, 414 :2, 415 DMI_REQID_DIS :1, 416 :4, 417 BBBS :2, 418 :1; 419 }; 420 struct { /* STRP1 */ 421 uint32_t cs_ss3 :4, 422 :4, 423 cs_ss2 :1, 424 :28; 425 }; 426 struct { /* STRP2 */ 427 uint32_t :8, 428 MESMASDEN :1, 429 MESMASDA :7, 430 MESMMCTPAEN :1, 431 MESMMCTPA :7, 432 MESMI2CEN :1, 433 MESMI2CA :7; 434 }; 435 struct { /* STRP3 */ 436 uint32_t :32; 437 }; 438 struct { /* STRP4 */ 439 uint32_t PHYCON :2, 440 :6, 441 GBEMAC_SMBUS_ADDR_EN :1, 442 GBEMAC_SMBUS_ADDR :7, 443 :1, 444 GBEPHY_SMBUS_ADDR :7, 445 :8; 446 }; 447 struct { /* STRP5 */ 448 uint32_t :32; 449 }; 450 struct { /* STRP6 */ 451 uint32_t :32; 452 }; 453 struct { /* STRP7 */ 454 uint32_t MESMA2UDID_VENDOR :16, 455 MESMA2UDID_DEVICE :16; 456 }; 457 struct { /* STRP8 */ 458 uint32_t :32; 459 }; 460 struct { /* STRP9 */ 461 uint32_t PCIEPCS1 :2, 462 PCIEPCS2 :2, 463 PCIELR1 :1, 464 PCIELR2 :1, 465 DMILR :1, 466 cs_ss4 :1, 467 PHY_PCIEPORTSEL :3, 468 PHY_PCIE_EN :1, 469 :2, 470 SUB_DECODE_EN :1, 471 :7, 472 PCHHOT_SML1ALERT_SEL :1, 473 :9; 474 }; 475 struct { /* STRP10 */ 476 uint32_t :1, 477 ME_BOOT_FLASH :1, 478 :6, 479 MDSMBE_EN :1, 480 MDSMBE_ADD :7, 481 :2, 482 ICC_SEL :3, 483 MER_CL1 :1, 484 ICC_PRO_SEL :1, 485 Deep_SX_EN :1, 486 ME_DBG_LAN :1, 487 :7; 488 }; 489 struct { /* STRP11 */ 490 uint32_t SML1GPAEN :1, 491 SML1GPA :7, 492 :16, 493 SML1I2CAEN :1, 494 SML1I2CA :7; 495 }; 496 struct { /* STRP12 */ 497 uint32_t :32; 498 }; 499 struct { /* STRP13 */ 500 uint32_t :32; 501 }; 502 struct { /* STRP14 */ 503 uint32_t :32; 504 }; 505 struct { /* STRP15 */ 506 uint32_t cs_ss6 :6, 507 IWL_EN :1, 508 cs_ss5 :2, 509 :4, 510 SMLINK1_THERM_SEL :1, 511 SLP_LAN_GP29_SEL :1, 512 :16; 513 }; 514 struct { /* STRP16 */ 515 uint32_t :32; 516 }; 517 struct { /* STRP17 */ 518 uint32_t ICML :1, 519 cs_ss7 :1, 520 :30; 521 }; 522 } cougar; 523 }; 524 }; 525 526 struct ich_desc_upper_map { 527 union { 528 uint32_t FLUMAP1; /* Flash Upper Map 1 */ 529 struct { 530 uint32_t VTBA :8, /* ME VSCC Table Base Address */ 531 VTL :8, /* ME VSCC Table Length */ 532 :8, 533 MDTBA :8; /* MIP Descr. Table Base Addr. (new since Cannon Point/300) */ 534 }; 535 }; 536 struct { 537 union { /* JEDEC-ID Register */ 538 uint32_t JID; 539 struct { 540 uint32_t vid :8, /* Vendor ID */ 541 cid0 :8, /* Component ID 0 */ 542 cid1 :8, /* Component ID 1 */ 543 :8; 544 }; 545 }; 546 union { /* Vendor Specific Component Capabilities */ 547 uint32_t VSCC; 548 struct { 549 uint32_t ubes :2, /* Upper Block/Sector Erase Size */ 550 uwg :1, /* Upper Write Granularity */ 551 uwsr :1, /* Upper Write Status Required */ 552 uwews :1, /* Upper Write Enable on Write Status */ 553 :3, 554 ueo :8, /* Upper Erase Opcode */ 555 lbes :2, /* Lower Block/Sector Erase Size */ 556 lwg :1, /* Lower Write Granularity */ 557 lwsr :1, /* Lower Write Status Required */ 558 lwews :1, /* Lower Write Enable on Write Status */ 559 :3, 560 leo :16; /* Lower Erase Opcode */ 561 }; 562 }; 563 } vscc_table[128]; 564 }; 565 566 struct ich_descriptors { 567 struct ich_desc_content content; 568 struct ich_desc_component component; 569 struct ich_desc_region region; 570 struct ich_desc_master master; 571 struct ich_desc_north_strap north; 572 struct ich_desc_south_strap south; 573 struct ich_desc_upper_map upper; 574 }; 575 576 ssize_t ich_number_of_regions(enum ich_chipset cs, const struct ich_desc_content *content); 577 ssize_t ich_number_of_masters(enum ich_chipset cs, const struct ich_desc_content *content); 578 579 void prettyprint_ich_chipset(enum ich_chipset cs); 580 void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc); 581 582 void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *content); 583 void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc); 584 void prettyprint_ich_descriptor_region(enum ich_chipset cs, const struct ich_descriptors *desc); 585 void prettyprint_ich_descriptor_master(enum ich_chipset cs, const struct ich_descriptors *desc); 586 587 void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap); 588 void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc); 589 int read_ich_descriptors_from_dump(const uint32_t *dump, size_t len, enum ich_chipset *cs, struct ich_descriptors *desc); 590 591 int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc); 592 int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); 593 594 int layout_from_ich_descriptors(struct flashrom_layout **, const void *dump, size_t len); 595 596 #endif /* __ICH_DESCRIPTORS_H__ */ 597