1Manual page 2=========== 3 4 5NAME 6---- 7 8**flashrom** - detect, read, write, verify and erase flash chips 9 10 11SYNOPSIS 12-------- 13 14| **flashrom** [-h|-R|-L|-z| 15| -p <programmername>[:<parameters>] [-c <chipname>] 16| (--flash-name|--flash-size| 17| [-E|-x|-r <file>|-w <file>|-v <file>] 18| [(-l <file>|--ifd|--fmap|--fmap-file <file>) 19| [-i <include>[:<file>]]] 20| [--wp-status] [--wp-list] [--wp-enable|--wp-disable] 21| [--wp-range <start>,<length>|--wp-region <region>] 22| [-n] [-N] [-f])] 23| [-V[V[V]]] [-o <logfile>] [--progress] 24 25 26DESCRIPTION 27----------- 28 29**flashrom** is a utility for detecting, reading, writing, verifying and erasing flash chips. 30It's often used to flash BIOS/EFI/coreboot/firmware images in-system using a supported mainboard. 31However, it also supports various external PCI/USB/parallel-port/serial-port based devices which can program flash 32chips, including some network cards (NICs), SATA/IDE controller cards, graphics cards, the Bus Pirate device, 33various FTDI FT2232/FT4232H/FT4233H/FT232H based USB devices, and more. 34 35It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40, TSOP48, and BGA chips, 36which use various protocols such as LPC, FWH, parallel flash, or SPI. 37 38 39OPTIONS 40------- 41 42You can specify one of ``-h``, ``-R``, ``-L``, ``-z``, ``-E``, ``-r``, ``-w``, ``-v`` or no operation. 43If no operation is specified, **flashrom** will only probe for flash chips. It is recommended that if you try **flashrom** the 44first time on a system, you run it in probe-only mode and check the output. 45Also you are advised to make a backup of your current ROM contents with ``-r`` before you try to write a new image. 46All operations involving any chip access (probe/read/write/...) require the ``-p/--programmer`` option to be used (please see below). 47 48 49**-r, --read <file>** 50 Read flash ROM contents and save them into the given **<file>**. 51 If the file already exists, it will be overwritten. 52 53 54**-w, --write (<file>|-)** 55 Write **<file>** into flash ROM. If **-** is provided instead, contents will be read from stdin. 56 This will first automatically erase the chip, then write to it. 57 58 In the process the chip is also read several times. First an in-memory backup is made for disaster recovery and to be 59 able to skip regions that are already equal to the image file. 60 This copy is updated along with the write operation. In case of erase errors it is even re-read completely. 61 After writing has finished and if verification is enabled, the whole flash chip is read out and compared with the input image. 62 63 64**-n, --noverify** 65 Skip the automatic verification of flash ROM contents after writing. Using this option is **not** recommended, 66 you should only use it if you know what you are doing and if you feel that the time for verification takes too long. 67 68 Typical usage is:: 69 70 flashrom -p prog -n -w <file> 71 72 This option is only useful in combination with ``--write``. 73 74 75**-N, --noverify-all** 76 Skip not included regions during automatic verification after writing (cf. ``-l`` and ``-i``). 77 You should only use this option if you are sure that communication with the flash chip is reliable 78 (e.g. when using the **internal** programmer). 79 Even if **flashrom** is instructed not to touch parts of the flash chip, their contents could be damaged 80 (e.g. due to misunderstood erase commands). 81 82 This option is required to flash an Intel system with locked ME flash region using the **internal** programmer. 83 It may be enabled by default in this case in the future. 84 85 86**-v, --verify (<file>|-)** 87 Verify the flash ROM contents against the given **<file>**. 88 If **-** is provided instead, contents will be written to the stdout. 89 90 91**-E, --erase** 92 Erase the flash ROM chip. 93 94 95**-x, --extract** 96 Extract every region defined on the layout from flash ROM chip to a file with the same name as the extracted region 97 (replacing spaces with underscores). 98 99 100**-V, --verbose** 101 More verbose output. This option can be supplied multiple times (max. 3 times, i.e. ``-VVV`` ) for even more debug output. 102 103 104**-c, --chip <chipname>** 105 Probe only for the specified flash ROM chip. This option takes the chip name as printed by ``flashrom -L`` without the 106 vendor name as parameter. Please note that the chip name is case sensitive. 107 108 109**-f, --force** 110 Force one or more of the following actions: 111 112 * Force chip read and pretend the chip is there. 113 * Force chip access even if the chip is bigger than the maximum supported size for the flash bus. 114 * Force erase even if erase is known bad. 115 * Force write even if write is known bad. 116 117 118**-l, --layout <file>** 119 Read ROM layout from **<file>**. 120 121 **flashrom** supports ROM layouts. This allows you to flash certain parts of the flash chip only. 122 A ROM layout file contains multiple lines with the following syntax:: 123 124 startaddr:endaddr imagename 125 126 ``startaddr`` and ``endaddr`` are hexadecimal addresses within the ROM file and do not refer to any physical address. 127 Please note that using a 0x prefix for those hexadecimal numbers is not necessary, but you can't specify decimal/octal numbers. 128 ``imagename`` is an arbitrary name for the region/image from ``startaddr`` to ``endaddr`` (both addresses included). 129 130 Example:: 131 132 00000000:00008fff gfxrom 133 00009000:0003ffff normal 134 00040000:0007ffff fallback 135 136 If you only want to update the image named **normal** in a ROM based on the layout above, run:: 137 138 flashrom -p prog --layout rom.layout --image normal -w some.rom 139 140 To update only the images named **normal** and **fallback**, run:: 141 142 flashrom -p prog -l rom.layout -i normal -i fallback -w some.rom 143 144 Overlapping sections are not supported. 145 146 147**--fmap** 148 Read layout from fmap in flash chip. 149 150 **flashrom** supports the fmap binary format which is commonly used by coreboot for partitioning a flash chip. 151 The on-chip fmap will be read and used to generate the layout. 152 153 If you only want to update the **COREBOOT** region defined in the fmap, run:: 154 155 flashrom -p prog --fmap --image COREBOOT -w some.rom 156 157 158**--fmap-file <file>** 159 Read layout from a **<file>** containing binary fmap (e.g. coreboot roms). 160 161 **flashrom** supports the fmap binary format which is commonly used by coreboot for partitioning a flash chip. 162 The fmap in the specified file will be read and used to generate the layout. 163 164 If you only want to update the **COREBOOT** region defined in the binary fmap file, run:: 165 166 flashrom -p prog --fmap-file some.rom --image COREBOOT -w some.rom 167 168 169**--ifd** 170 Read ROM layout from Intel Firmware Descriptor. 171 172 **flashrom** supports ROM layouts given by an Intel Firmware Descriptor (IFD). 173 The on-chip descriptor will be read and used to generate the layout. If you need to change the layout, 174 you have to update the IFD only first. 175 176 The following ROM images may be present in an IFD: 177 178 | ``fd`` - the IFD itself 179 | ``bios`` - the host firmware aka. BIOS 180 | ``me`` - Intel Management Engine firmware 181 | ``gbe`` - gigabit ethernet firmware 182 | ``pd`` - platform specific data 183 184 185**-i, --include <region>[:<file>]** 186 Read or write only **<region>** to or from ROM. 187 The **-i** option may be used multiple times if the user wishes to read or write multiple regions using a single command. 188 189 The user may optionally specify a corresponding **<file>** for any region they wish to read or write. 190 A read operation will read the corresponding regions from ROM and write individual files for each one. 191 A write option will read file(s) and write to the corresponding region(s) in ROM. 192 193 For write operations, files specified using ``-i`` take precedence over content from the argument to ``-w``. 194 195 Examples: 196 To read regions named **foo** and **bar** in layout file **<layout>** into region-sized files **foo.bin** and **bar.bin**, run:: 197 198 flashrom -p prog -l <layout> -i foo:foo.bin -i bar:bar.bin -r rom.bin 199 200 To write files **foo.bin** and **bar.bin** into regions named **foo** and **bar** in layout file **<layout>** to the ROM, run:: 201 202 flashrom -p prog -l <layout> -i foo:foo.bin -i bar:bar.bin -w rom.bin 203 204 205**--wp-status** 206 Prints the flash's current status register protection mode and write protection range. 207 208 209**--wp-list** 210 Prints a list of all protection ranges that the flash supports. 211 212 213**--wp-enable** 214 Enables hardware status register protection (SRP) if the flash supports it. 215 Once SRP is enabled, operations that change the flash's status registers (including ``--wp-disable`` and ``--wp-range``) 216 can only be performed if the flash's #WP pin is at an inactive logic level. 217 218 219**--wp-disable** 220 Disables status register protection if the flash allows it. 221 222 223**--wp-range <start>,<length>** 224 Configures the flash to protect a range of addresses from <start> to (<start> + <length> - 1), bounds inclusive. 225 The range must be supported by the flash, see ``--wp-list``. 226 227 228**--wp-region <region>** 229 Same as ``--wp-range`` but protects the range occupied by an image region. 230 This option requires a image layout to be specified, see ``--layout``. 231 The region must be supported by the flash, see ``--wp-list``. 232 233 234**--flash-name** 235 Prints out the detected flash chip's name. 236 237 238**--flash-size** 239 Prints out the detected flash chip's size. 240 241 242**--flash-contents <ref-file>** 243 The file contents of **<ref-file>** will be used to decide which parts of the flash need to be written. 244 Providing this saves an initial read of the full flash chip. 245 Be careful, if the provided data doesn't actually match the flash contents, results are undefined. 246 247 248**-L, --list-supported** 249 List the flash chips, chipsets, mainboards, and external programmers (including PCI, USB, parallel port, and serial port based devices) 250 supported by **flashrom**. 251 252 There are many unlisted boards which will work out of the box, without special support in **flashrom**. 253 Please let us know if you can verify that other boards work or do not work out of the box. 254 255 **IMPORTANT**: 256 For verification you have to test an ERASE and/or WRITE operation, so make sure you only do that if you have proper means to recover from failure! 257 258 259**-z, --list-supported-wiki** 260 Same as ``--list-supported``, but outputs the supported hardware in MediaWiki syntax, 261 so that it can be easily pasted into the `supported hardware wiki page <https://flashrom.org/Supported_hardware>`_. 262 Please note that MediaWiki output is not compiled in by default. 263 264 265**-p, --programmer <name>[:parameter[,parameter[,parameter]]]** 266 Specify the programmer device. This is mandatory for all operations involving any chip access (probe/read/write/...). 267 Currently supported are: 268 269 * ``internal`` (for in-system flashing in the mainboard) 270 * ``dummy`` (virtual programmer for testing **flashrom**) 271 * ``nic3com`` (for flash ROMs on 3COM network cards) 272 * ``nicrealtek`` (for flash ROMs on Realtek and SMC 1211 network cards) 273 * ``nicnatsemi`` (for flash ROMs on National Semiconductor DP838* network cards) 274 * ``nicintel`` (for parallel flash ROMs on Intel 10/100Mbit network cards) 275 * ``gfxnvidia`` (for flash ROMs on NVIDIA graphics cards) 276 * ``drkaiser`` (for flash ROMs on Dr. Kaiser PC-Waechter PCI cards) 277 * ``satasii`` (for flash ROMs on Silicon Image SATA/IDE controllers) 278 * ``satamv`` (for flash ROMs on Marvell SATA controllers) 279 * ``atahpt`` (for flash ROMs on Highpoint ATA/RAID controllers) 280 * ``atavia`` (for flash ROMs on VIA VT6421A SATA controllers) 281 * ``atapromise`` (for flash ROMs on Promise PDC2026x ATA/RAID controllers) 282 * ``it8212`` (for flash ROMs on ITE IT8212F ATA/RAID controller) 283 * ``ft2232_spi`` (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family based USB SPI programmer) 284 * ``serprog`` (for flash ROMs attached to a programmer speaking serprog, including some Arduino-based devices) 285 * ``buspirate_spi`` (for SPI flash ROMs attached to a Bus Pirate) 286 * ``dediprog`` (for SPI flash ROMs attached to a Dediprog SF100) 287 * ``rayer_spi`` (for SPI flash ROMs attached to a parallel port by one of various cable types) 288 * ``raiden_debug_spi`` (For Chrome EC based debug tools - SuzyQable, Servo V4, C2D2 & uServo) 289 * ``pony_spi`` (for SPI flash ROMs attached to a SI-Prog serial port bitbanging adapter) 290 * ``nicintel_spi`` (for SPI flash ROMs on Intel Gigabit network cards) 291 * ``ogp_spi`` (for SPI flash ROMs on Open Graphics Project graphics card) 292 * ``linux_mtd`` (for SPI flash ROMs accessible via /dev/mtdX on Linux) 293 * ``linux_spi`` (for SPI flash ROMs accessible via /dev/spidevX.Y on Linux) 294 * ``usbblaster_spi`` (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable) 295 * ``nicintel_eeprom`` (for SPI EEPROMs on Intel Gigabit network cards) 296 * ``mstarddc_spi`` (for SPI flash ROMs accessible through DDC in MSTAR-equipped displays) 297 * ``pickit2_spi`` (for SPI flash ROMs accessible via Microchip PICkit2) 298 * ``ch341a_spi`` (for SPI flash ROMs attached to WCH CH341A) 299 * ``ch347_api`` (for SPI flash ROMs attached to WHC CH347) 300 * ``digilent_spi`` (for SPI flash ROMs attached to iCEblink40 development boards) 301 * ``jlink_spi`` (for SPI flash ROMs attached to SEGGER J-Link and compatible devices) 302 * ``ni845x_spi`` (for SPI flash ROMs attached to National Instruments USB-8451 or USB-8452) 303 * ``stlinkv3_spi`` (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices) 304 * ``realtek_mst_i2c_spi`` (for SPI flash ROMs attached to Realtek DisplayPort hubs accessible through I2C) 305 * ``parade_lspcon`` (for SPI flash ROMs attached to Parade Technologies LSPCONs (PS175)) 306 * ``mediatek_i2c_spi`` (for SPI flash ROMs attached to some Mediatek display devices accessible over I2C) 307 * ``dirtyjtag_spi`` (for SPI flash ROMs attached to DirtyJTAG-compatible devices) 308 * ``asm106x`` (for SPI flash ROMs attached to asm106x PCI SATA controllers) 309 310 Some programmers have optional or mandatory parameters which are described in detail in the 311 **PROGRAMMER-SPECIFIC INFORMATION** section. Support for some programmers can be disabled at compile time. 312 ``flashrom -h`` lists all supported programmers. 313 314 315**-h, --help** 316 Show a help text and exit. 317 318 319**-o, --output <logfile>** 320 Save the full debug log to **<logfile>**. 321 If the file already exists, it will be overwritten. This is the recommended way to gather logs from **flashrom** 322 because they will be verbose even if the on-screen messages are not verbose and don't require output redirection. 323 324 325**--progress** 326 [Experimental feature] Show progress percentage of operations on the standard output. 327 328 329**-R, --version** 330 Show version information and exit. 331 332.. _programmer-specific information: 333 334PROGRAMMER-SPECIFIC INFORMATION 335------------------------------- 336Some programmer drivers accept further parameters to set programmer-specific parameters. These parameters are separated 337from the programmer name by a colon. While some programmers take arguments atfixed positions, other programmers use a 338key/value interface in which the key and value is separated by an equal sign and different pairs are separated by a 339comma or a colon. 340 341 342internal programmer 343^^^^^^^^^^^^^^^^^^^ 344 345 346**Board Enables** 347 Some mainboards require to run mainboard specific code to enable flash erase and write support 348 (and probe support on old systems with parallel flash). 349 The mainboard brand and model (if it requires specific code) is usually autodetected using one of the following mechanisms: 350 If your system is running coreboot, the mainboard type is determined from the coreboot table. 351 Otherwise, the mainboard is detected by examining the onboard PCI devices and possibly DMI info. 352 If PCI and DMI do not contain information to uniquely identify the mainboard (which is the exception), 353 or if you want to override the detected mainboard model, you can specify the mainboard using the:: 354 355 flashrom -p internal:mainboard=<vendor>:<board> 356 357 syntax. 358 359 See the **Known boards** or **Known laptops** section in the output of ``flashrom -L`` for a list of boards 360 which require the specification of the board name, if no coreboot table is found. 361 362 Some of these board-specific flash enabling functions (called **board enables** ) in **flashrom** have not yet been tested. 363 If your mainboard is detected needing an untested board enable function, a warning message is printed and the board enableis not executed, 364 because a wrong board enable function might cause the system to behave erratically, as board enable functions touch the 365 low-level internals of a mainboard. 366 Not executing a board enable function (if one is needed) might cause detection or erasing failure. 367 If your board protects only part of the flash (commonly the top end, called boot block), 368 **flashrom** might encounter an error only after erasing the unprotected part, so running without the board-enable function 369 might be dangerous for erase and write (which includes erase). 370 371 The suggested procedure for a mainboard with untested board specific code is to first try to probe the ROM 372 (just invoke **flashrom** and check that it detects your flash chip type) without running the board enable code 373 (i.e. without any parameters). If it finds your chip, fine. Otherwise, retry probing your chip with the board-enable code running, using:: 374 375 flashrom -p internal:boardenable=force 376 377 If your chip is still not detected, the board enable code seems to be broken or the flash chip unsupported. 378 Otherwise, make a backup of your current ROM contents (using ``-r``) and store it to a medium outside of your computer, 379 like a USB drive or a network share. If you needed to run the board enable code already for probing, use it for reading too. 380 If reading succeeds and the contents of the read file look legit you can try to write the new image. 381 You should enable the board enable code in any case now, as it has been written because it is known that writing/erasing 382 without the board enable is going to fail. In any case (success or failure), please report to the **flashrom** mailing list, see below. 383 384**Coreboot** 385 On systems running coreboot, **flashrom** checks whether the desired image matches your mainboard. 386 This needs some special board ID to be present in the image. 387 If **flashrom** detects that the image you want to write and the current board do not match, 388 it will refuse to write the image unless you specify:: 389 390 flashrom -p internal:boardmismatch=force 391 392 393**ITE IT87 Super I/O** 394 If your mainboard is manufactured by GIGABYTE and supports DualBIOS it is very likely that it uses an 395 ITE IT87 series Super I/O to switch between the two flash chips. 396 Only one of them can be accessed at a time and you can manually select which one to use with the:: 397 398 flashrom -p internal:dualbiosindex=chip 399 400 syntax where ``chip`` is the index of the chip to use (0 = main, 1 = backup). 401 You can check which one is currently selected by leaving out the ``chip`` parameter. 402 403 If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, **flashrom** should autodetect that configuration. 404 If you want to set the I/O base port of the IT87 series SPI controller manually instead of using the value provided by the BIOS, 405 use the:: 406 407 flashrom -p internal:it87spiport=portnum 408 409 syntax where ``portnum`` is the I/O port number (must be a multiple of 8). 410 In the unlikely case **flashrom** doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. 411 412 413**AMD chipsets** 414 Beginning with the SB700 chipset there is an integrated microcontroller (IMC) based on the 8051 embedded in every AMD southbridge. 415 Its firmware resides in the same flash chip as the host's which makes writing to the flash risky if the IMC is active. 416 Flashrom tries to temporarily disable the IMC but even then changing the contents of the flash can have unwanted effects: 417 when the IMC continues (at the latest after a reboot) it will continue executing code from the flash. 418 If the code was removed or changed in an unfortunate way it is unpredictable what the IMC will do. 419 Therefore, if **flashrom** detects an active IMC it will disable write support unless the user forces it with the:: 420 421 flashrom -p internal:amd_imc_force=yes 422 423 syntax. The user is responsible for supplying a suitable image or leaving out the IMC region with the help of a layout file. 424 This limitation might be removed in the future when we understand the details better and have received enough feedback from users. 425 Please report the outcome if you had to use this option to write a chip. 426 427 An optional ``spispeed`` parameter specifies the frequency of the SPI bus where applicable 428 (i.e.SB600 or later with an SPI flash chip directly attached to the chipset). 429 Syntax is:: 430 431 flashrom -p internal:spispeed=frequency 432 433 where ``frequency`` can be ``'16.5 MHz'``, ``'22 MHz'``, ``'33 MHz'``, ``'66 MHz'``, ``'100 MHZ'``, or ``'800 kHz'``. 434 Support of individual frequencies depends on the generation of the chipset: 435 436 * SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz. 437 The default is to use 16.5 MHz and disable Fast Reads. 438 * SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz. 439 The default is to use 16.5 MHz and disable Fast Reads. 440 * Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them. 441 The default is to use the frequency that is currently configured. 442 443 An optional ``spireadmode`` parameter specifies the read mode of the SPI bus where applicable (Bolton or later). 444 Syntax is:: 445 446 flashrom -p internal:spireadmode=mode 447 448 where ``mode`` can be ``'Normal (up to 33 MHz)'``, ``'Normal (up to 66 MHz)'``, ``'Dual IO (1-1-2)'``, ``'Quad IO (1-1-4)'``, 449 ``'Dual IO (1-2-2)'``, ``'Quad IO (1-4-4)'``, or ``'Fast Read'``. 450 451 The default is to use the read mode that is currently configured. 452 453 454**Intel chipsets** 455 If you have an Intel chipset with an ICH8 or later southbridge with SPI flash attached, and if a valid descriptor was written 456 to it (e.g. by the vendor), the chipset provides an alternative way to access the flash chip(s) named **Hardware Sequencing**. 457 It is much simpler than the normal access method (called **Software Sequencing**), but does not allow the software to 458 choose the SPI commands to be sent. You can use the:: 459 460 flashrom -p internal:ich_spi_mode=value 461 462 syntax where ``value`` can be ``auto``, ``swseq`` or ``hwseq``. By default (or when setting ``ich_spi_mode=auto``) the 463 module tries to use swseq and only activates hwseq if need be (e.g. if important opcodes are inaccessible due to lockdown; 464 or if more than one flash chip is attached). The other options (swseq, hwseq) select the respective mode (if possible). 465 466 ICH8 and later southbridges may also have locked address ranges of different kinds if a valid descriptor was written to it. 467 The flash address space is then partitioned in multiple so called "Flash Regions" containing the host firmware, 468 the ME firmware and so on respectively. The flash descriptor can also specify up to 5 so called **Protected Regions**, 469 which are freely chosen address ranges independent from the aforementioned **Flash Regions**. 470 All of them can be write and/or read protected individually. 471 472 If you have an Intel chipset with an ICH2 or later southbridge and if you want to set specific IDSEL values for a 473 non-default flash chip or an embedded controller (EC), you can use the:: 474 475 flashrom -p internal:fwh_idsel=value 476 477 syntax where ``value`` is the 48-bit hexadecimal raw value to be written in the IDSEL registers of the Intel southbridge. 478 The upper 32 bits use one hex digit each per 512 kB range between 0xffc00000 and 0xffffffff, and the lower 16 bits 479 use one hex digit each per 1024 kB range between 0xff400000 and 0xff7fffff. 480 The rightmost hex digit corresponds with the lowest address range. All address ranges have a corresponding sister range 481 4 MB below with identical IDSEL settings. The default value for ICH7 is given in the example below. 482 483 Example:: 484 485 flashrom -p internal:fwh_idsel=0x001122334567 486 487 488**Laptops** 489 Using **flashrom** on older laptops that don't boot from the SPI bus is dangerous and may easily make your hardware unusable 490 (see also the **BUGS** section). The embedded controller (EC) in some machines may interact badly with flashing. 491 More information is `in the wiki <https://flashrom.org/Laptops>`_. 492 Problems occur when the flash chip is shared between BIOS and EC firmware, and the latter does not expect **flashrom** 493 to access the chip. While **flashrom** tries to change the contents of that memory the EC might need to fetch new 494 instructions or data from it and could stop working correctly. Probing for and reading from the chip may also irritate 495 your EC and cause fan failure, backlight failure, sudden poweroff, and other nasty effects. **flashrom** will attempt to 496 detect if it is running on such a laptop and limit probing to SPI buses. If you want to probe the LPC bus anyway at your own risk, use:: 497 498 flashrom -p internal:laptop=force_I_want_a_brick 499 500 We will not help you if you force flashing on a laptop because this is a really dumb idea. 501 502 You have been warned. 503 504 Currently we rely on the chassis type encoded in the DMI/SMBIOS data to detect laptops. Some vendors did not implement 505 those bits correctly or set them to generic and/or dummy values. **flashrom** will then issue a warning and restrict buses like above. 506 In this case you can use:: 507 508 flashrom -p internal:laptop=this_is_not_a_laptop 509 510 to tell **flashrom** (at your own risk) that it is not running on a laptop. 511 512 513dummy programmer 514^^^^^^^^^^^^^^^^ 515 516The dummy programmer operates on a buffer in memory only. It provides a safe and fast way to test various aspects of 517**flashrom** and is mainly used in development and while debugging. 518It is able to emulate some chips to a certain degree (basic identify/read/erase/write operations work). 519 520An optional parameter specifies the bus types it should support. For that you have to use the:: 521 522 flashrom -p dummy:bus=[type[+type[+type]]] 523 524syntax where ``type`` can be ``parallel``, ``lpc``, ``fwh``, ``spi`` in any order. If you specify bus without type, 525all buses will be disabled. If you do not specify bus, all buses will be enabled. 526 527Example:: 528 529 flashrom -p dummy:bus=lpc+fwh 530 531The dummy programmer supports flash chip emulation for automated self-tests without hardware access. 532If you want to emulate a flash chip, use the:: 533 534 flashrom -p dummy:emulate=chip 535 536syntax where ``chip`` is one of the following chips (please specify only the chip name, not the vendor): 537 538* ST ``M25P10.RES`` SPI flash chip (128 kB, RES, page write) 539* SST ``SST25VF040.REMS`` SPI flash chip (512 kB, REMS, byte write) 540* SST ``SST25VF032B`` SPI flash chip (4096 kB, RDID, AAI write) 541* Macronix ``MX25L6436`` SPI flash chip (8192 kB, RDID, SFDP) 542* Winbond ``W25Q128FV`` SPI flash chip (16384 kB, RDID) 543* Spansion ``S25FL128L`` SPI flash chip (16384 kB, RDID) 544* Dummy vendor ``VARIABLE_SIZE`` SPI flash chip (configurable size, page write) 545 546Example:: 547 548 flashrom -p dummy:emulate=SST25VF040.REMS 549 550To use ``VARIABLE_SIZE`` chip, ``size`` must be specified to configure the size of the flash chip as a power of two. 551 552Example:: 553 554 flashrom -p dummy:emulate=VARIABLE_SIZE,size=16777216,image=dummy.bin 555 556 557**Persistent images** 558 If you use flash chip emulation, flash image persistence is available as well by using the:: 559 560 flashrom -p dummy:emulate=chip,image=image.rom 561 562 syntax where ``image.rom`` is the file where the simulated chip contents are read on **flashrom** startup and where the 563 chip contents on **flashrom** shutdown are written to. 564 565 Example:: 566 567 flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin 568 569 570**SPI write chunk size** 571 If you use SPI flash chip emulation for a chip which supports SPI page write with the default opcode, 572 you can set the maximum allowed write chunk size with the:: 573 574 flashrom -p dummy:emulate=chip,spi_write_256_chunksize=size 575 576 syntax where ``size`` is the number of bytes (min.\& 1, max.\& 256). 577 Example:: 578 579 flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5 580 581 582**SPI blacklist** 583 To simulate a programmer which refuses to send certain SPI commands to the flash chip, you can specify a blacklist of 584 SPI commands with the:: 585 586 flashrom -p dummy:spi_blacklist=commandlist 587 588 syntax where ``ommandlist`` is a list of two-digit hexadecimal representations of SPI commands. 589 If commandlist is e.g. 0302, **flashrom** will behave as if the SPI controller refuses to run command 0x03 (READ) and command 0x02 (WRITE). 590 commandlist may be up to 512 characters (256 commands) long. 591 Implementation note: **flashrom** will detect an error during command execution. 592 593 594**SPI ignorelist** 595 To simulate a flash chip which ignores (doesn't support) certain SPI commands, you can specify an ignorelist of SPI commands with the:: 596 597 flashrom -p dummy:spi_ignorelist=commandlist 598 599 syntax where ``commandlist`` is a list of two-digit hexadecimal representations of SPI commands. 600 If commandlist is e.g. 0302, the emulated flash chip will ignore command 0x03 (READ) and command 0x02 (WRITE). 601 ``commandlist`` may be up to 512 characters (256 commands) long. 602 Implementation note: **flashrom** won't detect an error during command execution. 603 604 605**SPI status register** 606 You can specify the initial content of the chip's status register with the:: 607 608 flashrom -p dummy:spi_status=content" 609 610 syntax where ``content`` is a hexadecimal value of up to 24 bits. For example, ``0x332211`` assigns 0x11 to SR1, 611 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with zeroes on the left. 612 See datasheet for chosen chip for details about the registers content. 613 614 615**Write protection** 616 Chips with emulated WP: **W25Q128FV**, **S25FL128L**. 617 618 You can simulate state of hardware protection pin (WP) with the:: 619 620 flashrom -p dummy:hwwp=state 621 622 syntax where ``state`` is ``yes`` or ``no`` (default value). ``yes`` means active state of the pin implies that chip is 623 write-protected (on real hardware the pin is usually negated, but not here). 624 625**Frequency** 626 Frequency can be specified in ``Hz`` (default), ``KHz``, or ``MHz`` (not case sensitive). 627 If ``freq`` parameter is passed in from command line, commands will delay for certain time before returning, 628 so that to emulate the requested frequency. 629 630 Valid range is [1Hz, 8000Mhz] and there is no delay by default. 631 632 The delay of an SPI command is proportional to the number of bits send over SPI bus in both directions 633 and is calculated based on the assumption that we transfer at 1 bit/Hz:: 634 635 flashrom -p dummy:emulate=W25Q128FV,freq=64mhz 636 637 638nic3com, nicrealtek, nicnatsemi, nicintel, nicintel_eeprom, nicintel_spi, gfxnvidia, ogp_spi, drkaiser, satasii, satamv, atahpt, atavia, atapromise, it8212 programmers 639^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 640 641These programmers have an option to specify the PCI address of the card your want to use, which must be specified if 642more than one card supported by the selected programmer is installed in your system. The syntax is:: 643 644 flashrom -p xxxx:pci=bb:dd.f 645 646where ``xxxx`` is the name of the programmer, ``bb`` is the PCI bus number, ``dd`` is the PCI device number, and ``b`` 647is the PCI function number of the desired device. Example:: 648 649 flashrom -p nic3com:pci=05:04.0 650 651Some of these programmers have more info below. 652 653atavia programmer 654^^^^^^^^^^^^^^^^^ 655 656Due to the mysterious address handling of the VIA VT6421A controller the user can specify an offset with the:: 657 658 flashrom -p atavia:offset=addr 659 660syntax where ``addr`` will be interpreted as usual (leading 0x (0) for hexadecimal (octal) values, or else decimal). 661For more information please see `its wiki page <https://flashrom.org/VT6421A "its wiki page>`_. 662 663 664atapromise programmer 665^^^^^^^^^^^^^^^^^^^^^ 666 667This programmer is currently limited to 32 kB, regardless of the actual size of the flash chip. This stems from the 668fact that, on the tested device (a Promise Ultra100), not all of the chip's address lines were actually connected. 669You may use this programmer to flash firmware updates, since these are only 16 kB in size (padding to 32 kB is required). 670 671nic3com programmer 672^^^^^^^^^^^^^^^^^^ 673 674flashrom supports some 3Com network cards to reflash the (parallel) flash attached to these cards, 675but it is also possible to use these cards to reflash other chips which fit in there electrically. 676Please note that the small number of address lines connected to the chip may make accessing large chips impossible. 677The maximum supported chip size is 128KB. 678 679nicintel_spi programmer 680^^^^^^^^^^^^^^^^^^^^^^^ 681 682Programmer for SPI flash ROMs on Intel Gigabit network cards. Tested on 32-bit hardware/PCI only. 683 684nicintel_eeprom programmer 685^^^^^^^^^^^^^^^^^^^^^^^^^^ 686 687This is the first programmer module in **flashrom** that does not provide access to NOR flash chips but EEPROMs mounted on 688gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their size nor allow 689themselves to be identified, the controller relies on correct size values written to predefined addresses within the chip. 690**Flashrom** follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed EEPROM/card is detected. 691Intel specifies following EEPROMs to be compatible: 692Atmel AT25128, AT25256, Micron (ST) M95128, M95256 and OnSemi (Catalyst) CAT25CS128. 693 694gfxnvidia programmer 695^^^^^^^^^^^^^^^^^^^^ 696 697Flashrom supports some Nvidia graphic cards to reflash the (parallel) flash attached to these cards, 698but it is also possible to use these cards to reflash other chips which fit in there electrically. 699 700satasii programmer 701^^^^^^^^^^^^^^^^^^ 702 703Flashrom supports some SiI ATA/SATA controllers to reflash the flash attached to these controller cards, 704but it is also possible to use these cards to reflash other chips which fit in there electrically. 705Please note that the small number of address lines connected to the chip may make accessing large chips impossible. 706 707ft2232_spi programmer 708^^^^^^^^^^^^^^^^^^^^^ 709 710This module supports various programmers based on FTDI FT2232/FT4232H/FT232H chips including the DLP Design DLP-USB1232H, 711openbiosprog-spi, Amontec JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, Olimex ARM-USB-TINY/-H, 712Olimex ARM-USB-OCD/-H, OpenMoko Neo1973 Debug board (V2+), TIAO/DIYGADGET USB Multi-Protocol Adapter (TUMPA), TUMPA Lite, 713GOEPEL PicoTAP, Google Servo v1/v2, Tin Can Tools Flyswatter/Flyswatter 2 and Kristech KT-LINK. 714 715An optional parameter specifies the controller type, channel/interface/port it should support. For that you have to use the:: 716 717 flashrom \-p ft2232_spi:type=model,port=interface 718 719syntax where ``model`` can be ``2232H``, ``4232H``, ``232H``, ``jtagkey``, ``busblaster``, ``openmoko``, ``arm-usb-tiny``, 720``arm-usb-tiny-h``, ``arm-usb-ocd``, ``arm-usb-ocd-h``, ``tumpa``, ``tumpalite``, ``picotap``, ``google-servo, 721``google-servo-v2``, ``google-servo-v2-legacy`` or ``kt-link``. 722``interface`` can be ``A``, ``B``, ``C``, or ``D``. The default model is ``4232H``, the default interface is ``A`` and 723GPIO is not used by default. 724 725If there is more than one ft2232_spi-compatible device connected, you can select which one should be used by specifying 726its serial number with the:: 727 728 flashrom -p ft2232_spi:serial=number 729 730syntax where ``number`` is the serial number of the device (which can be found for example in the output of lsusb -v). 731 732All models supported by the **ft2232_spi** driver can configure the SPI clock rate by setting a divisor. The expressible 733divisors are all **even** numbers between 2 and 2^17 (=131072) resulting in SPI clock frequencies of 6 MHz down to about 73492 Hz for 12 MHz inputs (non-H chips) and 30 MHz down to about 458 Hz for 60 MHz inputs ('H' chips). The default divisor 735is set to 2, but you can use another one by specifying the optional ``divisor`` parameter with the:: 736 737 flashrom -p ft2232_spi:divisor=div 738 739syntax. Using the parameter ``csgpiol`` (DEPRECATED - use ``gpiol`` instead) an additional CS# pin can be chosen, 740where the value can be a number between 0 and 3, denoting GPIOL0-GPIOL3 correspondingly. Example:: 741 742 flashrom -p ft2232_spi:csgpiol=3 743 744The parameter ``gpiolX=[HLC]`` allows use of the GPIOL pins either as generic gpios with a fixed value during flashing 745or as additional CS# signal, where ``X`` can be a number between 0 and 3, denoting GPIOL0-GPIOL3 correspondingly. 746The parameter may be specified multiple times, one time per GPIOL pin. Valid values are ``H``, ``L`` and ``C``: 747 748* ``H`` - Set GPIOL output high 749* ``L`` - Set GPIOL output low 750* ``C`` - Use GPIOL as additional CS# output 751 752Example:: 753 754 flashrom -p ft2232_spi:gpiol0=H 755 756**Note** that not all GPIOL pins are freely usable with all programmers as some have special functionality. 757 758 759serprog programmer 760^^^^^^^^^^^^^^^^^^ 761 762This module supports all programmers speaking the serprog protocol. This includes some Arduino-based devices as well as 763various programmers by Urja Rannikko, Juhana Helovuo, Stefan Tauner, Chi Zhang and many others. 764 765A mandatory parameter specifies either a serial device (and baud rate) or an IP/port combination for communicating with 766the programmer. The device/baud combination has to start with ``dev=`` and separate the optional baud rate with a colon. 767For example:: 768 769 flashrom -p serprog:dev=/dev/ttyS0:115200 770 771If no baud rate is given the default values by the operating system/hardware will be used. 772For IP connections you have to use the:: 773 774 flashrom -p serprog:ip=ipaddr:port 775 776syntax. In case the device supports it, you can set the SPI clock frequency with the optional ``spispeed`` parameter. 777The frequency is parsed as hertz, unless an ``M``, or ``k`` suffix is given, then megahertz or kilohertz are used respectively. 778Example that sets the frequency to 2 MHz:: 779 780 flashrom -p serprog:dev=/dev/device:baud,spispeed=2M 781 782Optional ``cs`` parameter can be used to switch which chip select number is used. This allows connecting multiple 783chips at once and selecting which one to flash by software means (rather than rewiring):: 784 785 flashrom -p serprog:dev=/dev/device:baud,cs=0 786 787The particular programmer implementation needs to support this feature, for it to work. If the requested chip 788select isn't available, flashrom will fail safely. 789 790More information about serprog is available in this document: :doc:`/supported_hw/supported_prog/serprog/serprog-protocol`. 791 792 793buspirate_spi programmer 794^^^^^^^^^^^^^^^^^^^^^^^^ 795 796A required ``dev`` parameter specifies the Bus Pirate device node and an optional ``spispeed`` parameter specifies the 797frequency of the SPI bus. The parameter delimiter is a comma. Syntax is:: 798 799 flashrom -p buspirate_spi:dev=/dev/device,spispeed=frequency 800 801where ``frequency`` can be ``30k``, ``125k``, ``250k``, ``1M``, ``2M``, ``2.6M``, ``4M`` or ``8M`` (in Hz). 802The default is the maximum frequency of 8 MHz. 803 804The baud rate for communication between the host and the Bus Pirate can be specified with the optional ``serialspeed`` 805parameter. Syntax is:: 806 807 flashrom -p buspirate_spi:serialspeed=baud 808 809where ``baud`` can be ``115200``, ``230400``, ``250000`` or ``2000000`` (``2M``). 810The default is ``2M`` baud for Bus Pirate hardware version 3.0 and greater, and 115200 otherwise. 811 812An optional pullups parameter specifies the use of the Bus Pirate internal pull-up resistors. This may be needed if you 813are working with a flash ROM chip that you have physically removed from the board. Syntax is:: 814 815 flashrom -p buspirate_spi:pullups=state 816 817where ``state`` can be ``on`` or ``off``. 818More information about the Bus Pirate pull-up resistors and their purpose is available 819`in a guide by dangerousprototypes <http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_resistors>`_. 820 821When working with low-voltage chips, the internal 10k pull-ups of the Bus Pirate might be too high. In such cases, it's necessary to create an external pull-up using lower-value resistors. 822 823For this, you can use the ``hiz`` parameter. This way, the Bus Pirate will operate as an open drain. Syntax is:: 824 825 flashrom -p buspirate_spi:hiz=state 826 827where ``state`` can be ``on`` or ``off``. 828 829The state of the Bus Pirate power supply pins is controllable through an optional ``psus`` parameter. Syntax is:: 830 831 flashrom -p buspirate_spi:psus=state 832 833where ``state`` can be ``on`` or ``off``. 834This allows the bus pirate to power the ROM chip directly. This may also be used to provide the required pullup voltage 835(when using the **pullups** option), by connecting the Bus Pirate's Vpu input to the appropriate Vcc pin. 836 837An optional aux parameter specifies the state of the Bus Pirate auxiliary pin. 838This may be used to drive the auxiliary pin high or low before a transfer. 839Syntax is:: 840 841 flashrom -p buspirate_spi:aux=state 842 843where ``state`` can be ``high`` or ``low``. The default ``state`` is ``high``. 844 845 846pickit2_spi programmer 847^^^^^^^^^^^^^^^^^^^^^^ 848 849An optional ``voltage`` parameter specifies the voltage the PICkit2 should use. The default unit is Volt if no unit is specified. 850You can use ``mV``, ``millivolt``, ``V`` or ``Volt`` as unit specifier. Syntax is:: 851 852 flashrom \-p pickit2_spi:voltage=value 853 854where ``value`` can be ``0V``, ``1.8V``, ``2.5V``, ``3.5V`` or the equivalent in mV. 855 856An optional ``spispeed`` parameter specifies the frequency of the SPI bus. Syntax is:: 857 858 flashrom -p pickit2_spi:spispeed=frequency 859 860where ``frequency`` can be ``250k``, ``333k``, ``500k`` or ``1M`` (in Hz). The default is a frequency of 1 MHz. 861 862 863dediprog programmer 864^^^^^^^^^^^^^^^^^^^ 865 866An optional ``voltage`` parameter specifies the voltage the Dediprog should use. The default unit is Volt if no unit is specified. 867You can use ``mV``, ``milliVolt``, ``V`` or ``Volt`` as unit specifier. Syntax is:: 868 869 flashrom -p dediprog:voltage=value 870 871where ``value`` can be ``0V``, ``1.8V``, ``2.5V``, ``3.5V`` or the equivalent in mV. 872 873An optional ``device`` parameter specifies which of multiple connected Dediprog devices should be used. 874Please be aware that the order depends on libusb's usb_get_busses() function and that the numbering starts at 0. 875Usage example to select the second device:: 876 877 flashrom -p dediprog:device=1 878 879An optional ``spispeed`` parameter specifies the frequency of the SPI bus. The firmware on the device needs to be 5.0.0 or newer. 880Syntax is:: 881 882 flashrom -p dediprog:spispeed=frequency 883 884where ``frequency`` can be ``375k``, ``750k``, ``1.5M``, ``2.18M``, ``3M``, ``8M``, ``12M`` or ``24M`` (in Hz). 885The default is a frequency of 12 MHz. 886 887An optional ``target`` parameter specifies which target chip should be used. Syntax is:: 888 889 flashrom -p dediprog:target=value 890 891where ``value`` can be ``1`` or ``2`` to select target chip 1 or 2 respectively. The default is target chip 1. 892 893 894rayer_spi programmer 895^^^^^^^^^^^^^^^^^^^^ 896 897The default I/O base address used for the parallel port is 0x378 and you can use the optional ``iobase`` parameter to 898specify an alternate base I/O address with the:: 899 900 flashrom -p rayer_spi:iobase=baseaddr 901 902syntax where ``baseaddr`` is base I/O port address of the parallel port, which must be a multiple of four. 903Make sure to not forget the "0x" prefix for hexadecimal port addresses. 904 905The default cable type is the RayeR cable. You can use the optional ``type`` parameter to specify the cable type with the:: 906 907 flashrom -p rayer_spi:type=model 908 909syntax where ``model`` can be ``rayer`` for the RayeR cable, ``byteblastermv`` for the Altera ByteBlasterMV, 910``stk200`` for the Atmel, ``STK200/300``, ``wiggler`` for the Macraigor Wiggler, ``xilinx`` for the Xilinx Parallel Cable III (DLC 5), 911or ``spi_tt`` for SPI Tiny Tools-compatible hardware. 912 913More information about the RayeR hardware is available at `RayeR's website <http://rayer.g6.cz/elektro/spipgm.htm>`_. 914The Altera ByteBlasterMV datasheet can be obtained from `Altera <http://www.altera.co.jp/literature/ds/dsbytemv.pdf>`_. 915For more information about the Macraigor Wiggler see `their company homepage <http://www.macraigor.com/wiggler.htm>`_. 916The schematic of the Xilinx DLC 5 was published in `a Xilinx guide <http://www.xilinx.com/support/documentation/user_guides/xtp029.pdf>`_. 917 918 919raiden_debug_spi programmer 920^^^^^^^^^^^^^^^^^^^^^^^^^^^ 921 922Some devices such as the GSC knows how it is wired to AP and EC flash chips, and can be told which specific device to talk to using the ``target`` parameter:: 923 924 flashrom -p raiden_debug_spi:target={ap,ec} 925 926Other devices such as Servo Micro and HyperDebug are generic, and do not know how they are wired, the caller is responsible for first configure the appropriate MUXes or buffers, and then tell the debugger which port to use (Servo Micro has just one SPI port, HyperDebug is the first of this kind to have multiple):: 927 928 flashrom -p raiden_debug_spi:target=N 929 930where ``N`` is an non-negative integer (default ``0``). 931 932The default is to use the first available servo. You can use the optional ``serial`` parameter to specify the servo 933USB device serial number to use specifically with:: 934 935 flashrom -p raiden_debug_spi:serial=XXX 936 937The servo device serial number can be found via ``lsusb``. 938Raiden will poll the ``ap`` target waiting for the system power to settle on the AP and EC flash devices. 939 940The optional ``custom_rst=true`` parameter alters the behavior of the reset process:: 941 942 flashrom -p raiden_debug_spi:custom_rst=<true|false> 943 944syntax, where: 945 946``custom_rst=false`` is the implicit default timeout of 3ms 947 948and ``custom_rst=true`` set ``RAIDEN_DEBUG_SPI_REQ_ENABLE_AP_CUSTOM`` instead of ``RAIDEN_DEBUG_SPI_REQ_ENABLE_AP``. 949This custom reset will modify the timeout from 3ms to 10ms and will not set ``EC_RST_L``, meaning neither the EC nor the AP will be reset. With this setting, it's the user's responsibility to manage the reset signal manually or by configuring the GPIO. 950Failure to handle the reset signal appropriately will likely result in flashing errors. 951 952More information about the ChromiumOS servo 953hardware is available at `servos website <https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo_v4.md>`_. 954 955 956pony_spi programmer 957^^^^^^^^^^^^^^^^^^^ 958 959The serial port (like /dev/ttyS0, /dev/ttyUSB0 on Linux or COM3 on windows) is specified using the mandatory ``dev`` 960parameter. The adapter type is selectable between SI-Prog (used for SPI devices with PonyProg 2000) or a custom made 961serial bitbanging programmer named "serbang". The optional ``type`` parameter accepts the values ``si_prog`` (default) 962or ``serbang``. 963 964Information about the SI-Prog adapter can be found at `its website <http://www.lancos.com/siprogsch.html>`_. 965 966An example call to **flashrom** is:: 967 968 flashrom -p pony_spi:dev=/dev/ttyS0,type=serbang 969 970Please note that while USB-to-serial adapters work under certain circumstances, this slows down operation considerably. 971 972 973ogp_spi programmer 974^^^^^^^^^^^^^^^^^^ 975 976The flash ROM chip to access must be specified with the ``rom`` parameter:: 977 978 flashrom -p ogp_spi:rom=name 979 980Where ``name`` is either ``cprom`` or ``s3`` for the configuration ROM and ``bprom`` or ``bios`` for the BIOS ROM. 981If more than one card supported by the **ogp_spi** programmer is installed in your system, you have to specify the PCI 982address of the card you want to use with the ``pci=`` parameter as explained in the **nic3com** et al. section above. 983 984 985linux_mtd programmer 986^^^^^^^^^^^^^^^^^^^^ 987 988You may specify the MTD device to use with the:: 989 990 flashrom -p linux_mtd:dev=/dev/mtdX 991 992syntax where ``/dev/mtdX`` is the Linux device node for your MTD device. If left unspecified the first MTD device found 993(e.g. /dev/mtd0) will be used by default. 994 995Please note that the linux_mtd driver only works on Linux. 996 997 998linux_spi programmer 999^^^^^^^^^^^^^^^^^^^^ 1000 1001You have to specify the SPI controller to use with the:: 1002 1003 flashrom -p linux_spi:dev=/dev/spidevX.Y 1004 1005syntax where ``/dev/spidevX.Y`` is the Linux device node for your SPI controller. 1006 1007In case the device supports it, you can set the SPI clock frequency with the optional ``spispeed`` parameter. 1008The frequency is parsed as kilohertz. Example that sets the frequency to 8 MHz:: 1009 1010 flashrom -p linux_spi:dev=/dev/spidevX.Y,spispeed=8000 1011 1012Please note that the linux_spi driver only works on Linux. 1013 1014 1015mstarddc_spi programmer 1016^^^^^^^^^^^^^^^^^^^^^^^ 1017 1018The Display Data Channel (DDC) is an I2C bus present on VGA and DVI connectors, that allows exchanging information 1019between a computer and attached displays. Its most common uses are getting display capabilities through EDID 1020(at I2C address 0x50) and sending commands to the display using the DDC/CI protocol (at address 0x37). 1021On displays driven by MSTAR SoCs, it is also possible to access the SoC firmware flash (connected to the Soc through another SPI bus) 1022using an In-System Programming (ISP) port, usually at address 0x49. This **flashrom** module allows the latter via Linux's I2C driver. 1023 1024**IMPORTANT:** 1025Before using this programmer, the display **MUST** be in standby mode, and only connected to the computer that will run 1026**flashrom** using a VGA cable, to an inactive VGA output. It absolutely **MUST NOT** be used as a display during the procedure! 1027 1028You have to specify the DDC/I2C controller and I2C address to use with the:: 1029 1030 flashrom -p mstarddc_spi:dev=/dev/i2c-X:YY 1031 1032syntax where ``/dev/i2c-X`` is the Linux device node for your I2C controller connected to the display's DDC channel, and 1033``YY`` is the (hexadecimal) address of the MSTAR ISP port (address 0x49 is usually used). 1034Example that uses I2C controller /dev/i2c-1 and address 0x49:: 1035 1036 flashrom -p mstarddc_spi:dev=/dev/i2c-1:49 1037 1038It is also possible to inhibit the reset command that is normally sent to the display once the **flashrom** operation is 1039completed using the optional ``noreset`` parameter. A value of 1 prevents **flashrom** from sending the reset command. 1040Example that does not reset the display at the end of the operation:: 1041 1042 flashrom -p mstarddc_spi:dev=/dev/i2c-1:49,noreset=1 1043 1044Please note that sending the reset command is also inhibited if an error occurred during the operation. 1045To send the reset command afterwards, you can simply run **flashrom** once more, in chip probe mode (not specifying an operation), 1046without the ``noreset`` parameter, once the flash read/write operation you intended to perform has completed successfully. 1047 1048Please also note that the mstarddc_spi driver only works on Linux. 1049 1050 1051ch341a_spi programmer 1052^^^^^^^^^^^^^^^^^^^^^ 1053 1054The WCH CH341A programmer does not support any parameters currently. SPI frequency is fixed at 2 MHz, and CS0 is used 1055as per the device. 1056 1057 1058ch347_spi programmer 1059^^^^^^^^^^^^^^^^^^^^ 1060 1061An optional ``spispeed`` parameter could be used to specify the SPI speed. This parameter is available for the CH347T and CH347F device. 1062The default SPI speed is 15MHz if no value is specified. 1063Syntax is:: 1064 1065 flashrom -p ch347_spi:spispeed=value 1066 1067where ``value`` can be ``60M``, ``30M``, ``15M``, ``7.5M``, ``3.75M``, ``1.875M``, ``937.5K``, ``468.75K``. 1068 1069 1070ni845x_spi programmer 1071^^^^^^^^^^^^^^^^^^^^^ 1072 1073An optional ``voltage`` parameter could be used to specify the IO voltage. This parameter is available for the NI USB-8452 device. 1074The default unit is Volt if no unit is specified. You can use ``mV``, ``milliVolt``, ``V`` or ``Volt`` as unit specifier. 1075Syntax is:: 1076 1077 flashrom -p ni845x_spi:voltage=value 1078 1079where ``value`` can be ``1.2V``, ``1.5V``, ``1.8V``, ``2.5V``, ``3.3V`` or the equivalent in mV. 1080 1081In the case if none of the programmer's supported IO voltage is within the supported voltage range of the detected flash 1082chip the **flashrom** will abort the operation (to prevent damaging the flash chip). 1083You can override this behaviour by passing ``yes`` to the ``ignore_io_voltage_limits`` parameter 1084(for e.g. if you are using an external voltage translator circuit). Syntax is:: 1085 1086 flashrom -p ni845x_spi:ignore_io_voltage_limits=yes 1087 1088You can use the ``serial`` parameter to explicitly specify which connected NI USB-845x device should be used. You should 1089use your device's 7 digit hexadecimal serial number. Usage example to select the device with 1230A12 serial number:: 1090 1091 flashrom -p ni845x_spi:serial=1230A12 1092 1093An optional ``spispeed`` parameter specifies the frequency of the SPI bus. Syntax is:: 1094 1095 flashrom -p ni845x_spi:spispeed=frequency 1096 1097where ``frequency`` should a number corresponding to the desired frequency in kHz. 1098The maximum ``frequency`` is 12 MHz (12000 kHz) for the USB-8451 and 50 MHz (50000 kHz) for the USB-8452. 1099The default is a frequency of 1 MHz (1000 kHz). 1100 1101An optional ``cs`` parameter specifies which target chip select line should be used. Syntax is:: 1102 1103 flashrom -p ni845x_spi:csnumber=value 1104 1105where ``value`` should be between ``0`` and ``7``. By default the CS0 is used. 1106 1107 1108digilent_spi programmer 1109^^^^^^^^^^^^^^^^^^^^^^^ 1110 1111An optional ``spispeed`` parameter specifies the frequency of the SPI bus. Syntax is:: 1112 1113 flashrom -p digilent_spi:spispeed=frequency 1114 1115where ``frequency`` can be ``62.5k``, ``125k``, ``250k``, ``500k``, ``1M``, ``2M`` or ``4M`` (in Hz). 1116The default is a frequency of 4 MHz. 1117 1118 1119dirtyjtag_spi programmer 1120^^^^^^^^^^^^^^^^^^^^^^^^ 1121 1122An optional ``freq`` parameter specifies the frequency of the SPI bus. Syntax is:: 1123 1124 flashrom -p dirtyjtag_spi:spispeed=frequency 1125 1126where ``spispeed`` can be any value in hertz, kilohertz or megahertz supported by the programmer. 1127The default is a frequency of 100 KHz. 1128 1129 1130jlink_spi programmer 1131^^^^^^^^^^^^^^^^^^^^ 1132 1133This module supports SEGGER J-Link and compatible devices. 1134 1135The **MOSI** signal of the flash chip must be attached to **TDI** pin of the programmer, **MISO** to **TDO** and 1136**SCK** to **TCK**. The chip select (**CS**) signal of the flash chip can be attached to different pins of the 1137programmer which can be selected with the:: 1138 1139 flashrom -p jlink_spi:cs=pin 1140 1141syntax where ``pin`` can be either ``TRST``, ``RESET`` or ``TMS``. The default pin for chip select is ``RESET``. 1142Note that, when using ``RESET``, it is normal that the indicator LED blinks orange or red. 1143 1144Additionally, the ``Tref`` pin of the programmer must be attached to the logic level of the flash chip. 1145The programmer measures the voltage on this pin and generates the reference 1146voltage for its input comparators and adapts its output voltages to it. 1147 1148Pinout for devices with 20-pin JTAG connector:: 1149 1150 +-------+ 1151 | 1 2 | 1: VTref 2: 1152 | 3 4 | 3: TRST 4: GND 1153 | 5 6 | 5: TDI 6: GND 1154 +-+ 7 8 | 7: TMS 8: GND 1155 | 9 10 | 9: TCK 10: GND 1156 | 11 12 | 11: 12: GND 1157 +-+ 13 14 | 13: TDO 14: 1158 | 15 16 | 15: RESET 16: 1159 | 17 18 | 17: 18: 1160 | 19 20 | 19: PWR_5V 20: 1161 +-------+ 1162 1163If there is more than one compatible device connected, you can select which one should be used by specifying its serial 1164number with the:: 1165 1166 flashrom -p jlink_spi:serial=number 1167 1168syntax where ``number`` is the serial number of the device (which can be found for example in the output of ``lsusb -v``). 1169 1170The SPI speed can be selected by using the:: 1171 1172 flashrom -p jlink_spi:spispeed=frequency 1173 1174syntax where ``frequency`` is the SPI clock frequency in kHz. The maximum speed depends on the device in use. 1175 1176The ``power=on`` option can be used to activate the 5 V power supply (PWR_5V) of the J-Link during a flash operation. 1177 1178 1179stlinkv3_spi programmer 1180^^^^^^^^^^^^^^^^^^^^^^^ 1181 1182This module supports SPI flash programming through the STMicroelectronics STLINK V3 programmer/debugger's SPI bridge interface:: 1183 1184 flashrom -p stlinkv3_spi 1185 1186If there is more than one compatible device connected, you can select which one should be used by specifying its 1187serial number with the:: 1188 1189 flashrom -p stlinkv3_spi:serial=number 1190 1191syntax where ``number`` is the serial number of the device (which can be found for example in the output of ``lsusb -v``). 1192 1193The SPI speed can be selected by using the:: 1194 1195 flashrom -p stlinkv3_spi:spispeed=frequency 1196 1197syntax where ``frequency`` is the SPI clock frequency in kHz. If the passed frequency is not supported by the adapter 1198the nearest lower supported frequency will be used. 1199 1200 1201realtek_mst_i2c_spi, parade_lspcon and mediatek_i2c_spi programmers 1202^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1203 1204These programmers tunnel SPI commands through I2C-connected devices. The I2C bus over which communication occurs must be 1205specified either by device path with the ``devpath`` option:: 1206 1207 flashrom -p realtek_mst_i2c_spi:devpath=/dev/i2c-8 1208 1209or by a bus number with the ``bus`` option, which implies a device path like ``/dev/i2c-N`` where ``N`` is the specified 1210bus number:: 1211 1212 flashrom -p parade_lspcon:bus=8 1213 1214 1215realtek_mst_i2c_spi programmer 1216^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1217 1218This programmer supports SPI flash programming for chips attached to Realtek DisplayPort MST hubs, themselves accessed 1219through I2C (tunneling SPI flash commands through the MST hub's I2C connection with the host). 1220 1221 1222In-system programming (ISP) mode 1223"""""""""""""""""""""""""""""""" 1224 1225The ``reset_mcu`` and ``enter_isp`` options provide control over device mode changes, where each can be set to ``0`` 1226or ``1`` to enable or disable the corresponding mode transition. 1227 1228``enter_isp`` defaults to ``1``, and if enabled will issue commands to the MST hub when beginning operation to put it 1229into ISP mode. 1230 1231``reset_mcu`` defaults to ``0``, and if enabled will issue a reset command to the MST hub on programming completion, 1232causing it to exit ISP mode and to reload its own firmware from flash. 1233 1234``allow_brick`` defaults to ``no``, however must be set explicitly to ``yes`` to allow the driver to run if you are sure 1235you have a MST chip. 1236 1237The hub must be in ISP mode for SPI flash access to be possible, so it is usually only useful to disable ``enter_isp`` 1238if an earlier invocation avoided resetting it on completion. For instance, to erase the flash and rewrite it with the 1239contents of a file without resetting in between (which could render it nonfunctional if attempting to load firmware 1240from a blank flash):: 1241 1242 flashrom -p realtek_mst_i2c_spi:bus=0,enter_isp=1,reset_mcu=0 -E 1243 1244 flashrom -p realtek_mst_i2c_spi:bus=0,enter_isp=0,reset_mcu=1 -w new.bin 1245 1246 1247parade_lspcon programmer 1248^^^^^^^^^^^^^^^^^^^^^^^^ 1249 1250This programmer supports SPI flash programming for chips attached to Parade Technologies DisplayPort-to-HDMI level 1251shifter/protocol converters (LSPCONs), e.g. the PS175. Communication to the SPI flash is tunneled through the LSPCON 1252over I2C. 1253 1254 1255mediatek_i2c_spi programmer 1256^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1257 1258This programmer supports SPI flash programming for chips attached to some Mediatek display controllers, themselves 1259accessed through I2C (tunneling SPI flash commands through an I2C connection with the host). 1260 1261The programmer is designed to support the TSUMOP82JUQ integrated display driver and scaler as used in the Google Meet 1262Series One Desk 27 (which runs a version of ChromeOS and uses **flashrom** in its ``tsum-scaler-updater`` scripts that ship 1263with the OS). Other chips may use compatible protocols but have not been tested with this programmer, and external chip 1264IOs may need to be controlled through other non- **flashrom** means to configure the chip in order for it to operate as expected. 1265 1266``devpath`` and ``bus`` options select the I2C bus to use, as described previously. ``allow_brick`` defaults to ``no``, 1267and must explicitly be set to ``yes`` in order for the programmer to operate. This is required because there is no 1268mechanism in the driver to positively identify that a given I2C bus is actually connected to a supported device. 1269 1270 1271EXAMPLES 1272-------- 1273 1274To back up and update your BIOS, run:: 1275 1276 flashrom -p internal -r backup.rom -o backuplog.txt 1277 flashrom -p internal -w newbios.rom -o writelog.txt 1278 1279Please make sure to copy backup.rom to some external media before you try to write. That makes offline recovery easier. 1280 1281If writing fails and **flashrom** complains about the chip being in an unknown state, you can try to restore the backup by running:: 1282 1283 flashrom -p internal -w backup.rom -o restorelog.txt 1284 1285If you encounter any problems, please contact us and supply backuplog.txt, writelog.txt and restorelog.txt. 1286See section **BUGS** for contact info. 1287 1288 1289EXIT STATUS 1290----------- 1291 1292**flashrom** exits with 0 on success, 1 on most failures but with 3 if a call to mmap() fails. 1293 1294 1295REQUIREMENTS 1296------------ 1297 1298**flashrom** needs different access permissions for different programmers. 1299 1300* internal 1301 1302 * needs raw memory access 1303 * PCI configuration space access 1304 * raw I/O port access (x86) 1305 * MSR access (x86) 1306 1307* atavia 1308 1309 * needs PCI configuration space access 1310 1311* nic3com, nicrealtek, nicnatsemi 1312 1313 * need PCI configuration space read access 1314 * raw I/O port access 1315 1316* atahpt 1317 1318 * needs PCI configuration space access 1319 * raw I/O port access 1320 1321* gfxnvidia, drkaiser, it8212 1322 1323 * need PCI configuration space access 1324 * raw memory access 1325 1326* rayer_spi 1327 1328 * needs raw I/O port access 1329 1330* raiden_debug_spi 1331 1332 * needs access to the respective USB device via libusb API version 1.0 1333 1334* satasii, nicintel, nicintel_eeprom, nicintel_spi 1335 1336 * need PCI configuration space read access 1337 * raw memory access 1338 1339* satamv, atapromise 1340 1341 * need PCI configuration space read access 1342 * raw I/O port access 1343 * raw memory access 1344 1345* serprog 1346 1347 * needs TCP access to the network or userspace access to a serial port 1348 1349* buspirate_spi 1350 1351 * needs userspace access to a serial port 1352 1353* ft2232_spi, usbblaster_spi, pickit2_spi 1354 1355 * need access to the respective USB device via libusb API version 1.0 1356 1357* ch341a_spi, dediprog 1358 1359 * need access to the respective USB device via libusb API version 1.0 1360 1361* dummy 1362 1363 * needs no access permissions at all 1364 1365* internal, nic3com, nicrealtek, nicnatsemi, gfxnvidia, drkaiser, satasii, satamv, atahpt, atavia, atapromise, asm106x 1366 1367 * have to be run as superuser/root 1368 * need raw access permission 1369 1370* serprog, buspirate_spi, dediprog, usbblaster_spi, ft2232_spi, pickit2_spi, ch341a_spi, digilent_spi, dirtyjtag_spi 1371 1372 * can be run as normal user on most operating systems if appropriate device permissions are set 1373 1374* ogp 1375 1376 * needs PCI configuration space read access and raw memory access 1377 1378* realtek_mst_i2c_spi, parade_lspcon 1379 1380 * need userspace access to the selected I2C bus 1381 1382On OpenBSD, you can obtain raw access permission by setting:: 1383 1384 securelevel=-1 1385 1386in **/etc/rc.securelevel** and rebooting, or rebooting into single user mode. 1387 1388 1389BUGS 1390---- 1391 1392You can report bugs, ask us questions or send success reports via our communication channels listed here: 1393`Contact <https://www.flashrom.org/Contact>`_ 1394 1395Also, we provide a `pastebin service <https://paste.flashrom.org>`_ that is very useful to share logs without spamming 1396the communication channels. 1397 1398 1399Laptops 1400------- 1401 1402Using **flashrom** on older laptops is dangerous and may easily make your hardware unusable. **flashrom** will attempt to detect 1403if it is running on a susceptible laptop and restrict flash-chip probing for safety reasons. Please see the detailed 1404discussion of this topic and associated **flashrom** options in the **Laptops** paragraph in the **internal programmer** 1405subsection of the **PROGRAMMER-SPECIFIC INFORMATION** section and the information `in our wiki <https://flashrom.org/Laptops>`_. 1406 1407One-time programmable (OTP) memory and unique IDs 1408 1409Some flash chips contain OTP memory often denoted as **security registers**. They usually have a capacity in the range 1410of some bytes to a few hundred bytes and can be used to give devices unique IDs etc. **flashrom** is not able to read 1411or write these memories and may therefore not be able to duplicate a chip completely. For chip types known to include 1412OTP memories a warning is printed when they are detected. 1413 1414Similar to OTP memories are unique, factory programmed, unforgeable IDs. They are not modifiable by the user at all. 1415 1416 1417LICENSE 1418------- 1419 1420**flashrom** is covered by the GNU General Public License (GPL), version 2. Some files are additionally available 1421under any later version of the GPL. 1422 1423 1424COPYRIGHT 1425--------- 1426Please see the individual files. 1427 1428 1429AUTHORS 1430------- 1431 1432Andrew Morgan, Anastasia Klimchuk, Carl-Daniel Hailfinger, Claus Gindhart, David Borg, David Hendricks, Dominik Geyer, 1433Edward O'Callaghan, Eric Biederman, Giampiero Giancipoli, Helge Wagner, Idwer Vollering, Joe Bao, Joerg Fischer, 1434Joshua Roys, Kyösti Mälkki, Luc Verhaegen, Li-Ta Lo, Mark Marshall, Markus Boas, Mattias Mattsson, Michael Karcher, 1435Nikolay Petukhov, Patrick Georgi, Peter Lemenkov, Peter Stuge, Reinder E.N. de Haan, Ronald G. Minnich, Ronald Hoogenboom, 1436Sean Nelson, Stefan Reinauer, Stefan Tauner, Stefan Wildemann, Stephan Guilloux, Steven James, Urja Rannikko, Uwe Hermann, 1437Wang Qingpei, Yinghai Lu and others, please see the **flashrom** git history for details. 1438 1439All still active authors can be reached via `the mailing list <flashrom\@flashrom.org>`_. 1440 1441This manual page was written by `Uwe Hermann <uwe\@hermann-uwe.de>`_, Carl-Daniel Hailfinger, Stefan Tauner and others. 1442It is licensed under the terms of the GNU GPL (version 2 or later). 1443