1 /* 2 * SFF 8636 standards based QSFP EEPROM Field Definitions 3 * 4 * Vidya Ravipati <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 */ 12 13 #ifndef QSFP_H__ 14 #define QSFP_H__ 15 16 /*------------------------------------------------------------------------------ 17 * 18 * QSFP EEPROM data structures 19 * 20 * register info from SFF-8636 Rev 2.7 21 */ 22 23 /*------------------------------------------------------------------------------ 24 * 25 * Lower Memory Page 00h 26 * Measurement, Diagnostic and Control Functions 27 * 28 */ 29 /* Identifier - 0 */ 30 /* Values are defined under SFF8024_ID_OFFSET */ 31 #define SFF8636_ID_OFFSET 0x00 32 33 #define SFF8636_REV_COMPLIANCE_OFFSET 0x01 34 35 #define SFF8636_STATUS_2_OFFSET 0x02 36 /* Flat Memory:0- Paging, 1- Page 0 only */ 37 #define SFF8636_STATUS_PAGE_3_PRESENT (1 << 2) 38 #define SFF8636_STATUS_INTL_OUTPUT (1 << 1) 39 #define SFF8636_STATUS_DATA_NOT_READY (1 << 0) 40 41 /* Channel Status Interrupt Flags - 3-5 */ 42 #define SFF8636_LOS_AW_OFFSET 0x03 43 #define SFF8636_TX4_LOS_AW (1 << 7) 44 #define SFF8636_TX3_LOS_AW (1 << 6) 45 #define SFF8636_TX2_LOS_AW (1 << 5) 46 #define SFF8636_TX1_LOS_AW (1 << 4) 47 #define SFF8636_RX4_LOS_AW (1 << 3) 48 #define SFF8636_RX3_LOS_AW (1 << 2) 49 #define SFF8636_RX2_LOS_AW (1 << 1) 50 #define SFF8636_RX1_LOS_AW (1 << 0) 51 52 #define SFF8636_FAULT_AW_OFFSET 0x04 53 #define SFF8636_TX4_FAULT_AW (1 << 3) 54 #define SFF8636_TX3_FAULT_AW (1 << 2) 55 #define SFF8636_TX2_FAULT_AW (1 << 1) 56 #define SFF8636_TX1_FAULT_AW (1 << 0) 57 58 #define SFF8636_LOL_AW_OFFSET 0x05 59 60 /* Module Monitor Interrupt Flags - 6-8 */ 61 #define SFF8636_TEMP_AW_OFFSET 0x06 62 #define SFF8636_TEMP_HALARM_STATUS (1 << 7) 63 #define SFF8636_TEMP_LALARM_STATUS (1 << 6) 64 #define SFF8636_TEMP_HWARN_STATUS (1 << 5) 65 #define SFF8636_TEMP_LWARN_STATUS (1 << 4) 66 67 #define SFF8636_VCC_AW_OFFSET 0x07 68 #define SFF8636_VCC_HALARM_STATUS (1 << 7) 69 #define SFF8636_VCC_LALARM_STATUS (1 << 6) 70 #define SFF8636_VCC_HWARN_STATUS (1 << 5) 71 #define SFF8636_VCC_LWARN_STATUS (1 << 4) 72 73 /* Channel Monitor Interrupt Flags - 9-21 */ 74 #define SFF8636_RX_PWR_12_AW_OFFSET 0x09 75 #define SFF8636_RX_PWR_1_HALARM (1 << 7) 76 #define SFF8636_RX_PWR_1_LALARM (1 << 6) 77 #define SFF8636_RX_PWR_1_HWARN (1 << 5) 78 #define SFF8636_RX_PWR_1_LWARN (1 << 4) 79 #define SFF8636_RX_PWR_2_HALARM (1 << 3) 80 #define SFF8636_RX_PWR_2_LALARM (1 << 2) 81 #define SFF8636_RX_PWR_2_HWARN (1 << 1) 82 #define SFF8636_RX_PWR_2_LWARN (1 << 0) 83 84 #define SFF8636_RX_PWR_34_AW_OFFSET 0x0A 85 #define SFF8636_RX_PWR_3_HALARM (1 << 7) 86 #define SFF8636_RX_PWR_3_LALARM (1 << 6) 87 #define SFF8636_RX_PWR_3_HWARN (1 << 5) 88 #define SFF8636_RX_PWR_3_LWARN (1 << 4) 89 #define SFF8636_RX_PWR_4_HALARM (1 << 3) 90 #define SFF8636_RX_PWR_4_LALARM (1 << 2) 91 #define SFF8636_RX_PWR_4_HWARN (1 << 1) 92 #define SFF8636_RX_PWR_4_LWARN (1 << 0) 93 94 #define SFF8636_TX_BIAS_12_AW_OFFSET 0x0B 95 #define SFF8636_TX_BIAS_1_HALARM (1 << 7) 96 #define SFF8636_TX_BIAS_1_LALARM (1 << 6) 97 #define SFF8636_TX_BIAS_1_HWARN (1 << 5) 98 #define SFF8636_TX_BIAS_1_LWARN (1 << 4) 99 #define SFF8636_TX_BIAS_2_HALARM (1 << 3) 100 #define SFF8636_TX_BIAS_2_LALARM (1 << 2) 101 #define SFF8636_TX_BIAS_2_HWARN (1 << 1) 102 #define SFF8636_TX_BIAS_2_LWARN (1 << 0) 103 104 #define SFF8636_TX_BIAS_34_AW_OFFSET 0xC 105 #define SFF8636_TX_BIAS_3_HALARM (1 << 7) 106 #define SFF8636_TX_BIAS_3_LALARM (1 << 6) 107 #define SFF8636_TX_BIAS_3_HWARN (1 << 5) 108 #define SFF8636_TX_BIAS_3_LWARN (1 << 4) 109 #define SFF8636_TX_BIAS_4_HALARM (1 << 3) 110 #define SFF8636_TX_BIAS_4_LALARM (1 << 2) 111 #define SFF8636_TX_BIAS_4_HWARN (1 << 1) 112 #define SFF8636_TX_BIAS_4_LWARN (1 << 0) 113 114 #define SFF8636_TX_PWR_12_AW_OFFSET 0x0D 115 #define SFF8636_TX_PWR_1_HALARM (1 << 7) 116 #define SFF8636_TX_PWR_1_LALARM (1 << 6) 117 #define SFF8636_TX_PWR_1_HWARN (1 << 5) 118 #define SFF8636_TX_PWR_1_LWARN (1 << 4) 119 #define SFF8636_TX_PWR_2_HALARM (1 << 3) 120 #define SFF8636_TX_PWR_2_LALARM (1 << 2) 121 #define SFF8636_TX_PWR_2_HWARN (1 << 1) 122 #define SFF8636_TX_PWR_2_LWARN (1 << 0) 123 124 #define SFF8636_TX_PWR_34_AW_OFFSET 0x0E 125 #define SFF8636_TX_PWR_3_HALARM (1 << 7) 126 #define SFF8636_TX_PWR_3_LALARM (1 << 6) 127 #define SFF8636_TX_PWR_3_HWARN (1 << 5) 128 #define SFF8636_TX_PWR_3_LWARN (1 << 4) 129 #define SFF8636_TX_PWR_4_HALARM (1 << 3) 130 #define SFF8636_TX_PWR_4_LALARM (1 << 2) 131 #define SFF8636_TX_PWR_4_HWARN (1 << 1) 132 #define SFF8636_TX_PWR_4_LWARN (1 << 0) 133 134 /* Module Monitoring Values - 22-33 */ 135 #define SFF8636_TEMP_CURR 0x16 136 #define SFF8636_TEMP_MSB_OFFSET 0x16 137 #define SFF8636_TEMP_LSB_OFFSET 0x17 138 139 #define SFF8636_VCC_CURR 0x1A 140 #define SFF8636_VCC_MSB_OFFSET 0x1A 141 #define SFF8636_VCC_LSB_OFFSET 0x1B 142 143 /* Channel Monitoring Values - 34-81 */ 144 #define SFF8636_RX_PWR_1_OFFSET 0x22 145 #define SFF8636_RX_PWR_2_OFFSET 0x24 146 #define SFF8636_RX_PWR_3_OFFSET 0x26 147 #define SFF8636_RX_PWR_4_OFFSET 0x28 148 149 #define SFF8636_TX_BIAS_1_OFFSET 0x2A 150 #define SFF8636_TX_BIAS_2_OFFSET 0x2C 151 #define SFF8636_TX_BIAS_3_OFFSET 0x2E 152 #define SFF8636_TX_BIAS_4_OFFSET 0x30 153 154 #define SFF8636_TX_PWR_1_OFFSET 0x32 155 #define SFF8636_TX_PWR_2_OFFSET 0x34 156 #define SFF8636_TX_PWR_3_OFFSET 0x36 157 #define SFF8636_TX_PWR_4_OFFSET 0x38 158 159 /* Control Bytes - 86 - 99 */ 160 #define SFF8636_TX_DISABLE_OFFSET 0x56 161 #define SFF8636_TX_DISABLE_4 (1 << 3) 162 #define SFF8636_TX_DISABLE_3 (1 << 2) 163 #define SFF8636_TX_DISABLE_2 (1 << 1) 164 #define SFF8636_TX_DISABLE_1 (1 << 0) 165 166 #define SFF8636_RX_RATE_SELECT_OFFSET 0x57 167 #define SFF8636_RX_RATE_SELECT_4_MASK (3 << 6) 168 #define SFF8636_RX_RATE_SELECT_3_MASK (3 << 4) 169 #define SFF8636_RX_RATE_SELECT_2_MASK (3 << 2) 170 #define SFF8636_RX_RATE_SELECT_1_MASK (3 << 0) 171 172 #define SFF8636_TX_RATE_SELECT_OFFSET 0x58 173 #define SFF8636_TX_RATE_SELECT_4_MASK (3 << 6) 174 #define SFF8636_TX_RATE_SELECT_3_MASK (3 << 4) 175 #define SFF8636_TX_RATE_SELECT_2_MASK (3 << 2) 176 #define SFF8636_TX_RATE_SELECT_1_MASK (3 << 0) 177 178 #define SFF8636_RX_APP_SELECT_4_OFFSET 0x58 179 #define SFF8636_RX_APP_SELECT_3_OFFSET 0x59 180 #define SFF8636_RX_APP_SELECT_2_OFFSET 0x5A 181 #define SFF8636_RX_APP_SELECT_1_OFFSET 0x5B 182 183 #define SFF8636_PWR_MODE_OFFSET 0x5D 184 #define SFF8636_HIGH_PWR_ENABLE (1 << 2) 185 #define SFF8636_LOW_PWR_SET (1 << 1) 186 #define SFF8636_PWR_OVERRIDE (1 << 0) 187 188 #define SFF8636_TX_APP_SELECT_4_OFFSET 0x5E 189 #define SFF8636_TX_APP_SELECT_3_OFFSET 0x5F 190 #define SFF8636_TX_APP_SELECT_2_OFFSET 0x60 191 #define SFF8636_TX_APP_SELECT_1_OFFSET 0x61 192 193 #define SFF8636_LOS_MASK_OFFSET 0x64 194 #define SFF8636_TX_LOS_4_MASK (1 << 7) 195 #define SFF8636_TX_LOS_3_MASK (1 << 6) 196 #define SFF8636_TX_LOS_2_MASK (1 << 5) 197 #define SFF8636_TX_LOS_1_MASK (1 << 4) 198 #define SFF8636_RX_LOS_4_MASK (1 << 3) 199 #define SFF8636_RX_LOS_3_MASK (1 << 2) 200 #define SFF8636_RX_LOS_2_MASK (1 << 1) 201 #define SFF8636_RX_LOS_1_MASK (1 << 0) 202 203 #define SFF8636_FAULT_MASK_OFFSET 0x65 204 #define SFF8636_TX_FAULT_1_MASK (1 << 3) 205 #define SFF8636_TX_FAULT_2_MASK (1 << 2) 206 #define SFF8636_TX_FAULT_3_MASK (1 << 1) 207 #define SFF8636_TX_FAULT_4_MASK (1 << 0) 208 209 #define SFF8636_TEMP_MASK_OFFSET 0x67 210 #define SFF8636_TEMP_HALARM_MASK (1 << 7) 211 #define SFF8636_TEMP_LALARM_MASK (1 << 6) 212 #define SFF8636_TEMP_HWARN_MASK (1 << 5) 213 #define SFF8636_TEMP_LWARN_MASK (1 << 4) 214 215 #define SFF8636_VCC_MASK_OFFSET 0x68 216 #define SFF8636_VCC_HALARM_MASK (1 << 7) 217 #define SFF8636_VCC_LALARM_MASK (1 << 6) 218 #define SFF8636_VCC_HWARN_MASK (1 << 5) 219 #define SFF8636_VCC_LWARN_MASK (1 << 4) 220 221 /*------------------------------------------------------------------------------ 222 * 223 * Upper Memory Page 00h 224 * Serial ID - Base ID, Extended ID and Vendor Specific ID fields 225 * 226 */ 227 /* Identifier - 128 */ 228 /* Identifier values same as Lower Memory Page 00h */ 229 #define SFF8636_UPPER_PAGE_0_ID_OFFSET 0x80 230 231 /* Extended Identifier - 128 */ 232 #define SFF8636_EXT_ID_OFFSET 0x81 233 #define SFF8636_EXT_ID_PWR_CLASS_MASK 0xC0 234 #define SFF8636_EXT_ID_PWR_CLASS_1 (0 << 6) 235 #define SFF8636_EXT_ID_PWR_CLASS_2 (1 << 6) 236 #define SFF8636_EXT_ID_PWR_CLASS_3 (2 << 6) 237 #define SFF8636_EXT_ID_PWR_CLASS_4 (3 << 6) 238 #define SFF8636_EXT_ID_CLIE_MASK 0x10 239 #define SFF8636_EXT_ID_CLIEI_CODE_PRESENT (1 << 4) 240 #define SFF8636_EXT_ID_CDR_TX_MASK 0x08 241 #define SFF8636_EXT_ID_CDR_TX_PRESENT (1 << 3) 242 #define SFF8636_EXT_ID_CDR_RX_MASK 0x04 243 #define SFF8636_EXT_ID_CDR_RX_PRESENT (1 << 2) 244 #define SFF8636_EXT_ID_EPWR_CLASS_MASK 0x03 245 #define SFF8636_EXT_ID_PWR_CLASS_LEGACY 0 246 #define SFF8636_EXT_ID_PWR_CLASS_5 1 247 #define SFF8636_EXT_ID_PWR_CLASS_6 2 248 #define SFF8636_EXT_ID_PWR_CLASS_7 3 249 250 /* Connector Values offset - 130 */ 251 /* Values are defined under SFF8024_CTOR */ 252 #define SFF8636_CTOR_OFFSET 0x82 253 #define SFF8636_CTOR_UNKNOWN 0x00 254 #define SFF8636_CTOR_SC 0x01 255 #define SFF8636_CTOR_FC_STYLE_1 0x02 256 #define SFF8636_CTOR_FC_STYLE_2 0x03 257 #define SFF8636_CTOR_BNC_TNC 0x04 258 #define SFF8636_CTOR_FC_COAX 0x05 259 #define SFF8636_CTOR_FIBER_JACK 0x06 260 #define SFF8636_CTOR_LC 0x07 261 #define SFF8636_CTOR_MT_RJ 0x08 262 #define SFF8636_CTOR_MU 0x09 263 #define SFF8636_CTOR_SG 0x0A 264 #define SFF8636_CTOR_OPT_PT 0x0B 265 #define SFF8636_CTOR_MPO 0x0C 266 /* 0D-1Fh --- Reserved */ 267 #define SFF8636_CTOR_HSDC_II 0x20 268 #define SFF8636_CTOR_COPPER_PT 0x21 269 #define SFF8636_CTOR_RJ45 0x22 270 #define SFF8636_CTOR_NO_SEPARABLE 0x23 271 #define SFF8636_CTOR_MXC_2X16 0x24 272 273 /* Specification Compliance - 131-138 */ 274 /* Ethernet Compliance Codes - 131 */ 275 #define SFF8636_ETHERNET_COMP_OFFSET 0x83 276 #define SFF8636_ETHERNET_RSRVD (1 << 7) 277 #define SFF8636_ETHERNET_10G_LRM (1 << 6) 278 #define SFF8636_ETHERNET_10G_LR (1 << 5) 279 #define SFF8636_ETHERNET_10G_SR (1 << 4) 280 #define SFF8636_ETHERNET_40G_CR4 (1 << 3) 281 #define SFF8636_ETHERNET_40G_SR4 (1 << 2) 282 #define SFF8636_ETHERNET_40G_LR4 (1 << 1) 283 #define SFF8636_ETHERNET_40G_ACTIVE (1 << 0) 284 285 /* SONET Compliance Codes - 132 */ 286 #define SFF8636_SONET_COMP_OFFSET 0x84 287 #define SFF8636_SONET_40G_OTN (1 << 3) 288 #define SFF8636_SONET_OC48_LR (1 << 2) 289 #define SFF8636_SONET_OC48_IR (1 << 1) 290 #define SFF8636_SONET_OC48_SR (1 << 0) 291 292 /* SAS/SATA Complaince Codes - 133 */ 293 #define SFF8636_SAS_COMP_OFFSET 0x85 294 #define SFF8636_SAS_12G (1 << 6) 295 #define SFF8636_SAS_6G (1 << 5) 296 #define SFF8636_SAS_3G (1 << 4) 297 298 /* Gigabit Ethernet Compliance Codes - 134 */ 299 #define SFF8636_GIGE_COMP_OFFSET 0x86 300 #define SFF8636_GIGE_1000_BASE_T (1 << 3) 301 #define SFF8636_GIGE_1000_BASE_CX (1 << 2) 302 #define SFF8636_GIGE_1000_BASE_LX (1 << 1) 303 #define SFF8636_GIGE_1000_BASE_SX (1 << 0) 304 305 /* Fibre Channel Link length/Transmitter Tech. - 135,136 */ 306 #define SFF8636_FC_LEN_OFFSET 0x87 307 #define SFF8636_FC_LEN_VERY_LONG (1 << 7) 308 #define SFF8636_FC_LEN_SHORT (1 << 6) 309 #define SFF8636_FC_LEN_INT (1 << 5) 310 #define SFF8636_FC_LEN_LONG (1 << 4) 311 #define SFF8636_FC_LEN_MED (1 << 3) 312 #define SFF8636_FC_TECH_LONG_LC (1 << 1) 313 #define SFF8636_FC_TECH_ELEC_INTER (1 << 0) 314 315 #define SFF8636_FC_TECH_OFFSET 0x88 316 #define SFF8636_FC_TECH_ELEC_INTRA (1 << 7) 317 #define SFF8636_FC_TECH_SHORT_WO_OFC (1 << 6) 318 #define SFF8636_FC_TECH_SHORT_W_OFC (1 << 5) 319 #define SFF8636_FC_TECH_LONG_LL (1 << 4) 320 321 /* Fibre Channel Transmitter Media - 137 */ 322 #define SFF8636_FC_TRANS_MEDIA_OFFSET 0x89 323 /* Twin Axial Pair */ 324 #define SFF8636_FC_TRANS_MEDIA_TW (1 << 7) 325 /* Shielded Twisted Pair */ 326 #define SFF8636_FC_TRANS_MEDIA_TP (1 << 6) 327 /* Miniature Coax */ 328 #define SFF8636_FC_TRANS_MEDIA_MI (1 << 5) 329 /* Video Coax */ 330 #define SFF8636_FC_TRANS_MEDIA_TV (1 << 4) 331 /* Multi-mode 62.5m */ 332 #define SFF8636_FC_TRANS_MEDIA_M6 (1 << 3) 333 /* Multi-mode 50m */ 334 #define SFF8636_FC_TRANS_MEDIA_M5 (1 << 2) 335 /* Multi-mode 50um */ 336 #define SFF8636_FC_TRANS_MEDIA_OM3 (1 << 1) 337 /* Single Mode */ 338 #define SFF8636_FC_TRANS_MEDIA_SM (1 << 0) 339 340 /* Fibre Channel Speed - 138 */ 341 #define SFF8636_FC_SPEED_OFFSET 0x8A 342 #define SFF8636_FC_SPEED_1200_MBPS (1 << 7) 343 #define SFF8636_FC_SPEED_800_MBPS (1 << 6) 344 #define SFF8636_FC_SPEED_1600_MBPS (1 << 5) 345 #define SFF8636_FC_SPEED_400_MBPS (1 << 4) 346 #define SFF8636_FC_SPEED_200_MBPS (1 << 2) 347 #define SFF8636_FC_SPEED_100_MBPS (1 << 0) 348 349 /* Encoding - 139 */ 350 /* Values are defined under SFF8024_ENCODING */ 351 #define SFF8636_ENCODING_OFFSET 0x8B 352 #define SFF8636_ENCODING_MANCHESTER 0x06 353 #define SFF8636_ENCODING_64B66B 0x05 354 #define SFF8636_ENCODING_SONET 0x04 355 #define SFF8636_ENCODING_NRZ 0x03 356 #define SFF8636_ENCODING_4B5B 0x02 357 #define SFF8636_ENCODING_8B10B 0x01 358 #define SFF8636_ENCODING_UNSPEC 0x00 359 360 /* BR, Nominal - 140 */ 361 #define SFF8636_BR_NOMINAL_OFFSET 0x8C 362 363 /* Extended RateSelect - 141 */ 364 #define SFF8636_EXT_RS_OFFSET 0x8D 365 #define SFF8636_EXT_RS_V1 (1 << 0) 366 367 /* Length (Standard SM Fiber)-km - 142 */ 368 #define SFF8636_SM_LEN_OFFSET 0x8E 369 370 /* Length (OM3)-Unit 2m - 143 */ 371 #define SFF8636_OM3_LEN_OFFSET 0x8F 372 373 /* Length (OM2)-Unit 1m - 144 */ 374 #define SFF8636_OM2_LEN_OFFSET 0x90 375 376 /* Length (OM1)-Unit 1m - 145 */ 377 #define SFF8636_OM1_LEN_OFFSET 0x91 378 379 /* Cable Assembly Length -Unit 1m - 146 */ 380 #define SFF8636_CBL_LEN_OFFSET 0x92 381 382 /* Device Technology - 147 */ 383 #define SFF8636_DEVICE_TECH_OFFSET 0x93 384 /* Transmitter Technology */ 385 #define SFF8636_TRANS_TECH_MASK 0xF0 386 /* Copper cable, linear active equalizers */ 387 #define SFF8636_TRANS_COPPER_LNR_EQUAL (15 << 4) 388 /* Copper cable, near end limiting active equalizers */ 389 #define SFF8636_TRANS_COPPER_NEAR_EQUAL (14 << 4) 390 /* Copper cable, far end limiting active equalizers */ 391 #define SFF8636_TRANS_COPPER_FAR_EQUAL (13 << 4) 392 /* Copper cable, near & far end limiting active equalizers */ 393 #define SFF8636_TRANS_COPPER_LNR_FAR_EQUAL (12 << 4) 394 /* Copper cable, passive equalized */ 395 #define SFF8636_TRANS_COPPER_PAS_EQUAL (11 << 4) 396 /* Copper cable, unequalized */ 397 #define SFF8636_TRANS_COPPER_PAS_UNEQUAL (10 << 4) 398 /* 1490 nm DFB */ 399 #define SFF8636_TRANS_1490_DFB (9 << 4) 400 /* Others */ 401 #define SFF8636_TRANS_OTHERS (8 << 4) 402 /* 1550 nm EML */ 403 #define SFF8636_TRANS_1550_EML (7 << 4) 404 /* 1310 nm EML */ 405 #define SFF8636_TRANS_1310_EML (6 << 4) 406 /* 1550 nm DFB */ 407 #define SFF8636_TRANS_1550_DFB (5 << 4) 408 /* 1310 nm DFB */ 409 #define SFF8636_TRANS_1310_DFB (4 << 4) 410 /* 1310 nm FP */ 411 #define SFF8636_TRANS_1310_FP (3 << 4) 412 /* 1550 nm VCSEL */ 413 #define SFF8636_TRANS_1550_VCSEL (2 << 4) 414 /* 1310 nm VCSEL */ 415 #define SFF8636_TRANS_1310_VCSEL (1 << 4) 416 /* 850 nm VCSEL */ 417 #define SFF8636_TRANS_850_VCSEL (0 << 4) 418 419 /* Active/No wavelength control */ 420 #define SFF8636_DEV_TECH_ACTIVE_WAVE_LEN (1 << 3) 421 /* Cooled transmitter */ 422 #define SFF8636_DEV_TECH_COOL_TRANS (1 << 2) 423 /* APD/Pin Detector */ 424 #define SFF8636_DEV_TECH_APD_DETECTOR (1 << 1) 425 /* Transmitter tunable */ 426 #define SFF8636_DEV_TECH_TUNABLE (1 << 0) 427 428 /* Vendor Name - 148-163 */ 429 #define SFF8636_VENDOR_NAME_START_OFFSET 0x94 430 #define SFF8636_VENDOR_NAME_END_OFFSET 0xA3 431 432 /* Extended Module Codes - 164 */ 433 #define SFF8636_EXT_MOD_CODE_OFFSET 0xA4 434 #define SFF8636_EXT_MOD_INFINIBAND_EDR (1 << 4) 435 #define SFF8636_EXT_MOD_INFINIBAND_FDR (1 << 3) 436 #define SFF8636_EXT_MOD_INFINIBAND_QDR (1 << 2) 437 #define SFF8636_EXT_MOD_INFINIBAND_DDR (1 << 1) 438 #define SFF8636_EXT_MOD_INFINIBAND_SDR (1 << 0) 439 440 /* Vendor OUI - 165-167 */ 441 #define SFF8636_VENDOR_OUI_OFFSET 0xA5 442 #define SFF8636_VENDOR_OUI_LEN 3 443 444 /* Vendor OUI - 165-167 */ 445 #define SFF8636_VENDOR_PN_START_OFFSET 0xA8 446 #define SFF8636_VENDOR_PN_END_OFFSET 0xB7 447 448 /* Vendor Revision - 184-185 */ 449 #define SFF8636_VENDOR_REV_START_OFFSET 0xB8 450 #define SFF8636_VENDOR_REV_END_OFFSET 0xB9 451 452 /* Wavelength - 186-187 */ 453 #define SFF8636_WAVELEN_HIGH_BYTE_OFFSET 0xBA 454 #define SFF8636_WAVELEN_LOW_BYTE_OFFSET 0xBB 455 456 /* Wavelength Tolerance- 188-189 */ 457 #define SFF8636_WAVE_TOL_HIGH_BYTE_OFFSET 0xBC 458 #define SFF8636_WAVE_TOL_LOW_BYTE_OFFSET 0xBD 459 460 /* Max case temp - Other than 70 C - 190 */ 461 #define SFF8636_MAXCASE_TEMP_OFFSET 0xBE 462 463 /* CC_BASE - 191 */ 464 #define SFF8636_CC_BASE_OFFSET 0xBF 465 466 /* Option Values - 192-195 */ 467 #define SFF8636_OPTION_1_OFFSET 0xC0 468 #define SFF8636_ETHERNET_UNSPECIFIED 0x00 469 #define SFF8636_ETHERNET_100G_AOC 0x01 470 #define SFF8636_ETHERNET_100G_SR4 0x02 471 #define SFF8636_ETHERNET_100G_LR4 0x03 472 #define SFF8636_ETHERNET_100G_ER4 0x04 473 #define SFF8636_ETHERNET_100G_SR10 0x05 474 #define SFF8636_ETHERNET_100G_CWDM4_FEC 0x06 475 #define SFF8636_ETHERNET_100G_PSM4 0x07 476 #define SFF8636_ETHERNET_100G_ACC 0x08 477 #define SFF8636_ETHERNET_100G_CWDM4_NO_FEC 0x09 478 #define SFF8636_ETHERNET_100G_RSVD1 0x0A 479 #define SFF8636_ETHERNET_100G_CR4 0x0B 480 #define SFF8636_ETHERNET_25G_CR_CA_S 0x0C 481 #define SFF8636_ETHERNET_25G_CR_CA_N 0x0D 482 #define SFF8636_ETHERNET_40G_ER4 0x10 483 #define SFF8636_ETHERNET_4X10_SR 0x11 484 #define SFF8636_ETHERNET_40G_PSM4 0x12 485 #define SFF8636_ETHERNET_G959_P1I1_2D1 0x13 486 #define SFF8636_ETHERNET_G959_P1S1_2D2 0x14 487 #define SFF8636_ETHERNET_G959_P1L1_2D2 0x15 488 #define SFF8636_ETHERNET_10GT_SFI 0x16 489 #define SFF8636_ETHERNET_100G_CLR4 0x17 490 #define SFF8636_ETHERNET_100G_AOC2 0x18 491 #define SFF8636_ETHERNET_100G_ACC2 0x19 492 493 #define SFF8636_ETHERNET_100GE_DWDM2 0x1A 494 #define SFF8636_ETHERNET_100G_1550NM_WDM 0x1B 495 #define SFF8636_ETHERNET_10G_BASET_SR 0x1C 496 #define SFF8636_ETHERNET_5G_BASET 0x1D 497 #define SFF8636_ETHERNET_2HALFG_BASET 0x1E 498 #define SFF8636_ETHERNET_40G_SWDM4 0x1F 499 #define SFF8636_ETHERNET_100G_SWDM4 0x20 500 #define SFF8636_ETHERNET_100G_PAM4_BIDI 0x21 501 #define SFF8636_ETHERNET_4WDM10_MSA 0x22 502 #define SFF8636_ETHERNET_4WDM20_MSA 0x23 503 #define SFF8636_ETHERNET_4WDM40_MSA 0x24 504 #define SFF8636_ETHERNET_100G_DR 0x25 505 #define SFF8636_ETHERNET_100G_FR_NOFEC 0x26 506 #define SFF8636_ETHERNET_100G_LR_NOFEC 0x27 507 /* 28h-2Fh reserved */ 508 #define SFF8636_ETHERNET_200G_ACC1 0x30 509 #define SFF8636_ETHERNET_200G_AOC1 0x31 510 #define SFF8636_ETHERNET_200G_ACC2 0x32 511 #define SFF8636_ETHERNET_200G_A0C2 0x33 512 /* 34h-3Fh reserved */ 513 #define SFF8636_ETHERNET_200G_CR4 0x40 514 #define SFF8636_ETHERNET_200G_SR4 0x41 515 #define SFF8636_ETHERNET_200G_DR4 0x42 516 #define SFF8636_ETHERNET_200G_FR4 0x43 517 #define SFF8636_ETHERNET_200G_PSM4 0x44 518 #define SFF8636_ETHERNET_50G_LR 0x45 519 #define SFF8636_ETHERNET_200G_LR4 0x46 520 /* 47h-4Fh reserved */ 521 #define SFF8636_ETHERNET_64G_EA 0x50 522 #define SFF8636_ETHERNET_64G_SW 0x51 523 #define SFF8636_ETHERNET_64G_LW 0x52 524 #define SFF8636_ETHERNET_128FC_EA 0x53 525 #define SFF8636_ETHERNET_128FC_SW 0x54 526 #define SFF8636_ETHERNET_128FC_LW 0x55 527 /* 56h-5Fh reserved */ 528 529 #define SFF8636_OPTION_2_OFFSET 0xC1 530 /* Tx input equalizers auto-adaptive */ 531 #define SFF8636_O2_TX_EQ_AUTO (1 << 3) 532 /* Rx output amplitude */ 533 #define SFF8636_O2_RX_OUTPUT_AMP (1 << 0) 534 #define SFF8636_OPTION_3_OFFSET 0xC2 535 /* Tx CDR Loss of Lock */ 536 #define SFF8636_O3_TX_LOL (1 << 5) 537 /* Rx CDR Loss of Lock */ 538 #define SFF8636_O3_RX_LOL (1 << 4) 539 /* Rx Squelch Disable */ 540 #define SFF8636_O3_RX_SQL_DSBL (1 << 3) 541 /* Rx Output Disable capable */ 542 #define SFF8636_O3_RX_OUTPUT_DSBL (1 << 2) 543 /* Tx Squelch Disable */ 544 #define SFF8636_O3_TX_SQL_DSBL (1 << 1) 545 /* Tx Squelch Impl */ 546 #define SFF8636_O3_TX_SQL_IMPL (1 << 0) 547 #define SFF8636_OPTION_4_OFFSET 0xC3 548 /* Memory Page 02 present */ 549 #define SFF8636_O4_PAGE_02_PRESENT (1 << 7) 550 /* Memory Page 01 present */ 551 #define SFF8636_O4_PAGE_01_PRESENT (1 << 6) 552 /* Rate Select implemented */ 553 #define SFF8636_O4_RATE_SELECT (1 << 5) 554 /* Tx_DISABLE implemented */ 555 #define SFF8636_O4_TX_DISABLE (1 << 4) 556 /* Tx_FAULT implemented */ 557 #define SFF8636_O4_TX_FAULT (1 << 3) 558 /* Tx Squelch implemented */ 559 #define SFF8636_O4_TX_SQUELCH (1 << 2) 560 /* Tx Loss of Signal */ 561 #define SFF8636_O4_TX_LOS (1 << 1) 562 563 /* Vendor SN - 196-211 */ 564 #define SFF8636_VENDOR_SN_START_OFFSET 0xC4 565 #define SFF8636_VENDOR_SN_END_OFFSET 0xD3 566 567 /* Vendor Date - 212-219 */ 568 #define SFF8636_DATE_YEAR_OFFSET 0xD4 569 #define SFF8636_DATE_YEAR_LEN 2 570 #define SFF8636_DATE_MONTH_OFFSET 0xD6 571 #define SFF8636_DATE_MONTH_LEN 2 572 #define SFF8636_DATE_DAY_OFFSET 0xD8 573 #define SFF8636_DATE_DAY_LEN 2 574 #define SFF8636_DATE_VENDOR_LOT_OFFSET 0xDA 575 #define SFF8636_DATE_VENDOR_LOT_LEN 2 576 577 /* Diagnostic Monitoring Type - 220 */ 578 #define SFF8636_DIAG_TYPE_OFFSET 0xDC 579 #define SFF8636_RX_PWR_TYPE_MASK 0x8 580 #define SFF8636_RX_PWR_TYPE_AVG_PWR (1 << 3) 581 #define SFF8636_RX_PWR_TYPE_OMA (0 << 3) 582 #define SFF8636_TX_PWR_TYPE_MASK 0x4 583 #define SFF8636_TX_PWR_TYPE_AVG_PWR (1 << 2) 584 585 /* Enhanced Options - 221 */ 586 #define SFF8636_ENH_OPTIONS_OFFSET 0xDD 587 #define SFF8636_RATE_SELECT_EXT_SUPPORT (1 << 3) 588 #define SFF8636_RATE_SELECT_APP_TABLE_SUPPORT (1 << 2) 589 590 /* Check code - 223 */ 591 #define SFF8636_CC_EXT_OFFSET 0xDF 592 #define SFF8636_CC_EXT_LEN 1 593 594 /*------------------------------------------------------------------------------ 595 * 596 * Upper Memory Page 03h 597 * Contains module thresholds, channel thresholds and masks, 598 * and optional channel controls 599 * 600 * Offset - Page Num(3) * PageSize(0x80) + Page offset 601 */ 602 603 /* 3 * 128 + Lower page 00h(128) */ 604 #define SFF8636_PAGE03H_OFFSET (128 * 4) 605 606 /* Module Thresholds (48 Bytes) 128-175 */ 607 /* MSB at low address, LSB at high address */ 608 #define SFF8636_TEMP_HALRM 0x80 609 #define SFF8636_TEMP_LALRM 0x82 610 #define SFF8636_TEMP_HWARN 0x84 611 #define SFF8636_TEMP_LWARN 0x86 612 613 #define SFF8636_VCC_HALRM 0x90 614 #define SFF8636_VCC_LALRM 0x92 615 #define SFF8636_VCC_HWARN 0x94 616 #define SFF8636_VCC_LWARN 0x96 617 618 #define SFF8636_RX_PWR_HALRM 0xB0 619 #define SFF8636_RX_PWR_LALRM 0xB2 620 #define SFF8636_RX_PWR_HWARN 0xB4 621 #define SFF8636_RX_PWR_LWARN 0xB6 622 623 #define SFF8636_TX_BIAS_HALRM 0xB8 624 #define SFF8636_TX_BIAS_LALRM 0xBA 625 #define SFF8636_TX_BIAS_HWARN 0xBC 626 #define SFF8636_TX_BIAS_LWARN 0xBE 627 628 #define SFF8636_TX_PWR_HALRM 0xC0 629 #define SFF8636_TX_PWR_LALRM 0xC2 630 #define SFF8636_TX_PWR_HWARN 0xC4 631 #define SFF8636_TX_PWR_LWARN 0xC6 632 633 #define ETH_MODULE_SFF_8636_MAX_LEN 640 634 #define ETH_MODULE_SFF_8436_MAX_LEN 640 635 636 #endif /* QSFP_H__ */ 637