1 #include <stdio.h>
2 #include <stdint.h>
3 #include <stdlib.h>
4 #include <string.h>
5 #include <alloca.h>
6
7 #include <errno.h>
8 #include <sys/types.h>
9 #include <sys/sysctl.h>
10 #include <mach/machine.h>
11
12 #include <cpuinfo.h>
13 #include <mach/api.h>
14 #include <cpuinfo/internal-api.h>
15 #include <cpuinfo/log.h>
16
17 /* Polyfill recent CPUFAMILY_ARM_* values for older SDKs */
18 #ifndef CPUFAMILY_ARM_VORTEX_TEMPEST
19 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07D34B9F
20 #endif
21 #ifndef CPUFAMILY_ARM_LIGHTNING_THUNDER
22 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504D2
23 #endif
24 #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
25 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3
26 #endif
27 #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
28 #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
29 #endif
30
31 struct cpuinfo_arm_isa cpuinfo_isa = {
32 .aes = true,
33 .sha1 = true,
34 .sha2 = true,
35 .pmull = true,
36 .crc32 = true,
37 };
38
get_sys_info(int type_specifier,const char * name)39 static uint32_t get_sys_info(int type_specifier, const char* name) {
40 size_t size = 0;
41 uint32_t result = 0;
42 int mib[2] = { CTL_HW, type_specifier };
43 if (sysctl(mib, 2, NULL, &size, NULL, 0) != 0) {
44 cpuinfo_log_info("sysctl(\"%s\") failed: %s", name, strerror(errno));
45 } else if (size == sizeof(uint32_t)) {
46 sysctl(mib, 2, &result, &size, NULL, 0);
47 cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", name, result, size);
48 } else {
49 cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", name);
50 }
51 return result;
52 }
53
get_sys_info_by_name(const char * type_specifier)54 static uint32_t get_sys_info_by_name(const char* type_specifier) {
55 size_t size = 0;
56 uint32_t result = 0;
57 if (sysctlbyname(type_specifier, NULL, &size, NULL, 0) != 0) {
58 cpuinfo_log_info("sysctlbyname(\"%s\") failed: %s", type_specifier, strerror(errno));
59 } else if (size == sizeof(uint32_t)) {
60 sysctlbyname(type_specifier, &result, &size, NULL, 0);
61 cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", type_specifier, result, size);
62 } else {
63 cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", type_specifier);
64 }
65 return result;
66 }
67
decode_uarch(uint32_t cpu_family,uint32_t core_index,uint32_t core_count)68 static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index, uint32_t core_count) {
69 switch (cpu_family) {
70 case CPUFAMILY_ARM_CYCLONE:
71 return cpuinfo_uarch_cyclone;
72 case CPUFAMILY_ARM_TYPHOON:
73 return cpuinfo_uarch_typhoon;
74 case CPUFAMILY_ARM_TWISTER:
75 return cpuinfo_uarch_twister;
76 case CPUFAMILY_ARM_HURRICANE:
77 return cpuinfo_uarch_hurricane;
78 case CPUFAMILY_ARM_MONSOON_MISTRAL:
79 /* 2x Monsoon + 4x Mistral cores */
80 return core_index < 2 ? cpuinfo_uarch_monsoon : cpuinfo_uarch_mistral;
81 case CPUFAMILY_ARM_VORTEX_TEMPEST:
82 /* Hexa-core: 2x Vortex + 4x Tempest; Octa-core: 4x Cortex + 4x Tempest */
83 return core_index + 4 < core_count ? cpuinfo_uarch_vortex : cpuinfo_uarch_tempest;
84 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
85 /* Hexa-core: 2x Lightning + 4x Thunder; Octa-core (presumed): 4x Lightning + 4x Thunder */
86 return core_index + 4 < core_count ? cpuinfo_uarch_lightning : cpuinfo_uarch_thunder;
87 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
88 /* Hexa-core: 2x Firestorm + 4x Icestorm; Octa-core: 4x Firestorm + 4x Icestorm */
89 return core_index + 4 < core_count ? cpuinfo_uarch_firestorm : cpuinfo_uarch_icestorm;
90 case CPUFAMILY_ARM_AVALANCHE_BLIZZARD:
91 /* Hexa-core: 2x Avalanche + 4x Blizzard */
92 return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard;
93 default:
94 /* Use hw.cpusubtype for detection */
95 break;
96 }
97
98 return cpuinfo_uarch_unknown;
99 }
100
decode_package_name(char * package_name)101 static void decode_package_name(char* package_name) {
102 size_t size;
103 if (sysctlbyname("hw.machine", NULL, &size, NULL, 0) != 0) {
104 cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
105 return;
106 }
107
108 char *machine_name = alloca(size);
109 if (sysctlbyname("hw.machine", machine_name, &size, NULL, 0) != 0) {
110 cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
111 return;
112 }
113 cpuinfo_log_debug("hw.machine: %s", machine_name);
114
115 char name[10];
116 uint32_t major = 0, minor = 0;
117 if (sscanf(machine_name, "%9[^,0123456789]%"SCNu32",%"SCNu32, name, &major, &minor) != 3) {
118 cpuinfo_log_warning("parsing \"hw.machine\" failed: %s", strerror(errno));
119 return;
120 }
121
122 uint32_t chip_model = 0;
123 char suffix = '\0';
124 if (strcmp(name, "iPhone") == 0) {
125 /*
126 * iPhone 4 and up are supported:
127 * - iPhone 4 [A4]: iPhone3,1, iPhone3,2, iPhone3,3
128 * - iPhone 4S [A5]: iPhone4,1
129 * - iPhone 5 [A6]: iPhone5,1, iPhone5,2
130 * - iPhone 5c [A6]: iPhone5,3, iPhone5,4
131 * - iPhone 5s [A7]: iPhone6,1, iPhone6,2
132 * - iPhone 6 [A8]: iPhone7,2
133 * - iPhone 6 Plus [A8]: iPhone7,1
134 * - iPhone 6s [A9]: iPhone8,1
135 * - iPhone 6s Plus [A9]: iPhone8,2
136 * - iPhone SE [A9]: iPhone8,4
137 * - iPhone 7 [A10]: iPhone9,1, iPhone9,3
138 * - iPhone 7 Plus [A10]: iPhone9,2, iPhone9,4
139 * - iPhone 8 [A11]: iPhone10,1, iPhone10,4
140 * - iPhone 8 Plus [A11]: iPhone10,2, iPhone10,5
141 * - iPhone X [A11]: iPhone10,3, iPhone10,6
142 * - iPhone XS [A12]: iPhone11,2,
143 * - iPhone XS Max [A12]: iPhone11,4, iPhone11,6
144 * - iPhone XR [A12]: iPhone11,8
145 */
146 chip_model = major + 1;
147 } else if (strcmp(name, "iPad") == 0) {
148 switch (major) {
149 /* iPad 2 and up are supported */
150 case 2:
151 /*
152 * iPad 2 [A5]: iPad2,1, iPad2,2, iPad2,3, iPad2,4
153 * iPad mini [A5]: iPad2,5, iPad2,6, iPad2,7
154 */
155 chip_model = major + 3;
156 break;
157 case 3:
158 /*
159 * iPad 3rd Gen [A5X]: iPad3,1, iPad3,2, iPad3,3
160 * iPad 4th Gen [A6X]: iPad3,4, iPad3,5, iPad3,6
161 */
162 chip_model = (minor <= 3) ? 5 : 6;
163 suffix = 'X';
164 break;
165 case 4:
166 /*
167 * iPad Air [A7]: iPad4,1, iPad4,2, iPad4,3
168 * iPad mini Retina [A7]: iPad4,4, iPad4,5, iPad4,6
169 * iPad mini 3 [A7]: iPad4,7, iPad4,8, iPad4,9
170 */
171 chip_model = major + 3;
172 break;
173 case 5:
174 /*
175 * iPad mini 4 [A8]: iPad5,1, iPad5,2
176 * iPad Air 2 [A8X]: iPad5,3, iPad5,4
177 */
178 chip_model = major + 3;
179 suffix = (minor <= 2) ? '\0' : 'X';
180 break;
181 case 6:
182 /*
183 * iPad Pro 9.7" [A9X]: iPad6,3, iPad6,4
184 * iPad Pro [A9X]: iPad6,7, iPad6,8
185 * iPad 5th Gen [A9]: iPad6,11, iPad6,12
186 */
187 chip_model = major + 3;
188 suffix = minor <= 8 ? 'X' : '\0';
189 break;
190 case 7:
191 /*
192 * iPad Pro 12.9" [A10X]: iPad7,1, iPad7,2
193 * iPad Pro 10.5" [A10X]: iPad7,3, iPad7,4
194 * iPad 6th Gen [A10]: iPad7,5, iPad7,6
195 */
196 chip_model = major + 3;
197 suffix = minor <= 4 ? 'X' : '\0';
198 break;
199 default:
200 cpuinfo_log_info("unknown iPad: %s", machine_name);
201 break;
202 }
203 } else if (strcmp(name, "iPod") == 0) {
204 switch (major) {
205 case 5:
206 chip_model = 5;
207 break;
208 /* iPod touch (5th Gen) [A5]: iPod5,1 */
209 case 7:
210 /* iPod touch (6th Gen, 2015) [A8]: iPod7,1 */
211 chip_model = 8;
212 break;
213 default:
214 cpuinfo_log_info("unknown iPod: %s", machine_name);
215 break;
216 }
217 } else {
218 cpuinfo_log_info("unknown device: %s", machine_name);
219 }
220 if (chip_model != 0) {
221 snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%"PRIu32"%c", chip_model, suffix);
222 }
223 }
224
cpuinfo_arm_mach_init(void)225 void cpuinfo_arm_mach_init(void) {
226 struct cpuinfo_processor* processors = NULL;
227 struct cpuinfo_core* cores = NULL;
228 struct cpuinfo_cluster* clusters = NULL;
229 struct cpuinfo_package* packages = NULL;
230 struct cpuinfo_uarch_info* uarchs = NULL;
231 struct cpuinfo_cache* l1i = NULL;
232 struct cpuinfo_cache* l1d = NULL;
233 struct cpuinfo_cache* l2 = NULL;
234 struct cpuinfo_cache* l3 = NULL;
235
236 struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology();
237 processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor));
238 if (processors == NULL) {
239 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors",
240 mach_topology.threads * sizeof(struct cpuinfo_processor), mach_topology.threads);
241 goto cleanup;
242 }
243 cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core));
244 if (cores == NULL) {
245 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores",
246 mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores);
247 goto cleanup;
248 }
249 packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package));
250 if (packages == NULL) {
251 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" packages",
252 mach_topology.packages * sizeof(struct cpuinfo_package), mach_topology.packages);
253 goto cleanup;
254 }
255
256 const uint32_t threads_per_core = mach_topology.threads / mach_topology.cores;
257 const uint32_t threads_per_package = mach_topology.threads / mach_topology.packages;
258 const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages;
259
260 for (uint32_t i = 0; i < mach_topology.packages; i++) {
261 packages[i] = (struct cpuinfo_package) {
262 .processor_start = i * threads_per_package,
263 .processor_count = threads_per_package,
264 .core_start = i * cores_per_package,
265 .core_count = cores_per_package,
266 };
267 decode_package_name(packages[i].name);
268 }
269
270
271 const uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
272
273 /*
274 * iOS 15 and macOS 12 added sysctls for ARM features, use them where possible.
275 * Otherwise, fallback to hardcoded set of CPUs with known support.
276 */
277 const uint32_t has_feat_lse = get_sys_info_by_name("hw.optional.arm.FEAT_LSE");
278 if (has_feat_lse != 0) {
279 cpuinfo_isa.atomics = true;
280 } else {
281 // Mandatory in ARMv8.1-A, list only cores released before iOS 15 / macOS 12
282 switch (cpu_family) {
283 case CPUFAMILY_ARM_MONSOON_MISTRAL:
284 case CPUFAMILY_ARM_VORTEX_TEMPEST:
285 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
286 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
287 cpuinfo_isa.atomics = true;
288 }
289 }
290
291 const uint32_t has_feat_rdm = get_sys_info_by_name("hw.optional.arm.FEAT_RDM");
292 if (has_feat_rdm != 0) {
293 cpuinfo_isa.rdm = true;
294 } else {
295 // Optional in ARMv8.2-A (implemented in Apple cores),
296 // list only cores released before iOS 15 / macOS 12
297 switch (cpu_family) {
298 case CPUFAMILY_ARM_MONSOON_MISTRAL:
299 case CPUFAMILY_ARM_VORTEX_TEMPEST:
300 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
301 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
302 cpuinfo_isa.rdm = true;
303 }
304 }
305
306 const uint32_t has_feat_fp16 = get_sys_info_by_name("hw.optional.arm.FEAT_FP16");
307 if (has_feat_fp16 != 0) {
308 cpuinfo_isa.fp16arith = true;
309 } else {
310 // Optional in ARMv8.2-A (implemented in Apple cores),
311 // list only cores released before iOS 15 / macOS 12
312 switch (cpu_family) {
313 case CPUFAMILY_ARM_MONSOON_MISTRAL:
314 case CPUFAMILY_ARM_VORTEX_TEMPEST:
315 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
316 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
317 cpuinfo_isa.fp16arith = true;
318 }
319 }
320
321 const uint32_t has_feat_fhm = get_sys_info_by_name("hw.optional.arm.FEAT_FHM");
322 if (has_feat_fhm != 0) {
323 cpuinfo_isa.fhm = true;
324 } else {
325 // Prior to iOS 15, use 'hw.optional.armv8_2_fhm'
326 const uint32_t has_feat_fhm_legacy = get_sys_info_by_name("hw.optional.armv8_2_fhm");
327 if (has_feat_fhm_legacy != 0) {
328 cpuinfo_isa.fhm = true;
329 } else {
330 // Mandatory in ARMv8.4-A when FP16 arithmetics is implemented,
331 // list only cores released before iOS 15 / macOS 12
332 switch (cpu_family) {
333 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
334 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
335 cpuinfo_isa.fhm = true;
336 }
337 }
338 }
339
340 const uint32_t has_feat_bf16 = get_sys_info_by_name("hw.optional.arm.FEAT_BF16");
341 if (has_feat_bf16 != 0) {
342 cpuinfo_isa.bf16 = true;
343 }
344
345 const uint32_t has_feat_fcma = get_sys_info_by_name("hw.optional.arm.FEAT_FCMA");
346 if (has_feat_fcma != 0) {
347 cpuinfo_isa.fcma = true;
348 } else {
349 // Mandatory in ARMv8.3-A, list only cores released before iOS 15 / macOS 12
350 switch (cpu_family) {
351 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
352 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
353 cpuinfo_isa.fcma = true;
354 }
355 }
356
357 const uint32_t has_feat_jscvt = get_sys_info_by_name("hw.optional.arm.FEAT_JSCVT");
358 if (has_feat_jscvt != 0) {
359 cpuinfo_isa.jscvt = true;
360 } else {
361 // Mandatory in ARMv8.3-A, list only cores released before iOS 15 / macOS 12
362 switch (cpu_family) {
363 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
364 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
365 cpuinfo_isa.jscvt = true;
366 }
367 }
368
369 const uint32_t has_feat_dotprod = get_sys_info_by_name("hw.optional.arm.FEAT_DotProd");
370 if (has_feat_dotprod != 0) {
371 cpuinfo_isa.dot = true;
372 } else {
373 // Mandatory in ARMv8.4-A, list only cores released before iOS 15 / macOS 12
374 switch (cpu_family) {
375 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
376 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
377 cpuinfo_isa.dot = true;
378 }
379 }
380
381 const uint32_t has_feat_i8mm = get_sys_info_by_name("hw.optional.arm.FEAT_I8MM");
382 if (has_feat_i8mm != 0) {
383 cpuinfo_isa.i8mm = true;
384 }
385
386 uint32_t num_clusters = 1;
387 for (uint32_t i = 0; i < mach_topology.cores; i++) {
388 cores[i] = (struct cpuinfo_core) {
389 .processor_start = i * threads_per_core,
390 .processor_count = threads_per_core,
391 .core_id = i % cores_per_package,
392 .package = packages + i / cores_per_package,
393 .vendor = cpuinfo_vendor_apple,
394 .uarch = decode_uarch(cpu_family, i, mach_topology.cores),
395 };
396 if (i != 0 && cores[i].uarch != cores[i - 1].uarch) {
397 num_clusters++;
398 }
399 }
400 for (uint32_t i = 0; i < mach_topology.threads; i++) {
401 const uint32_t smt_id = i % threads_per_core;
402 const uint32_t core_id = i / threads_per_core;
403 const uint32_t package_id = i / threads_per_package;
404
405 processors[i].smt_id = smt_id;
406 processors[i].core = &cores[core_id];
407 processors[i].package = &packages[package_id];
408 }
409
410 clusters = calloc(num_clusters, sizeof(struct cpuinfo_cluster));
411 if (clusters == NULL) {
412 cpuinfo_log_error(
413 "failed to allocate %zu bytes for descriptions of %"PRIu32" clusters",
414 num_clusters * sizeof(struct cpuinfo_cluster), num_clusters);
415 goto cleanup;
416 }
417 uarchs = calloc(num_clusters, sizeof(struct cpuinfo_uarch_info));
418 if (uarchs == NULL) {
419 cpuinfo_log_error(
420 "failed to allocate %zu bytes for descriptions of %"PRIu32" uarchs",
421 num_clusters * sizeof(enum cpuinfo_uarch), num_clusters);
422 goto cleanup;
423 }
424 uint32_t cluster_idx = UINT32_MAX;
425 for (uint32_t i = 0; i < mach_topology.cores; i++) {
426 if (i == 0 || cores[i].uarch != cores[i - 1].uarch) {
427 cluster_idx++;
428 uarchs[cluster_idx] = (struct cpuinfo_uarch_info) {
429 .uarch = cores[i].uarch,
430 .processor_count = 1,
431 .core_count = 1,
432 };
433 clusters[cluster_idx] = (struct cpuinfo_cluster) {
434 .processor_start = i * threads_per_core,
435 .processor_count = 1,
436 .core_start = i,
437 .core_count = 1,
438 .cluster_id = cluster_idx,
439 .package = cores[i].package,
440 .vendor = cores[i].vendor,
441 .uarch = cores[i].uarch,
442 };
443 } else {
444 uarchs[cluster_idx].processor_count++;
445 uarchs[cluster_idx].core_count++;
446 clusters[cluster_idx].processor_count++;
447 clusters[cluster_idx].core_count++;
448 }
449 cores[i].cluster = &clusters[cluster_idx];
450 }
451
452 for (uint32_t i = 0; i < mach_topology.threads; i++) {
453 const uint32_t core_id = i / threads_per_core;
454 processors[i].cluster = cores[core_id].cluster;
455 }
456
457 for (uint32_t i = 0; i < mach_topology.packages; i++) {
458 packages[i].cluster_start = 0;
459 packages[i].cluster_count = num_clusters;
460 }
461
462 const uint32_t cacheline_size = get_sys_info(HW_CACHELINE, "HW_CACHELINE");
463 const uint32_t l1d_cache_size = get_sys_info(HW_L1DCACHESIZE, "HW_L1DCACHESIZE");
464 const uint32_t l1i_cache_size = get_sys_info(HW_L1ICACHESIZE, "HW_L1ICACHESIZE");
465 const uint32_t l2_cache_size = get_sys_info(HW_L2CACHESIZE, "HW_L2CACHESIZE");
466 const uint32_t l3_cache_size = get_sys_info(HW_L3CACHESIZE, "HW_L3CACHESIZE");
467 const uint32_t l1_cache_associativity = 4;
468 const uint32_t l2_cache_associativity = 8;
469 const uint32_t l3_cache_associativity = 16;
470 const uint32_t cache_partitions = 1;
471 const uint32_t cache_flags = 0;
472
473 uint32_t threads_per_l1 = 0, l1_count = 0;
474 if (l1i_cache_size != 0 || l1d_cache_size != 0) {
475 /* Assume L1 caches are private to each core */
476 threads_per_l1 = 1;
477 l1_count = mach_topology.threads / threads_per_l1;
478 cpuinfo_log_debug("detected %"PRIu32" L1 caches", l1_count);
479 }
480
481 uint32_t threads_per_l2 = 0, l2_count = 0;
482 if (l2_cache_size != 0) {
483 /* Assume L2 cache is shared between all cores */
484 threads_per_l2 = mach_topology.cores;
485 l2_count = 1;
486 cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count);
487 }
488
489 uint32_t threads_per_l3 = 0, l3_count = 0;
490 if (l3_cache_size != 0) {
491 /* Assume L3 cache is shared between all cores */
492 threads_per_l3 = mach_topology.cores;
493 l3_count = 1;
494 cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count);
495 }
496
497 if (l1i_cache_size != 0) {
498 l1i = calloc(l1_count, sizeof(struct cpuinfo_cache));
499 if (l1i == NULL) {
500 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches",
501 l1_count * sizeof(struct cpuinfo_cache), l1_count);
502 goto cleanup;
503 }
504 for (uint32_t c = 0; c < l1_count; c++) {
505 l1i[c] = (struct cpuinfo_cache) {
506 .size = l1i_cache_size,
507 .associativity = l1_cache_associativity,
508 .sets = l1i_cache_size / (l1_cache_associativity * cacheline_size),
509 .partitions = cache_partitions,
510 .line_size = cacheline_size,
511 .flags = cache_flags,
512 .processor_start = c * threads_per_l1,
513 .processor_count = threads_per_l1,
514 };
515 }
516 for (uint32_t t = 0; t < mach_topology.threads; t++) {
517 processors[t].cache.l1i = &l1i[t / threads_per_l1];
518 }
519 }
520
521 if (l1d_cache_size != 0) {
522 l1d = calloc(l1_count, sizeof(struct cpuinfo_cache));
523 if (l1d == NULL) {
524 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches",
525 l1_count * sizeof(struct cpuinfo_cache), l1_count);
526 goto cleanup;
527 }
528 for (uint32_t c = 0; c < l1_count; c++) {
529 l1d[c] = (struct cpuinfo_cache) {
530 .size = l1d_cache_size,
531 .associativity = l1_cache_associativity,
532 .sets = l1d_cache_size / (l1_cache_associativity * cacheline_size),
533 .partitions = cache_partitions,
534 .line_size = cacheline_size,
535 .flags = cache_flags,
536 .processor_start = c * threads_per_l1,
537 .processor_count = threads_per_l1,
538 };
539 }
540 for (uint32_t t = 0; t < mach_topology.threads; t++) {
541 processors[t].cache.l1d = &l1d[t / threads_per_l1];
542 }
543 }
544
545 if (l2_count != 0) {
546 l2 = calloc(l2_count, sizeof(struct cpuinfo_cache));
547 if (l2 == NULL) {
548 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches",
549 l2_count * sizeof(struct cpuinfo_cache), l2_count);
550 goto cleanup;
551 }
552 for (uint32_t c = 0; c < l2_count; c++) {
553 l2[c] = (struct cpuinfo_cache) {
554 .size = l2_cache_size,
555 .associativity = l2_cache_associativity,
556 .sets = l2_cache_size / (l2_cache_associativity * cacheline_size),
557 .partitions = cache_partitions,
558 .line_size = cacheline_size,
559 .flags = cache_flags,
560 .processor_start = c * threads_per_l2,
561 .processor_count = threads_per_l2,
562 };
563 }
564 for (uint32_t t = 0; t < mach_topology.threads; t++) {
565 processors[t].cache.l2 = &l2[0];
566 }
567 }
568
569 if (l3_count != 0) {
570 l3 = calloc(l3_count, sizeof(struct cpuinfo_cache));
571 if (l3 == NULL) {
572 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches",
573 l3_count * sizeof(struct cpuinfo_cache), l3_count);
574 goto cleanup;
575 }
576 for (uint32_t c = 0; c < l3_count; c++) {
577 l3[c] = (struct cpuinfo_cache) {
578 .size = l3_cache_size,
579 .associativity = l3_cache_associativity,
580 .sets = l3_cache_size / (l3_cache_associativity * cacheline_size),
581 .partitions = cache_partitions,
582 .line_size = cacheline_size,
583 .flags = cache_flags,
584 .processor_start = c * threads_per_l3,
585 .processor_count = threads_per_l3,
586 };
587 }
588 for (uint32_t t = 0; t < mach_topology.threads; t++) {
589 processors[t].cache.l3 = &l3[0];
590 }
591 }
592
593 /* Commit changes */
594 cpuinfo_processors = processors;
595 cpuinfo_cores = cores;
596 cpuinfo_clusters = clusters;
597 cpuinfo_packages = packages;
598 cpuinfo_uarchs = uarchs;
599 cpuinfo_cache[cpuinfo_cache_level_1i] = l1i;
600 cpuinfo_cache[cpuinfo_cache_level_1d] = l1d;
601 cpuinfo_cache[cpuinfo_cache_level_2] = l2;
602 cpuinfo_cache[cpuinfo_cache_level_3] = l3;
603
604 cpuinfo_processors_count = mach_topology.threads;
605 cpuinfo_cores_count = mach_topology.cores;
606 cpuinfo_clusters_count = num_clusters;
607 cpuinfo_packages_count = mach_topology.packages;
608 cpuinfo_uarchs_count = num_clusters;
609 cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count;
610 cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count;
611 cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count;
612 cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count;
613 cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]);
614
615 __sync_synchronize();
616
617 cpuinfo_is_initialized = true;
618
619 processors = NULL;
620 cores = NULL;
621 clusters = NULL;
622 packages = NULL;
623 uarchs = NULL;
624 l1i = l1d = l2 = l3 = NULL;
625
626 cleanup:
627 free(processors);
628 free(cores);
629 free(clusters);
630 free(packages);
631 free(uarchs);
632 free(l1i);
633 free(l1d);
634 free(l2);
635 free(l3);
636 }
637