xref: /aosp_15_r20/external/cpuinfo/src/arm/cache.c (revision 2b54f0db79fd8303838913b20ff3780cddaa909f) 
1 #include <stdint.h>
2 
3 #include <cpuinfo.h>
4 #include <cpuinfo/internal-api.h>
5 #include <cpuinfo/log.h>
6 #include <arm/api.h>
7 #include <arm/midr.h>
8 
9 
cpuinfo_arm_decode_cache(enum cpuinfo_uarch uarch,uint32_t cluster_cores,uint32_t midr,const struct cpuinfo_arm_chipset chipset[restrict static1],uint32_t cluster_id,uint32_t arch_version,struct cpuinfo_cache l1i[restrict static1],struct cpuinfo_cache l1d[restrict static1],struct cpuinfo_cache l2[restrict static1],struct cpuinfo_cache l3[restrict static1])10 void cpuinfo_arm_decode_cache(
11 	enum cpuinfo_uarch uarch,
12 	uint32_t cluster_cores,
13 	uint32_t midr,
14 	const struct cpuinfo_arm_chipset chipset[restrict static 1],
15 	uint32_t cluster_id,
16 	uint32_t arch_version,
17 	struct cpuinfo_cache l1i[restrict static 1],
18 	struct cpuinfo_cache l1d[restrict static 1],
19 	struct cpuinfo_cache l2[restrict static 1],
20 	struct cpuinfo_cache l3[restrict static 1])
21 {
22 	switch (uarch) {
23 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__)
24 		case cpuinfo_uarch_xscale:
25 			switch (midr_get_part(midr) >> 8) {
26 				case 2:
27 					/*
28 					 * PXA 210/25X/26X
29 					 *
30 					 * See "Computer Organization and Design, Revised Printing: The Hardware/Software Interface"
31 					 *     by David A. Patterson, John L. Hennessy
32 					 */
33 					*l1i = (struct cpuinfo_cache) {
34 						.size = 16 * 1024,
35 						.associativity = 32,
36 						.line_size = 32
37 					};
38 					*l1d = (struct cpuinfo_cache) {
39 						.size = 16 * 1024,
40 						.associativity = 4,
41 						.line_size = 64
42 					};
43 					break;
44 				case 4:
45 					/* PXA 27X */
46 					*l1i = (struct cpuinfo_cache) {
47 						.size = 32 * 1024,
48 						.associativity = 32,
49 						.line_size = 32
50 					};
51 					*l1d = (struct cpuinfo_cache) {
52 						.size = 32 * 1024,
53 						.associativity = 32,
54 						.line_size = 32
55 					};
56 					break;
57 				case 6:
58 					/*
59 					 * PXA 3XX
60 					 *
61 					 * See http://download.intel.com/design/intelxscale/31628302.pdf
62 					 */
63 					*l1i = (struct cpuinfo_cache) {
64 						.size = 32 * 1024,
65 						.associativity = 4,
66 						.line_size = 32
67 					};
68 					*l1d = (struct cpuinfo_cache) {
69 						.size = 32 * 1024,
70 						.associativity = 4,
71 						.line_size = 32
72 					};
73 					*l2 = (struct cpuinfo_cache) {
74 						.size = 256 * 1024,
75 						.associativity = 8,
76 						.line_size = 32
77 					};
78 					break;
79 			}
80 			break;
81 		case cpuinfo_uarch_arm11:
82 			*l1i = (struct cpuinfo_cache) {
83 				.size = 16 * 1024,
84 				.associativity = 4,
85 				.line_size = 32
86 			};
87 			*l1d = (struct cpuinfo_cache) {
88 				.size = 16 * 1024,
89 				.associativity = 4,
90 				.line_size = 32
91 			};
92 			break;
93 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) */
94 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
95 		case cpuinfo_uarch_cortex_a5:
96 			/*
97 			 * Cortex-A5 Technical Reference Manual:
98 			 * 7.1.1. Memory system
99 			 *   The Cortex-A5 processor has separate instruction and data caches.
100 			 *   The caches have the following features:
101 			 *    - Data cache is 4-way set-associative.
102 			 *    - Instruction cache is 2-way set-associative.
103 			 *    - The cache line length is eight words.
104 			 *    - You can configure the instruction and data caches independently during implementation
105 			 *      to sizes of 4KB, 8KB, 16KB, 32KB, or 64KB.
106 			 * 1.1.3. System design components
107 			 *    PrimeCell Level 2 Cache Controller (PL310)
108 			 *      The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a
109 			 *      recognized method of improving the performance of ARM-based systems when significant memory traffic
110 			 *      is generated by the processor. The PrimeCell Level 2 Cache Controller reduces the number of external
111 			 *      memory accesses and has been optimized for use with the Cortex-A5 processor.
112 			 * 8.1.7. Exclusive L2 cache
113 			 *    The Cortex-A5 processor can be connected to an L2 cache that supports an exclusive cache mode.
114 			 *    This mode must be activated both in the Cortex-A5 processor and in the L2 cache controller.
115 			 *
116 			 *  +--------------------+-----------+-----------+----------+-----------+
117 			 *  | Processor model    | L1D cache | L1I cache | L2 cache | Reference |
118 			 *  +--------------------+-----------+-----------+----------+-----------+
119 			 *  | Qualcomm MSM7225A  |           |           |          |           |
120 			 *  | Qualcomm MSM7625A  |           |           |          |           |
121 			 *  | Qualcomm MSM7227A  |           |           |          |           |
122 			 *  | Qualcomm MSM7627A  |    32K    |    32K    |   256K   | Wiki [1]  |
123 			 *  | Qualcomm MSM7225AB |           |           |          |           |
124 			 *  | Qualcomm MSM7225AB |           |           |          |           |
125 			 *  | Qualcomm QSD8250   |           |           |          |           |
126 			 *  | Qualcomm QSD8650   |           |           |          |           |
127 			 *  +--------------------+-----------+-----------+----------+-----------+
128 			 *  | Spreadtrum SC6821  |    32K    |    32K    |    ?     |           |
129 			 *  | Spreadtrum SC6825  |    32K    |    32K    |   256K   | Wiki [2]  |
130 			 *  | Spreadtrum SC8810  |     ?     |     ?     |    ?     |           |
131 			 *  | Spreadtrum SC8825  |    32K    |    32K    |    ?     |           |
132 			 *  +--------------------+-----------+-----------+----------+-----------+
133 			 *
134 			 * [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1
135 			 * [2] https://en.wikipedia.org/wiki/Spreadtrum
136 			 */
137 			*l1i = (struct cpuinfo_cache) {
138 				.size = 32 * 1024,
139 				.associativity = 2,
140 				.line_size = 32
141 			};
142 			*l1d = (struct cpuinfo_cache) {
143 				.size = 32 * 1024,
144 				.associativity = 4,
145 				.line_size = 32
146 			};
147 			*l2 = (struct cpuinfo_cache) {
148 				.size = 256 * 1024,
149 				/*
150 				 * Follow NXP specification: "Eight-way set-associative 512 kB L2 cache with 32B line size"
151 				 * Reference: http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf
152 				 */
153 				.associativity = 8,
154 				.line_size = 32
155 			};
156 			break;
157 		case cpuinfo_uarch_cortex_a7:
158 			/*
159 			 * Cortex-A7 MPCore Technical Reference Manual:
160 			 * 6.1. About the L1 memory system
161 			 *   The L1 memory system consists of separate instruction and data caches. You can configure the
162 			 *   instruction and data caches independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
163 			 *
164 			 *   The L1 instruction memory system has the following features:
165 			 *    - Instruction side cache line length of 32-bytes.
166 			 *    - 2-way set-associative instruction cache.
167 			 *
168 			 *   The L1 data memory system has the following features:
169 			 *    - Data side cache line length of 64-bytes.
170 			 *    - 4-way set-associative data cache.
171 			 *
172 			 * 7.1. About the L2 Memory system
173 			 *   The L2 memory system consists of an:
174 			 *    - Optional tightly-coupled L2 cache that includes:
175 			 *      - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB.
176 			 *      - Fixed line length of 64 bytes
177 			 *      - 8-way set-associative cache structure
178 			 *
179 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
180 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | Reference |
181 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
182 			 *  | Allwinner A20      |   2   |    32K    |    32K    |   256K    |    [1]    |
183 			 *  | Allwinner A23      |   2   |    32K    |    32K    |   256K    |    [2]    |
184 			 *  | Allwinner A31      |   4   |    32K    |    32K    |    1M     |    [3]    |
185 			 *  | Allwinner A31s     |   4   |    32K    |    32K    |    1M     |    [4]    |
186 			 *  | Allwinner A33      |   4   |    32K    |    32K    |   512K    |    [5]    |
187 			 *  | Allwinner A80 Octa | 4(+4) |    32K    |    32K    | 512K(+2M) |    [6]    |
188 			 *  | Allwinner A81T     |   8   |    32K    |    32K    |    1M     |    [7]    |
189 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
190 			 *  | Broadcom BCM2836   |   4   |    32K    |    32K    |    512K   |    [8]    |
191 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
192 			 *  | Kirin 920          | 4(+4) |     ?     |     ?     |    512K   |    [9]    |
193 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
194 			 *
195 			 * [1] https://linux-sunxi.org/A20
196 			 * [2] https://linux-sunxi.org/A23
197 			 * [3] http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf
198 			 * [4] https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf
199 			 * [5] http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf
200 			 * [6] https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf
201 			 * [7] http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
202 			 * [8] https://www.raspberrypi.org/forums/viewtopic.php?t=98428
203 			 * [9] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
204 			 */
205 			*l1i = (struct cpuinfo_cache) {
206 				.size = 32 * 1024,
207 				.associativity = 2,
208 				.line_size = 32
209 			};
210 			*l1d = (struct cpuinfo_cache) {
211 				.size = 32 * 1024,
212 				.associativity = 4,
213 				.line_size = 64
214 			};
215 			*l2 = (struct cpuinfo_cache) {
216 				.size = 128 * 1024 * cluster_cores,
217 				.associativity = 8,
218 				.line_size = 64
219 			};
220 			break;
221 		case cpuinfo_uarch_cortex_a8:
222 			/*
223 			 * Cortex-A8 Technical Reference Manual:
224 			 * 7.1. About the L1 memory system
225 			 *    The L1 memory system consists of separate instruction and data caches in a Harvard arrangement.
226 			 *    The L1 memory system provides the core with:
227 			 *     - fixed line length of 64 bytes
228 			 *     - support for 16KB or 32KB caches
229 			 *     - 4-way set associative cache structure
230 			 * 8.1. About the L2 memory system
231 			 *    The L2 memory system is tightly coupled to the L1 data cache and L1 instruction cache.
232 			 *    The key features of the L2 memory system include:
233 			 *     - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB
234 			 *     - fixed line length of 64 bytes
235 			 *     - 8-way set associative cache structure
236 			 *
237 			 *  +----------------------+-----------+-----------+-----------+-----------+
238 			 *  | Processor model      | L1D cache | L1I cache | L2 cache  | Reference |
239 			 *  +----------------------+-----------+-----------+-----------+-----------+
240 			 *  | Exynos 3 Single 3110 |    32K    |    32K    |   512K    |    [1]    |
241 			 *  +----------------------+-----------+-----------+-----------+-----------+
242 			 *  | TI DM 3730           |    32K    |    32K    |   256K    |    [2]    |
243 			 *  +----------------------+-----------+-----------+-----------+-----------+
244 			 *
245 			 * [1] https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf
246 			 * [2] https://www.ti.com/lit/ds/symlink/dm3725.pdf
247 			 */
248 			*l1i = (struct cpuinfo_cache) {
249 				.size = 32 * 1024,
250 				.associativity = 4,
251 				.line_size = 64
252 			};
253 			*l1d = (struct cpuinfo_cache) {
254 				.size = 32 * 1024,
255 				.associativity = 4,
256 				.line_size = 64
257 			};
258 			*l2 = (struct cpuinfo_cache) {
259 				.associativity = 8,
260 				.line_size = 64
261 			};
262 			switch (chipset->vendor) {
263 				case cpuinfo_arm_chipset_vendor_samsung:
264 					l2->size = 512 * 1024;
265 					break;
266 				default:
267 					l2->size = 256 * 1024;
268 					break;
269 			}
270 
271 			break;
272 		case cpuinfo_uarch_cortex_a9:
273 			/*
274 			 * ARM Cortex‑A9 Technical Reference Manual:
275 			 * 7.1.1 Memory system
276 			 *    The Cortex‑A9 processor has separate instruction and data caches.
277 			 *    The caches have the following features:
278 			 *     - Both caches are 4-way set-associative.
279 			 *     - The cache line length is eight words.
280 			 *     - You can configure the instruction and data caches independently during implementation
281 			 *       to sizes of 16KB, 32KB, or 64KB.
282 			 * 8.1.5 Exclusive L2 cache
283 			 *    The Cortex‑A9 processor can be connected to an L2 cache that supports an exclusive cache mode.
284 			 *    This mode must be activated both in the Cortex‑A9 processor and in the L2 cache controller.
285 			 *
286 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
287 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | Reference |
288 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
289 			 *  | Exynos 4 Dual 4210 |   2   |    32K    |    32K    |    1M     |    [1]    |
290 			 *  | Exynos 4 Dual 4212 |   2   |    32K    |    32K    |    1M     |    [2]    |
291 			 *  | Exynos 4 Quad 4412 |   4   |    32K    |    32K    |    1M     |    [3]    |
292 			 *  | Exynos 4 Quad 4415 |   4   |    32K    |    32K    |    1M     |           |
293 			 *  | TI OMAP 4430       |   2   |    32K    |    32K    |    1M     |    [4]    |
294 			 *  | TI OMAP 4460       |   2   |    32K    |    32K    |    1M     |    [5]    |
295 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
296 			 *
297 			 * [1] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf
298 			 * [2] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf
299 			 * [3] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf
300 			 * [4] https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf
301 			 * [5] http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9
302 			 */
303 
304 			/* Use Exynos 4 specs */
305 			*l1i = (struct cpuinfo_cache) {
306 				.size = 32 * 1024,
307 				.associativity = 4,
308 				.line_size = 32
309 			};
310 			*l1d = (struct cpuinfo_cache) {
311 				.size = 32 * 1024,
312 				.associativity = 4,
313 				.line_size = 32
314 			};
315 			*l2 = (struct cpuinfo_cache) {
316 				.size = 1024 * 1024,
317 				/* OMAP4460 in Pandaboard ES has 16-way set-associative L2 cache */
318 				.associativity = 16,
319 				.line_size = 32
320 			};
321 			break;
322 		case cpuinfo_uarch_cortex_a15:
323 			/*
324 			 * 6.1. About the L1 memory system
325 			 *    The L1 memory system consists of separate instruction and data caches.
326 			 *    The L1 instruction memory system has the following features:
327 			 *     - 32KB 2-way set-associative instruction cache.
328 			 *     - Fixed line length of 64 bytes.
329 			 *    The L1 data memory system has the following features:
330 			 *     - 32KB 2-way set-associative data cache.
331 			 *     - Fixed line length of 64 bytes.
332 			 * 7.1. About the L2 memory system
333 			 *    The features of the L2 memory system include:
334 			 *     - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
335 			 *     - Fixed line length of 64 bytes.
336 			 *     - 16-way set-associative cache structure.
337 			 *
338 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
339 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | Reference |
340 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
341 			 *  | Exynos 5 Dual 5250 |   2   |    32K    |    32K    |    1M     |    [1]    |
342 			 *  | Exynos 5 Hexa 5260 | 2(+4) |    32K    |    32K    | 1M(+512K) |    [2]    |
343 			 *  | Exynos 5 Octa 5410 | 4(+4) |    32K    |    32K    | 2M(+512K) |    [3]    |
344 			 *  | Exynos 5 Octa 5420 | 4(+4) |    32K    |    32K    | 2M(+512K) |    [3]    |
345 			 *  | Exynos 5 Octa 5422 | 4(+4) |    32K    |    32K    | 2M(+512K) |    [3]    |
346 			 *  | Exynos 5 Octa 5430 | 4(+4) |    32K    |    32K    | 2M(+512K) |    [3]    |
347 			 *  | Exynos 5 Octa 5800 | 4(+4) |    32K    |    32K    | 2M(+512K) |    [3]    |
348 			 *  | Kirin 920          | 4(+4) |     ?     |     ?     | 2M(+512K) |    [4]    |
349 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
350 			 *
351 			 * [1] http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf
352 			 * [2] http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf
353 			 * [3] http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13
354 			 * [4] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/
355 			 */
356 			*l1i = (struct cpuinfo_cache) {
357 				.size = 32 * 1024,
358 				.associativity = 2,
359 				.line_size = 64
360 			};
361 			*l1d = (struct cpuinfo_cache) {
362 				.size = 32 * 1024,
363 				.associativity = 2,
364 				.line_size = 64
365 			};
366 			*l2 = (struct cpuinfo_cache) {
367 				.size = cluster_cores * 512 * 1024,
368 				.associativity = 16,
369 				.line_size = 64
370 			};
371 			break;
372 		case cpuinfo_uarch_cortex_a17:
373 			/*
374 			 * ARM Cortex-A17 MPCore Processor Technical Reference Manual:
375 			 * 6.1. About the L1 memory system
376 			 *    The L1 memory system consists of separate instruction and data caches.
377 			 *    The size of the instruction cache is implemented as either 32KB or 64KB.
378 			 *    The size of the data cache is 32KB.
379 			 *
380 			 *    The L1 instruction cache has the following features:
381 			 *     - Instruction side cache line length of 64-bytes.
382 			 *     - 4-way set-associative instruction cache.
383 			 *
384 			 *    The L1 data cache has the following features:
385 			 *     - Data side cache line length of 64-bytes.
386 			 *     - 4-way set-associative data cache.
387 			 *
388 			 * 7.1. About the L2 Memory system
389 			 *    An integrated L2 cache:
390 			 *     - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB.
391 			 *     - A fixed line length of 64 bytes.
392 			 *     - 16-way set-associative cache structure.
393 			 *
394 			 *  +------------------+-------+-----------+-----------+-----------+-----------+
395 			 *  | Processor model  | Cores | L1D cache | L1I cache | L2 cache  | Reference |
396 			 *  +------------------+-------+-----------+-----------+-----------+-----------+
397 			 *  | MediaTek MT6595  | 4(+4) |    32K    |    32K    | 2M(+512K) |    [1]    |
398 			 *  +------------------+-------+-----------+-----------+-----------+-----------+
399 			 *
400 			 * [1] https://blog.osakana.net/archives/5268
401 			 */
402 			*l1i = (struct cpuinfo_cache) {
403 				.size = 32 * 1024,
404 				.associativity = 4,
405 				.line_size = 64
406 			};
407 			*l1d = (struct cpuinfo_cache) {
408 				.size = 32 * 1024,
409 				.associativity = 4,
410 				.line_size = 64
411 			};
412 			*l2 = (struct cpuinfo_cache) {
413 				.size = cluster_cores * 512 * 1024,
414 				.associativity = 16,
415 				.line_size = 64
416 			};
417 			break;
418 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
419 		case cpuinfo_uarch_cortex_a35:
420 			/*
421 			 * ARM Cortex‑A35 Processor Technical Reference Manual:
422 			 * 6.1. About the L1 memory system
423 			 *   The L1 memory system includes several power-saving and performance-enhancing features.
424 			 *   These include separate instruction and data caches, which can be configured
425 			 *   independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
426 			 *
427 			 *   L1 instruction-side memory system
428 			 *     A dedicated instruction cache that:
429 			 *      - is virtually indexed and physically tagged.
430 			 *      - is 2-way set associative.
431 			 *      - is configurable to be 8KB, 16KB, 32KB, or 64KB.
432 			 *      - uses a cache line length of 64 bytes.
433 			 *
434 			 *   L1 data-side memory system
435 			 *     A dedicated data cache that:
436 			 *      - is physically indexed and physically tagged.
437 			 *      - is 4-way set associative.
438 			 *      - is configurable to be 8KB, 16KB, 32KB, or 64KB.
439 			 *      - uses a cache line length of 64 bytes.
440 			 *
441 			 * 7.1. About the L2 memory system
442 			 *   The L2 cache is 8-way set associative.
443 			 *   Further features of the L2 cache are:
444 			 *    - Configurable size of 128KB, 256KB, 512KB, and 1MB.
445 			 *    - Fixed line length of 64 bytes.
446 			 *    - Physically indexed and tagged.
447 			 *
448 			 *  +-----------------+---------+-----------+-----------+-----------+-----------+
449 			 *  | Processor model |  Cores  | L1D cache | L1I cache | L2 cache  | Reference |
450 			 *  +-----------------+---------+-----------+-----------+-----------+-----------+
451 			 *  | MediaTek MT6599 | 4(+4+2) |     ?     |     ?     |     ?     |           |
452 			 *  +-----------------+---------+-----------+-----------+-----------+-----------+
453 			 */
454 			*l1i = (struct cpuinfo_cache) {
455 				.size = 16 * 1024, /* assumption based on low-end Cortex-A53 */
456 				.associativity = 2,
457 				.line_size = 64
458 			};
459 			*l1d = (struct cpuinfo_cache) {
460 				.size = 16 * 1024, /* assumption based on low-end Cortex-A53 */
461 				.associativity = 4,
462 				.line_size = 64
463 			};
464 			*l2 = (struct cpuinfo_cache) {
465 				.size = 256 * 1024, /* assumption based on low-end Cortex-A53 */
466 				.associativity = 8,
467 				.line_size = 64
468 			};
469 			break;
470 		case cpuinfo_uarch_cortex_a53:
471 			/*
472 			 * ARM Cortex-A53 MPCore Processor Technical Reference Manual:
473 			 * 6.1. About the L1 memory system
474 			 *   The L1 memory system consists of separate instruction and data caches. The implementer configures the
475 			 *   instruction and data caches independently during implementation, to sizes of 8KB, 16KB, 32KB, or 64KB.
476 			 *
477 			 *   The L1 Instruction memory system has the following key features:
478 			 *    - Instruction side cache line length of 64 bytes.
479 			 *    - 2-way set associative L1 Instruction cache.
480 			 *
481 			 *   The L1 Data memory system has the following features:
482 			 *    - Data side cache line length of 64 bytes.
483 			 *    - 4-way set associative L1 Data cache.
484 			 *
485 			 * 7.1. About the L2 memory system
486 			 *   The L2 memory system consists of an:
487 			 *    - Optional tightly-coupled L2 cache that includes:
488 			 *      - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB.
489 			 *      - Fixed line length of 64 bytes.
490 			 *      - 16-way set-associative cache structure.
491 			 *
492 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
493 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | Reference |
494 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
495 			 *  | Broadcom BCM2837   |   4   |    16K    |    16K    |    512K   |    [1]    |
496 			 *  | Exynos 7420        | 4(+4) |    32K    |    32K    |    256K   |  [2, 3]   |
497 			 *  | Exynos 8890        | 4(+4) |    32K    |    32K    |    256K   |    [4]    |
498 			 *  | Rochchip RK3368    |  4+4  |    32K    |    32K    | 512K+256K |   sysfs   |
499 			 *  | MediaTek MT8173C   | 2(+2) |    32K    |    32K    | 512K(+1M) |   sysfs   |
500 			 *  | Snapdragon 410     |   4   |    32K    |    32K    |    512K   |    [3]    |
501 			 *  | Snapdragon 630     |  4+4  |    32K    |    32K    |  1M+512K  |   sysfs   |
502 			 *  | Snapdragon 636     | 4(+4) |  32K+64K  |  32K+64K  |   1M+1M   |   sysfs   |
503 			 *  | Snapdragon 660     | 4(+4) |  32K+64K  |  32K+64K  |   1M+1M   |   sysfs   |
504 			 *  | Snapdragon 835     | 4(+4) |  32K+64K  |  32K+64K  |  1M(+2M)  |   sysfs   |
505 			 *  | Kirin 620          |  4+4  |    32K    |    32K    |    512K   |    [5]    |
506 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
507 			 *
508 			 * [1] https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766
509 			 * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
510 			 * [3] https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf
511 			 * [4] http://www.boardset.com/products/products_v8890.php
512 			 * [5] http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
513 			 */
514 			if (midr_is_qualcomm_cortex_a53_silver(midr)) {
515 				/* Qualcomm-modified Cortex-A53 in Snapdragon 630/660/835 */
516 
517 				uint32_t l2_size = 512 * 1024;
518 				switch (chipset->series) {
519 					case cpuinfo_arm_chipset_series_qualcomm_msm:
520 						if (chipset->model == 8998) {
521 							/* Snapdragon 835 (MSM8998): 1 MB L2 (little cores only) */
522 							l2_size = 1024 * 1024;
523 						}
524 						break;
525 					case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
526 						switch (chipset->model) {
527 							case 630:
528 								if (cluster_id == 0) {
529 									/* Snapdragon 630: 1 MB L2 for the big cores */
530 									l2_size = 1024 * 1024;
531 								}
532 								break;
533 							case 636:
534 								/* Snapdragon 636: 1 MB L2 (little cores only) */
535 								l2_size = 1024 * 1024;
536 								break;
537 							case 660:
538 							case 662:
539 								/* Snapdragon 660: 1 MB L2 (little cores only) */
540 								l2_size = 1024 * 1024;
541 								break;
542 						}
543 						break;
544 					default:
545 						break;
546 				}
547 
548 				*l1i = (struct cpuinfo_cache) {
549 					.size = 32 * 1024,
550 					.associativity = 2,
551 					.line_size = 64
552 				};
553 				*l1d = (struct cpuinfo_cache) {
554 					.size = 32 * 1024,
555 					.associativity = 4,
556 					.line_size = 64
557 				};
558 				*l2 = (struct cpuinfo_cache) {
559 					.size = l2_size,
560 					.associativity = 16,
561 					.line_size = 64
562 				};
563 			} else {
564 				/* Standard Cortex-A53 */
565 
566 				/* Use conservative values by default */
567 				uint32_t l1_size = 16 * 1024;
568 				uint32_t l2_size = 256 * 1024;
569 				switch (chipset->series) {
570 					case cpuinfo_arm_chipset_series_qualcomm_msm:
571 						l1_size = 32 * 1024;
572 						l2_size = 512 * 1024;
573 						switch (chipset->model) {
574 							case 8937: /* Snapdragon 430 */
575 							case 8940: /* Snapdragon 435 */
576 							case 8953: /* Snapdragon 625 or 626 (8953PRO) */
577 								if (cluster_id == 0) {
578 									/* 1M L2 for big cluster */
579 									l2_size = 1024 * 1024;
580 								}
581 								break;
582 							case 8952: /* Snapdragon 617 */
583 								if (cluster_id != 0) {
584 									/* 256K L2 for LITTLE cluster */
585 									l2_size = 256 * 1024;
586 								}
587 								break;
588 							default:
589 								/* Silence compiler warning about unhandled enum values */
590 								break;
591 						}
592 						break;
593 					case cpuinfo_arm_chipset_series_qualcomm_apq:
594 						l1_size = 32 * 1024;
595 						l2_size = 512 * 1024;
596 						break;
597 					case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
598 						l1_size = 32 * 1024;
599 						l2_size = 512 * 1024;
600 						if (chipset->model == 450 && cluster_id == 0) {
601 							/* Snapdragon 450: 1M L2 for big cluster */
602 							l2_size = 1024 * 1024;
603 						}
604 						break;
605 					case cpuinfo_arm_chipset_series_hisilicon_hi:
606 						l1_size = 32 * 1024;
607 						l2_size = 512 * 1024;
608 						break;
609 					case cpuinfo_arm_chipset_series_hisilicon_kirin:
610 						l1_size = 32 * 1024;
611 						switch (chipset->model) {
612 							case 970: /* Kirin 970 */
613 								l2_size = 1024 * 1024;
614 								break;
615 							default:
616 								l2_size = 512 * 1024;
617 								break;
618 						}
619 						break;
620 					case cpuinfo_arm_chipset_series_mediatek_mt:
621 						switch (chipset->model) {
622 							case 8173:
623 								l1_size = 32 * 1024;
624 								l2_size = 512 * 1024;
625 								break;
626 						}
627 						break;
628 					case cpuinfo_arm_chipset_series_rockchip_rk:
629 						l1_size = 32 * 1024;
630 						switch (chipset->model) {
631 							case 3368:
632 								if (cluster_id == 0) {
633 									 /* RK3368: 512 KB L2 for the big cores */
634 									l2_size = 512 * 1024;
635 								}
636 								break;
637 						}
638 						break;
639 					case cpuinfo_arm_chipset_series_broadcom_bcm:
640 						switch (chipset->model) {
641 							case 2837: /* BCM2837 */
642 								l2_size = 512 * 1024;
643 								break;
644 						}
645 						break;
646 					case cpuinfo_arm_chipset_series_samsung_exynos:
647 						l1_size = 32 * 1024;
648 						break;
649 					default:
650 						/* Silence compiler warning about unhandled enum values */
651 						break;
652 				}
653 				*l1i = (struct cpuinfo_cache) {
654 					.size = l1_size,
655 					.associativity = 2,
656 					.line_size = 64
657 				};
658 				*l1d = (struct cpuinfo_cache) {
659 					.size = l1_size,
660 					.associativity = 4,
661 					.line_size = 64
662 				};
663 				*l2 = (struct cpuinfo_cache) {
664 					.size = l2_size,
665 					.associativity = 16,
666 					.line_size = 64
667 				};
668 			}
669 			break;
670 		case cpuinfo_uarch_cortex_a55r0:
671 		case cpuinfo_uarch_cortex_a55:
672 			/*
673 			 * ARM Cortex-A55 Core Technical Reference Manual
674 			 * A6.1. About the L1 memory system
675 			 *   The Cortex®-A55 core's L1 memory system enhances core performance and power efficiency.
676 			 *   It consists of separate instruction and data caches. You can configure instruction and data caches
677 			 *   independently during implementation to sizes of 16KB, 32KB, or 64KB.
678 			 *
679 			 *   L1 instruction-side memory system
680 			 *   The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:
681 			 *    - 64-byte instruction side cache line length.
682 			 *    - 4-way set associative L1 instruction cache.
683 			 *
684 			 *   L1 data-side memory system
685 			 *    - 64-byte data side cache line length.
686 			 *    - 4-way set associative L1 data cache.
687 			 *
688 			 * A7.1 About the L2 memory system
689 			 *   The Cortex-A55 L2 memory system is required to interface the Cortex-A55 cores to the L3 memory system.
690 			 *   The L2 memory subsystem consists of:
691 			 *    - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB or 256KB. Cache
692 			 *      lines have a fixed length of 64 bytes.
693 			 *
694 			 *   The main features of the L2 memory system are:
695 			 *    - Strictly exclusive with L1 data cache.
696 			 *    - Pseudo-inclusive with L1 instruction cache.
697 			 *    - Private per-core unified L2 cache.
698 			 *
699 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
700 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | L3 cache | Reference  |
701 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
702 			 *  | Snapdragon 845     | 4(+4) |    32K    |    32K    |    128K   |    2M    | [1], sysfs |
703 			 *  | Exynos 9810        | 4(+4) |     ?     |     ?     |    None   |   512K   |     [2]    |
704 			 *  | Kirin 980          | 4(+4) |    32K    |    32K    |    128K   |    4M    |     [3]    |
705 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
706 			 *
707 			 * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
708 			 * [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
709 			 * [3] https://en.wikichip.org/wiki/hisilicon/kirin/980
710 			 */
711 			if (midr_is_qualcomm_cortex_a55_silver(midr)) {
712 				/* Qualcomm-modified Cortex-A55 in Snapdragon 670 / 710 / 845 */
713 				uint32_t l3_size = 1024 * 1024;
714 				switch (chipset->series) {
715 					case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
716 						/* Snapdragon 845: 2M L3 cache */
717 						if (chipset->model == 845) {
718 							l3_size = 2 * 1024 * 1024;
719 						}
720 						break;
721 					default:
722 						break;
723 				}
724 
725 				*l1i = (struct cpuinfo_cache) {
726 					.size = 32 * 1024,
727 					.associativity = 4,
728 					.line_size = 64,
729 				};
730 				*l1d = (struct cpuinfo_cache) {
731 					.size = 32 * 1024,
732 					.associativity = 4,
733 					.line_size = 64,
734 				};
735 				*l2 = (struct cpuinfo_cache) {
736 					.size = 128 * 1024,
737 					.associativity = 4,
738 					.line_size = 64,
739 				};
740 				*l3 = (struct cpuinfo_cache) {
741 					.size = l3_size,
742 					.associativity = 16,
743 					.line_size = 64,
744 				};
745 			} else {
746 				/* Standard Cortex-A55 */
747 
748 				*l1i = (struct cpuinfo_cache) {
749 					.size = 32 * 1024,
750 					.associativity = 4,
751 					.line_size = 64,
752 				};
753 				*l1d = (struct cpuinfo_cache) {
754 					.size = 32 * 1024,
755 					.associativity = 4,
756 					.line_size = 64,
757 				};
758 				if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) {
759 					*l2 = (struct cpuinfo_cache) {
760 						.size = 512 * 1024,
761 						/* DynamIQ */
762 						.associativity = 16,
763 						.line_size = 64,
764 					};
765 				} else {
766 					uint32_t l3_size = 1024 * 1024;
767 					switch (chipset->series) {
768 						case cpuinfo_arm_chipset_series_hisilicon_kirin:
769 							/* Kirin 980: 4M L3 cache */
770 							if (chipset->model == 980) {
771 								l3_size = 4 * 1024 * 1024;
772 							}
773 							break;
774 						default:
775 							break;
776 					}
777 					*l2 = (struct cpuinfo_cache) {
778 						.size = 128 * 1024,
779 						.associativity = 4,
780 						.line_size = 64,
781 					};
782 					*l3 = (struct cpuinfo_cache) {
783 						.size = l3_size,
784 						/* DynamIQ */
785 						.associativity = 16,
786 						.line_size = 64,
787 					};
788 				}
789 			}
790 			break;
791 		case cpuinfo_uarch_cortex_a57:
792 			/*
793 			 * ARM Cortex-A57 MPCore Processor Technical Reference Manual:
794 			 * 6.1. About the L1 memory system
795 			 *   The L1 memory system consists of separate instruction and data caches.
796 			 *
797 			 *   The L1 instruction memory system has the following features:
798 			 *    - 48KB 3-way set-associative instruction cache.
799 			 *    - Fixed line length of 64 bytes.
800 			 *
801 			 *   The L1 data memory system has the following features:
802 			 *    - 32KB 2-way set-associative data cache.
803 			 *    - Fixed line length of 64 bytes.
804 			 *
805 			 * 7.1 About the L2 memory system
806 			 *   The features of the L2 memory system include:
807 			 *    - Configurable L2 cache size of 512KB, 1MB, and 2MB.
808 			 *    - Fixed line length of 64 bytes.
809 			 *    - 16-way set-associative cache structure.
810 			 *    - Inclusion property with L1 data caches.
811 			 *
812 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
813 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | Reference |
814 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
815 			 *  | Snapdragon 810     | 4(+4) |    32K    |    48K    |    2M     |    [1]    |
816 			 *  | Exynos 7420        | 4(+4) |    32K    |    48K    |    2M     |    [2]    |
817 			 *  | Jetson TX1         |   4   |    32K    |    48K    |    2M     |    [3]    |
818 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
819 			 *
820 			 * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview
821 			 * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2
822 			 * [3] https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/
823 			 */
824 			*l1i = (struct cpuinfo_cache) {
825 				.size = 48 * 1024,
826 				.associativity = 3,
827 				.line_size = 64
828 			};
829 			*l1d = (struct cpuinfo_cache) {
830 				.size = 32 * 1024,
831 				.associativity = 2,
832 				.line_size = 64
833 			};
834 			*l2 = (struct cpuinfo_cache) {
835 				.size = cluster_cores * 512 * 1024,
836 				.associativity = 16,
837 				.line_size = 64,
838 				.flags = CPUINFO_CACHE_INCLUSIVE
839 			};
840 			break;
841 		case cpuinfo_uarch_cortex_a65:
842 		{
843 			/*
844 			 * ARM Cortex‑A65 Core Technical Reference Manual
845 			 * A6.1. About the L1 memory system
846 			 *   The L1 memory system enhances the performance and power efficiency in the Cortex‑A65 core.
847 			 *   It consists of separate instruction and data caches. You can configure instruction and data caches
848 			 *   independently during implementation to sizes of 32KB or 64KB.
849 			 *
850 			 *   L1 instruction-side memory system
851 			 *   The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:
852 			 *    - 64-byte instruction side cache line length.
853 			 *    - 4-way set associative L1 instruction cache.
854 			 *
855 			 *   L1 data-side memory system
856 			 *    - 64-byte data side cache line length.
857 			 *    - 4-way set associative L1 data cache.
858 			 *
859 			 * A7.1 About the L2 memory system
860 			 *   The Cortex‑A65 L2 memory system is required to interface the Cortex‑A65 cores to the L3 memory system.
861 			 *   The L2 memory subsystem consists of:
862 			 *    - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB, or 256KB.
863 			 *      Cache lines have a fixed length of 64 bytes.
864 			 *
865 			 *   The main features of the L2 memory system are:
866 			 *    - Strictly exclusive with L1 data cache.
867 			 *    - Pseudo-inclusive with L1 instruction cache.
868 			 *    - Private per-core unified L2 cache.
869 			 */
870 			const uint32_t l1_size = 32 * 1024;
871 			const uint32_t l2_size = 128 * 1024;
872 			const uint32_t l3_size = 512 * 1024;
873 			*l1i = (struct cpuinfo_cache) {
874 				.size = l1_size,
875 				.associativity = 4,
876 				.line_size = 64,
877 			};
878 			*l1d = (struct cpuinfo_cache) {
879 				.size = l1_size,
880 				.associativity = 4,
881 				.line_size = 64,
882 			};
883 			*l2 = (struct cpuinfo_cache) {
884 				.size = l2_size,
885 				.associativity = 4,
886 				.line_size = 64,
887 				.flags = CPUINFO_CACHE_INCLUSIVE
888 			};
889 			*l3 = (struct cpuinfo_cache) {
890 				.size = l3_size,
891 				/* DynamIQ */
892 				.associativity = 16,
893 				.line_size = 64,
894 			};
895 			break;
896 		}
897 		case cpuinfo_uarch_cortex_a72:
898 		{
899 			/*
900 			 * ARM Cortex-A72 MPCore Processor Technical Reference Manual
901 			 * 6.1. About the L1 memory system
902 			 *   The L1 memory system consists of separate instruction and data caches.
903 			 *
904 			 *   The L1 instruction memory system has the following features:
905 			 *    - 48KB 3-way set-associative instruction cache.
906 			 *    - Fixed line length of 64 bytes.
907 			 *
908 			 *   The L1 data memory system has the following features:
909 			 *    - 32KB 2-way set-associative data cache.
910 			 *    - Fixed cache line length of 64 bytes.
911 			 *
912 			 * 7.1 About the L2 memory system
913 			 *   The features of the L2 memory system include:
914 			 *    - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
915 			 *    - Fixed line length of 64 bytes.
916 			 *    - Banked pipeline structures.
917 			 *    - Inclusion property with L1 data caches.
918 			 *    - 16-way set-associative cache structure.
919 			 *
920 			 *  +---------------------+---------+-----------+-----------+------------+-----------+
921 			 *  | Processor model     | Cores   | L1D cache | L1I cache | L2 cache   | Reference |
922 			 *  +---------------------+---------+-----------+-----------+------------+-----------+
923 			 *  | Snapdragon 650      |  2(+4)  | 32K(+32K) | 48K(+32K) |  1M(+512K) |    [1]    |
924 			 *  | Snapdragon 652      |  4(+4)  | 32K(+32K) | 48K(+32K) |  1M(+512K) |    [2]    |
925 			 *  | Snapdragon 653      |  4(+4)  | 32K(+32K) | 48K(+32K) |  1M(+512K) |    [3]    |
926 			 *  | HiSilicon Kirin 950 |  4(+4)  |  32K+32K  |  48K+32K  |     ?      |           |
927 			 *  | HiSilicon Kirin 955 |  4(+4)  |  32K+32K  |  48K+32K  |     ?      |           |
928 			 *  | MediaTek MT8173C    |  2(+2)  | 32K(+32K) | 48K(+32K) |  1M(+512K) |   sysfs   |
929 			 *  | MediaTek Helio X20  | 2(+4+4) |     ?     |     ?     |     ?      |           |
930 			 *  | MediaTek Helio X23  | 2(+4+4) |     ?     |     ?     |     ?      |           |
931 			 *  | MediaTek Helio X25  | 2(+4+4) |     ?     |     ?     |     ?      |           |
932 			 *  | MediaTek Helio X27  | 2(+4+4) |     ?     |     ?     |     ?      |           |
933 			 *  | Broadcom BCM2711    |    4    |    32K    |    48K    |     1M     |    [4]    |
934 			 *  +---------------------+---------+-----------+-----------+------------+-----------+
935 			 *
936 			 * [1] http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650
937 			 * [2] http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652
938 			 * [3] http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro
939 			 * [4] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
940 			 */
941 			uint32_t l2_size;
942 			switch (chipset->series) {
943 				case cpuinfo_arm_chipset_series_hisilicon_kirin:
944 					l2_size = 2 * 1024 * 1024;
945 					break;
946 				default:
947 					l2_size = 1024 * 1024;
948 					break;
949 			}
950 
951 			*l1i = (struct cpuinfo_cache) {
952 				.size = 48 * 1024,
953 				.associativity = 3,
954 				.line_size = 64
955 			};
956 			*l1d = (struct cpuinfo_cache) {
957 				.size = 32 * 1024,
958 				.associativity = 2,
959 				.line_size = 64
960 			};
961 			*l2 = (struct cpuinfo_cache) {
962 				.size = l2_size,
963 				.associativity = 16,
964 				.line_size = 64,
965 				.flags = CPUINFO_CACHE_INCLUSIVE
966 			};
967 			break;
968 		}
969 		case cpuinfo_uarch_cortex_a73:
970 		{
971 			/*
972 			 * ARM Cortex‑A73 MPCore Processor Technical Reference Manual
973 			 * 6.1. About the L1 memory system
974 			 *   The L1 memory system consists of separate instruction and data caches.
975 			 *   The size of the instruction cache is 64KB.
976 			 *   The size of the data cache is configurable to either 32KB or 64KB.
977 			 *
978 			 *   The L1 instruction memory system has the following key features:
979 			 *    - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.
980 			 *    - Fixed cache line length of 64 bytes.
981 			 *
982 			 *   The L1 data memory system has the following features:
983 			 *    - ...the data cache behaves like an eight-way set associative PIPT cache (for 32KB configurations)
984 			 *      and a 16-way set associative PIPT cache (for 64KB configurations).
985 			 *    - Fixed cache line length of 64 bytes.
986 			 *
987 			 * 7.1 About the L2 memory system
988 			 *   The L2 memory system consists of:
989 			 *    - A tightly-integrated L2 cache with:
990 			 *      - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB.
991 			 *      - A 16-way, set-associative structure.
992 			 *      - A fixed line length of 64 bytes.
993 			 *
994 			 * The ARM Cortex A73 - Artemis Unveiled [1]
995 			 *   "ARM still envisions that most vendors will choose to use configurations of 1 to
996 			 *    2MB in consumer products. The L2 cache is inclusive of the L1 cache. "
997 			 *
998 			 *  +---------------------+---------+-----------+-----------+-----------+-----------+
999 			 *  | Processor model     | Cores   | L1D cache | L1I cache | L2 cache  | Reference |
1000 			 *  +---------------------+---------+-----------+-----------+-----------+-----------+
1001 			 *  | HiSilicon Kirin 960 |  4(+4)  |  64K+32K  |  64K+32K  |     ?     |    [2]    |
1002 			 *  | MediaTek Helio X30  | 2(+4+4) |     ?     |  64K+ ?   |     ?     |           |
1003 			 *  | Snapdragon 636      |  4(+4)  | 64K(+32K) | 64K(+32K) |  1M(+1M)  |   sysfs   |
1004 			 *  | Snapdragon 660      |  4(+4)  |  64K+32K  |  64K+32K  |  1M(+1M)  |    [3]    |
1005 			 *  | Snapdragon 835      |  4(+4)  |  64K+32K  |  64K+32K  |  2M(+1M)  |   sysfs   |
1006 			 *  +---------------------+---------+-----------+-----------+-----------+-----------+
1007 			 *
1008 			 * [1] http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2
1009 			 * [2] http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3
1010 			 * [3] https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/
1011 			 */
1012 			uint32_t l1d_size = 32 * 1024;
1013 			uint32_t l2_size = 512 * 1024;
1014 			switch (chipset->series) {
1015 				case cpuinfo_arm_chipset_series_hisilicon_kirin:
1016 					l1d_size = 64 * 1024;
1017 					l2_size = 2 * 1024 * 1024;
1018 					break;
1019 				case cpuinfo_arm_chipset_series_mediatek_mt:
1020 					l1d_size = 64 * 1024;
1021 					l2_size = 1 * 1024 * 1024; /* TODO: verify assumption */
1022 					break;
1023 				default:
1024 					switch (midr) {
1025 						case UINT32_C(0x51AF8001): /* Kryo 280 Gold */
1026 							l1d_size = 64 * 1024;
1027 							l2_size = 2 * 1024 * 1024;
1028 							break;
1029 						case UINT32_C(0x51AF8002): /* Kryo 260 Gold */
1030 							l1d_size = 64 * 1024;
1031 							l2_size = 1 * 1024 * 1024;
1032 							break;
1033 					}
1034 			}
1035 
1036 			*l1i = (struct cpuinfo_cache) {
1037 				.size = 64 * 1024,
1038 				.associativity = 4,
1039 				.line_size = 64
1040 			};
1041 			*l1d = (struct cpuinfo_cache) {
1042 				.size = l1d_size,
1043 				.associativity = (l1d_size >> 12),
1044 				.line_size = 64
1045 			};
1046 			*l2 = (struct cpuinfo_cache) {
1047 				.size = l2_size,
1048 				.associativity = 16,
1049 				.line_size = 64,
1050 				.flags = CPUINFO_CACHE_INCLUSIVE
1051 			};
1052 			break;
1053 		}
1054 		case cpuinfo_uarch_cortex_a75:
1055 		{
1056 			/*
1057 			 * ARM Cortex-A75 Core Technical Reference Manual
1058 			 * A6.1. About the L1 memory system
1059 			 *   The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
1060 			 *
1061 			 * A6.1.1 L1 instruction-side memory system
1062 			 *   The L1 instruction memory system has the following key features:
1063 			 *    - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.
1064 			 *    - Fixed cache line length of 64 bytes.
1065 			 *
1066 			 * A6.1.2 L1 data-side memory system
1067 			 *   The L1 data memory system has the following features:
1068 			 *    - Physically Indexed, Physically Tagged (PIPT), 16-way set-associative L1 data cache.
1069 			 *    - Fixed cache line length of 64 bytes.
1070 			 *    - Pseudo-random cache replacement policy.
1071 			 *
1072 			 * A7.1 About the L2 memory system
1073 			 *   The L2 memory subsystem consist of:
1074 			 *    - An 8-way set associative L2 cache with a configurable size of 256KB or 512KB.
1075 			 *      Cache lines have a fixed length of 64 bytes.
1076 			 *
1077 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1078 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | L3 cache | Reference  |
1079 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1080 			 *  | Snapdragon 845     | 4(+4) |    64K    |    64K    |    256K   |    2M    | [1], sysfs |
1081 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1082 			 *
1083 			 * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
1084 			 */
1085 			uint32_t l3_size = 1024 * 1024;
1086 			switch (chipset->series) {
1087 				case cpuinfo_arm_chipset_series_qualcomm_snapdragon:
1088 					/* Snapdragon 845: 2M L3 cache */
1089 					if (chipset->model == 845) {
1090 						l3_size = 2 * 1024 * 1024;
1091 					}
1092 					break;
1093 				default:
1094 					break;
1095 			}
1096 			*l1i = (struct cpuinfo_cache) {
1097 				.size = 64 * 1024,
1098 				.associativity = 4,
1099 				.line_size = 64
1100 			};
1101 			*l1d = (struct cpuinfo_cache) {
1102 				.size = 64 * 1024,
1103 				.associativity = 16,
1104 				.line_size = 64
1105 			};
1106 			*l2 = (struct cpuinfo_cache) {
1107 				.size = 256 * 1024,
1108 				.associativity = 8,
1109 				.line_size = 64
1110 			};
1111 			*l3 = (struct cpuinfo_cache) {
1112 				.size = l3_size,
1113 				.associativity = 16,
1114 				.line_size = 64
1115 			};
1116 			break;
1117 		}
1118 		case cpuinfo_uarch_cortex_a76:
1119 		{
1120 			/*
1121 			 * ARM Cortex-A76 Core Technical Reference Manual
1122 			 * A6.1. About the L1 memory system
1123 			 *   The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
1124 			 *
1125 			 * A6.1.1 L1 instruction-side memory system
1126 			 *   The L1 instruction memory system has the following key features:
1127 			 *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1128 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1129 			 *    - Fixed cache line length of 64 bytes.
1130 			 *
1131 			 * A6.1.2 L1 data-side memory system
1132 			 *   The L1 data memory system has the following features:
1133 			 *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1134 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1135 			 *    - Fixed cache line length of 64 bytes.
1136 			 *    - Pseudo-LRU cache replacement policy.
1137 			 *
1138 			 * A7.1 About the L2 memory system
1139 			 *   The L2 memory subsystem consist of:
1140 			 *    - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB.
1141 			 *      Cache lines have a fixed length of 64 bytes.
1142 			 *    - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
1143 			 *    - Dynamic biased replacement policy.
1144 			 *    - Modified Exclusive Shared Invalid (MESI) coherency.
1145 			 *
1146 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1147 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | L3 cache | Reference  |
1148 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1149 			 *  | Kirin 980          | 4(+4) |    64K    |    64K    |    512K   |    4M    |  [1], [2]  |
1150 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1151 			 *
1152 			 * [1] https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm
1153 			 * [2] https://en.wikichip.org/wiki/hisilicon/kirin/980
1154 			 */
1155 			uint32_t l2_size = 256 * 1024;
1156 			uint32_t l3_size = 1024 * 1024;
1157 			switch (chipset->series) {
1158 				case cpuinfo_arm_chipset_series_hisilicon_kirin:
1159 					/* Kirin 980: 512K L2 cache + 4M L3 cache */
1160 					if (chipset->model == 980) {
1161 						l2_size = 512 * 1024;
1162 						l3_size = 4 * 1024 * 1024;
1163 					}
1164 					break;
1165 				default:
1166 					break;
1167 			}
1168 			*l1i = (struct cpuinfo_cache) {
1169 				.size = 64 * 1024,
1170 				.associativity = 4,
1171 				.line_size = 64,
1172 			};
1173 			*l1d = (struct cpuinfo_cache) {
1174 				.size = 64 * 1024,
1175 				.associativity = 4,
1176 				.line_size = 64,
1177 			};
1178 			*l2 = (struct cpuinfo_cache) {
1179 				.size = l2_size,
1180 				.associativity = 8,
1181 				.line_size = 64,
1182 				.flags = CPUINFO_CACHE_INCLUSIVE,
1183 			};
1184 			*l3 = (struct cpuinfo_cache) {
1185 				.size = l3_size,
1186 				.associativity = 16,
1187 				.line_size = 64,
1188 			};
1189 			break;
1190 		}
1191 		case cpuinfo_uarch_cortex_a77:
1192 		{
1193 			/*
1194 			 * ARM Cortex-A77 Core Technical Reference Manual
1195 			 * A6.1. About the L1 memory system
1196 			 *   The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
1197 			 *
1198 			 * A6.1.1 L1 instruction-side memory system
1199 			 *   The L1 instruction memory system has the following key features:
1200 			 *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1201 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1202 			 *    - Fixed cache line length of 64 bytes.
1203 			 *
1204 			 * A6.1.2 L1 data-side memory system
1205 			 *   The L1 data memory system has the following features:
1206 			 *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1207 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1208 			 *    - Fixed cache line length of 64 bytes.
1209 			 *    - Pseudo-LRU cache replacement policy.
1210 			 *
1211 			 * A7.1 About the L2 memory system
1212 			 *   The L2 memory subsystem consist of:
1213 			 *    - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache lines
1214 			 *      have a fixed length of 64 bytes.
1215 			 *    - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
1216 			 */
1217 			const uint32_t l2_size = 256 * 1024;
1218 			const uint32_t l3_size = 1024 * 1024;
1219 			*l1i = (struct cpuinfo_cache) {
1220 				.size = 64 * 1024,
1221 				.associativity = 4,
1222 				.line_size = 64,
1223 			};
1224 			*l1d = (struct cpuinfo_cache) {
1225 				.size = 64 * 1024,
1226 				.associativity = 4,
1227 				.line_size = 64,
1228 			};
1229 			*l2 = (struct cpuinfo_cache) {
1230 				.size = l2_size,
1231 				.associativity = 8,
1232 				.line_size = 64,
1233 				.flags = CPUINFO_CACHE_INCLUSIVE,
1234 			};
1235 			*l3 = (struct cpuinfo_cache) {
1236 				.size = l3_size,
1237 				.associativity = 16,
1238 				.line_size = 64,
1239 			};
1240 			break;
1241 		}
1242 		case cpuinfo_uarch_neoverse_n1:
1243 		case cpuinfo_uarch_neoverse_v1:
1244 		case cpuinfo_uarch_neoverse_n2:
1245 		{
1246                         /*
1247                          * ARM Neoverse-n1 Core Technical Reference Manual
1248                          * A6.1. About the L1 memory system
1249 			 *   The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
1250                          *
1251                          * A6.1.1 L1 instruction-side memory system
1252                          *   The L1 instruction memory system has the following key features:
1253                          *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1254                          *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1255                          *    - Fixed cache line length of 64 bytes.
1256                          *
1257                          * A6.1.2 L1 data-side memory system
1258                          *   The L1 data memory system has the following features:
1259                          *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
1260                          *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
1261                          *    - Fixed cache line length of 64 bytes.
1262                          *    - Pseudo-LRU cache replacement policy.
1263                          *
1264                          * A7.1 About the L2 memory system
1265                          *   The L2 memory subsystem consist of:
1266 			 *    - An 8-way set associative L2 cache with a configurable size of 256KB, 512KB, or 1024KB. Cache lines
1267 			 *      have a fixed length of 64 bytes.
1268                          *    - Strictly inclusive with L1 data cache.
1269 			 *    - When configured with instruction cache hardware coherency, strictly inclusive with L1 instruction cache.
1270 			 *    - When configured without instruction cache hardware coherency, weakly inclusive with L1 instruction cache.
1271                          */
1272 
1273 			const uint32_t min_l2_size_KB= 256;
1274 			const uint32_t min_l3_size_KB = 0;
1275 
1276 			*l1i = (struct cpuinfo_cache) {
1277 				.size = 64 * 1024,
1278 				.associativity = 4,
1279 				.line_size = 64,
1280 			};
1281 			*l1d = (struct cpuinfo_cache) {
1282 				.size = 64 * 1024,
1283 				.associativity = 4,
1284 				.line_size = 64,
1285 			};
1286 			*l2 = (struct cpuinfo_cache) {
1287 				.size = min_l2_size_KB * 1024,
1288 				.associativity = 8,
1289 				.line_size = 64,
1290 				.flags = CPUINFO_CACHE_INCLUSIVE,
1291 			};
1292 			*l3 = (struct cpuinfo_cache) {
1293 				.size = min_l3_size_KB * 1024,
1294 				.associativity = 16,
1295 				.line_size = 64,
1296 			};
1297 			break;
1298 		}
1299 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
1300 		case cpuinfo_uarch_scorpion:
1301 			/*
1302 			 * - "The CPU includes 32KB instruction and data caches as
1303 			 *    well as a complete memory-management unit (MMU) suitable
1304 			 *    for high-level operating systems. The CPU also has
1305 			 *    256KB of SRAM that can be allocated in 64KB increments
1306 			 *    to level-two (L2) cache or tightly coupled memory (TCM)." [1]
1307 			 *    We interpret it as L2 cache being 4-way set-associative on single-core Scorpion.
1308 			 * - L1 Data Cache = 32 KB. 32 B/line. [2]
1309              * - L2 Cache = 256 KB. 128 B/line. [2]
1310 			 * - 256 KB (single-core) or 512 KB (dual-core) L2 cache [3]
1311 			 * - Single or dual-core configuration [3]
1312 			 * - For L1 cache assume the same associativity as Krait
1313 			 *
1314 			 * [1] https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf
1315 			 * [2] http://www.7-cpu.com/cpu/Snapdragon.html
1316 			 * [3] https://en.wikipedia.org/wiki/Scorpion_(CPU)
1317 			 */
1318 			*l1i = (struct cpuinfo_cache) {
1319 				.size = 32 * 1024,
1320 				.associativity = 4,
1321 				.line_size = 32
1322 			};
1323 			*l1d = (struct cpuinfo_cache) {
1324 				.size = 32 * 1024,
1325 				.associativity = 4,
1326 				.line_size = 32
1327 			};
1328 			*l2 = (struct cpuinfo_cache) {
1329 				.size = cluster_cores * 256 * 1024,
1330 				.associativity = 4,
1331 				.line_size = 128
1332 			};
1333 			break;
1334 		case cpuinfo_uarch_krait:
1335 			/*
1336 			 * - L0 Data cache = 4 KB. 64 B/line, direct mapped [1]
1337 			 * - L0 Instruction cache = 4 KB. [1]
1338 			 * - L1 Data cache = 16 KB. 64 B/line, 4-way [1]
1339 			 * - L1 Instruction cache = 16 KB, 4-way [1]
1340 			 * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has fast access only to 512 KB of L2 cache. [1]
1341 			 * - L2	= 1MB (dual core) or 2MB (quad core), 8-way set associative [2]
1342 			 *
1343 			 * [1] http://www.7-cpu.com/cpu/Krait.html
1344 			 * [2] http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2
1345 			 */
1346 			*l1i = (struct cpuinfo_cache) {
1347 				.size = 16 * 1024,
1348 				.associativity = 4,
1349 				.line_size = 64 /* assume same as L1D */
1350 			};
1351 			*l1d = (struct cpuinfo_cache) {
1352 				.size = 16 * 1024,
1353 				.associativity = 4,
1354 				.line_size = 64
1355 			};
1356 			*l2 = (struct cpuinfo_cache) {
1357 				.size = cluster_cores * 512 * 1024,
1358 				.associativity = 8,
1359 				.line_size = 128
1360 			};
1361 			break;
1362 #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */
1363 		case cpuinfo_uarch_kryo:
1364 			/*
1365 			 *  +-----------------+-------+-----------+-----------+-----------+-----------+
1366 			 *  | Processor model | Cores | L1D cache | L1I cache | L2 cache  | Reference |
1367 			 *  +-----------------+-------+-----------+-----------+-----------+-----------+
1368 			 *  | Snapdragon 820  |  2+2  |    24K    |    32K    |  1M+512K  |   [1, 2]  |
1369 			 *  | Snapdragon 821  |  2+2  |     ?     |     ?     |  1M+512K  |    [1]    |
1370 			 *  +-----------------+-------+-----------+-----------+-----------+-----------+
1371 			 *
1372 			 * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview/2
1373 			 * [2] https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf
1374 			 */
1375 			*l1i = (struct cpuinfo_cache) {
1376 				.size = 32 * 1024,
1377 				.associativity = 4,
1378 				.line_size = 64
1379 			};
1380 			*l1d = (struct cpuinfo_cache) {
1381 				.size = 24 * 1024,
1382 				.associativity = 3,
1383 				.line_size = 64
1384 			};
1385 			if (midr_is_kryo_silver(midr)) {
1386 				/* Kryo "Silver" */
1387 				*l2 = (struct cpuinfo_cache) {
1388 					.size = 512 * 1024,
1389 					.associativity = 8,
1390 					.line_size = 128
1391 				};
1392 			} else {
1393 				/* Kryo "Gold" */
1394 				*l2 = (struct cpuinfo_cache) {
1395 					.size = 1024 * 1024,
1396 					.associativity = 8,
1397 					.line_size = 128
1398 				};
1399 			}
1400 			break;
1401 		case cpuinfo_uarch_denver:
1402 		case cpuinfo_uarch_denver2:
1403 			/*
1404 			 * The Denver chip includes a 128KB, 4-way level 1 instruction cache, a 64KB, 4-way level 2 data cache,
1405 			 * and a 2MB, 16-way level 2 cache, all of which can service both cores. [1]
1406 			 *
1407 			 * All the caches have 64-byte lines. [2]
1408 			 *
1409 			 * [1] http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html
1410 			 * [2] http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014
1411 			 */
1412 			*l1i = (struct cpuinfo_cache) {
1413 				.size = 128 * 1024,
1414 				.associativity = 4,
1415 				.line_size = 64
1416 			};
1417 			*l1d = (struct cpuinfo_cache) {
1418 				.size = 64 * 1024,
1419 				.associativity = 4,
1420 				.line_size = 64
1421 			};
1422 			*l2 = (struct cpuinfo_cache) {
1423 				.size = 2 * 1024 * 1024,
1424 				.associativity = 16,
1425 				.line_size = 64
1426 			};
1427 			break;
1428 		case cpuinfo_uarch_exynos_m1:
1429 		case cpuinfo_uarch_exynos_m2:
1430 			/*
1431 			 * - "Moving past branch prediction we can see some elements of how the cache is set up for the L1 I$,
1432 			 *    namely 64 KB split into four sets with 128-byte line sizes for 128 cache lines per set" [1]
1433 			 * - "For loads and stores, a 32 KB, 8-way set associative cache with 64 byte line size is used" [1]
1434 			 * - "The L2 cache here is 2MB shared across all cores split into 16 sets. This memory is also split
1435 			 *    into 4 banks and has a 22 cycle latency" [1]
1436 			 *
1437 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
1438 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | Reference |
1439 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
1440 			 *  | Exynos 8 Octa 8890 | 4(+4) |    64K    |    32K    |    2M     |    [1]    |
1441 			 *  | Exynos 8 Octa 8895 | 4(+4) |    64K    |    32K    |    2M     |    [2]    |
1442 			 *  +--------------------+-------+-----------+-----------+-----------+-----------+
1443 			 *
1444 			 * [1] http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed
1445 			 * [2] https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market
1446 			 */
1447 			*l1i = (struct cpuinfo_cache) {
1448 				.size = 64 * 1024,
1449 				.associativity = 4,
1450 				.line_size = 128
1451 			};
1452 			*l1d = (struct cpuinfo_cache) {
1453 				.size = 32 * 1024,
1454 				.associativity = 8,
1455 				.line_size = 64
1456 			};
1457 			*l2 = (struct cpuinfo_cache) {
1458 				.size = 2 * 1024 * 1024,
1459 				.associativity = 16,
1460 				.line_size = 64
1461 			};
1462 			break;
1463 		case cpuinfo_uarch_exynos_m3:
1464 			/*
1465 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1466 			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | L3 cache | Reference  |
1467 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1468 			 *  | Exynos 9810        | 4(+4) |    64K    |     ?     |    512K   |    4M    |     [1]    |
1469 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
1470 			 *
1471 			 * [1] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
1472 			 */
1473 			*l1i = (struct cpuinfo_cache) {
1474 				.size = 64 * 1024 /* assume same as in Exynos M1/M2 cores */,
1475 				.associativity = 4 /* assume same as in Exynos M1/M2 cores */,
1476 				.line_size = 128 /* assume same as in Exynos M1/M2 cores */
1477 			};
1478 			*l1d = (struct cpuinfo_cache) {
1479 				.size = 64 * 1024,
1480 				.associativity = 8 /* assume same as in Exynos M1/M2 cores */,
1481 				.line_size = 64 /* assume same as in Exynos M1/M2 cores */,
1482 			};
1483 			*l2 = (struct cpuinfo_cache) {
1484 				.size = 512 * 1024,
1485 				.associativity = 16 /* assume same as in Exynos M1/M2 cores */,
1486 				.line_size = 64 /* assume same as in Exynos M1/M2 cores */,
1487 			};
1488 			*l3 = (struct cpuinfo_cache) {
1489 				.size = 4 * 1024 * 1024,
1490 				.associativity = 16 /* assume DynamIQ cache */,
1491 				.line_size = 64 /* assume DynamIQ cache */,
1492 			};
1493 			break;
1494 #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__)
1495 		case cpuinfo_uarch_thunderx:
1496 			/*
1497 			 * "78K-Icache and 32K-D cache per core, 16 MB shared L2 cache" [1]
1498 			 *
1499 			 * [1] https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf
1500 			 */
1501 			*l1i = (struct cpuinfo_cache) {
1502 				.size = 78 * 1024,
1503 				.associativity = 4 /* assumption */,
1504 				.line_size = 64 /* assumption */
1505 			};
1506 			*l1d = (struct cpuinfo_cache) {
1507 				.size = 32 * 1024,
1508 				.associativity = 4 /* assumption */,
1509 				.line_size = 64 /* assumption */
1510 			};
1511 			*l2 = (struct cpuinfo_cache) {
1512 				.size = 16 * 1024 * 1024,
1513 				.associativity = 8 /* assumption */,
1514 				.line_size = 64 /* assumption */
1515 			};
1516 			break;
1517 		case cpuinfo_uarch_taishan_v110:
1518 			/*
1519 			 * It features private 64 KiB L1 instruction and data caches as well as 512 KiB of private L2. [1]
1520 			 *
1521 			 *  +------------------+-------+-----------+-----------+-----------+----------+-----------+
1522 			 *  | Processor model  | Cores | L1D cache | L1I cache | L2 cache  | L3 cache | Reference |
1523 			 *  +------------------+-------+-----------+-----------+-----------+----------+-----------+
1524 			 *  | Kunpeng 920-3226 |  32   |    64K    |    64K    |    512K   |    32M   |     [2]   |
1525 			 *  +------------------+-------+-----------+-----------+-----------+----------+-----------+
1526 			 *  | Kunpeng 920-4826 |  48   |    64K    |    64K    |    512K   |    48M   |     [3]   |
1527 			 *  +------------------+-------+-----------+-----------+-----------+----------+-----------+
1528 			 *  | Kunpeng 920-6426 |  64   |    64K    |    64K    |    512K   |    64M   |     [4]   |
1529 			 *  +------------------+-------+-----------+-----------+-----------+----------+-----------+
1530 			 *
1531 			 * [1] https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110
1532 			 * [2] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226
1533 			 * [3] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826
1534 			 * [4] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426
1535 			 */
1536 			*l1i = (struct cpuinfo_cache) {
1537 				.size = 64 * 1024,
1538 				.associativity = 4 /* assumption */,
1539 				.line_size = 128 /* assumption */,
1540 			};
1541 			*l1d = (struct cpuinfo_cache) {
1542 				.size = 64 * 1024,
1543 				.associativity = 4 /* assumption */,
1544 				.line_size = 128 /* assumption */,
1545 			};
1546 			*l2 = (struct cpuinfo_cache) {
1547 				.size = 512 * 1024,
1548 				.associativity = 8 /* assumption */,
1549 				.line_size = 128 /* assumption */,
1550 				.flags = CPUINFO_CACHE_INCLUSIVE /* assumption */,
1551 			};
1552 			*l3 = (struct cpuinfo_cache) {
1553 				.size = cluster_cores * 1024 * 1024,
1554 				.associativity = 16 /* assumption */,
1555 				.line_size = 128 /* assumption */,
1556 			};
1557 			break;
1558 #endif
1559 		case cpuinfo_uarch_cortex_a12:
1560 		case cpuinfo_uarch_cortex_a32:
1561 		default:
1562 			cpuinfo_log_warning("target uarch not recognized; using generic cache parameters");
1563 			/* Follow OpenBLAS */
1564 			if (arch_version >= 8) {
1565 				*l1i = (struct cpuinfo_cache) {
1566 					.size = 32 * 1024,
1567 					.associativity = 4,
1568 					.line_size = 64
1569 				};
1570 				*l1d = (struct cpuinfo_cache) {
1571 					.size = 32 * 1024,
1572 					.associativity = 4,
1573 					.line_size = 64
1574 				};
1575 				*l2 = (struct cpuinfo_cache) {
1576 					.size = cluster_cores * 256 * 1024,
1577 					.associativity = 8,
1578 					.line_size = 64
1579 				};
1580 			} else {
1581 				*l1i = (struct cpuinfo_cache) {
1582 					.size = 16 * 1024,
1583 					.associativity = 4,
1584 					.line_size = 32
1585 				};
1586 				*l1d = (struct cpuinfo_cache) {
1587 					.size = 16 * 1024,
1588 					.associativity = 4,
1589 					.line_size = 32
1590 				};
1591 				if (arch_version >= 7) {
1592 					*l2 = (struct cpuinfo_cache) {
1593 						.size = cluster_cores * 128 * 1024,
1594 						.associativity = 8,
1595 						.line_size = 32
1596 					};
1597 				}
1598 			}
1599 			break;
1600 	}
1601 	l1i->sets = l1i->size / (l1i->associativity * l1i->line_size);
1602 	l1i->partitions = 1;
1603 	l1d->sets = l1d->size / (l1d->associativity * l1d->line_size);
1604 	l1d->partitions = 1;
1605 	if (l2->size != 0) {
1606 		l2->sets = l2->size / (l2->associativity * l2->line_size);
1607 		l2->partitions = 1;
1608 		if (l3->size != 0) {
1609 			l3->sets = l3->size / (l3->associativity * l3->line_size);
1610 			l3->partitions = 1;
1611 		}
1612 	}
1613 }
1614 
cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor * processor)1615 uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* processor) {
1616 	/*
1617 	 * There is no precise way to detect cache size on ARM/ARM64, and cache size reported by cpuinfo
1618 	 * may underestimate the actual cache size. Thus, we use microarchitecture-specific maximum.
1619 	 */
1620 	switch (processor->core->uarch) {
1621 		case cpuinfo_uarch_xscale:
1622 		case cpuinfo_uarch_arm11:
1623 		case cpuinfo_uarch_scorpion:
1624 		case cpuinfo_uarch_krait:
1625 		case cpuinfo_uarch_kryo:
1626 		case cpuinfo_uarch_exynos_m1:
1627 		case cpuinfo_uarch_exynos_m2:
1628 		case cpuinfo_uarch_exynos_m3:
1629 			/* cpuinfo-detected cache size always correct */
1630 			return cpuinfo_compute_max_cache_size(processor);
1631 		case cpuinfo_uarch_cortex_a5:
1632 			/* Max observed (NXP Vybrid SoC) */
1633 			return 512 * 1024;
1634 		case cpuinfo_uarch_cortex_a7:
1635 			/*
1636 			 * Cortex-A7 MPCore Technical Reference Manual:
1637 			 * 7.1. About the L2 Memory system
1638 			 *   The L2 memory system consists of an:
1639 			 *    - Optional tightly-coupled L2 cache that includes:
1640 			 *      - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB.
1641 			 */
1642 			return 1024 * 1024;
1643 		case cpuinfo_uarch_cortex_a8:
1644 			/*
1645 			 * Cortex-A8 Technical Reference Manual:
1646 			 * 8.1. About the L2 memory system
1647 			 *   The key features of the L2 memory system include:
1648 			 *    - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB
1649 			 */
1650 			return 1024 * 1024;
1651 		case cpuinfo_uarch_cortex_a9:
1652 			/* Max observed (e.g. Exynos 4212) */
1653 			return 1024 * 1024;
1654 		case cpuinfo_uarch_cortex_a12:
1655 		case cpuinfo_uarch_cortex_a17:
1656 			/*
1657 			 * ARM Cortex-A17 MPCore Processor Technical Reference Manual:
1658 			 * 7.1. About the L2 Memory system
1659 			 *   The key features of the L2 memory system include:
1660 			 *    - An integrated L2 cache:
1661 			 *      - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB.
1662 			 */
1663 			return 8 * 1024 * 1024;
1664 		case cpuinfo_uarch_cortex_a15:
1665 			/*
1666 			 * ARM Cortex-A15 MPCore Processor Technical Reference Manual:
1667 			 * 7.1. About the L2 memory system
1668 			 *   The features of the L2 memory system include:
1669 			 *    - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
1670 			 */
1671 			return 4 * 1024 * 1024;
1672 		case cpuinfo_uarch_cortex_a35:
1673 			/*
1674 			 * ARM Cortex‑A35 Processor Technical Reference Manual:
1675 			 * 7.1 About the L2 memory system
1676 			 *   L2 cache
1677 			 *    - Further features of the L2 cache are:
1678 			 *      - Configurable size of 128KB, 256KB, 512KB, and 1MB.
1679 			 */
1680 			return 1024 * 1024;
1681 		case cpuinfo_uarch_cortex_a53:
1682 			/*
1683 			 * ARM Cortex-A53 MPCore Processor Technical Reference Manual:
1684 			 * 7.1. About the L2 memory system
1685 			 *   The L2 memory system consists of an:
1686 			 *    - Optional tightly-coupled L2 cache that includes:
1687 			 *      - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB.
1688 			 */
1689 			return 2 * 1024 * 1024;
1690 		case cpuinfo_uarch_cortex_a57:
1691 			/*
1692 			 * ARM Cortex-A57 MPCore Processor Technical Reference Manual:
1693 			 * 7.1 About the L2 memory system
1694 			 *   The features of the L2 memory system include:
1695 			 *    - Configurable L2 cache size of 512KB, 1MB, and 2MB.
1696 			 */
1697 			return 2 * 1024 * 1024;
1698 		case cpuinfo_uarch_cortex_a72:
1699 			/*
1700 			 * ARM Cortex-A72 MPCore Processor Technical Reference Manual:
1701 			 * 7.1 About the L2 memory system
1702 			 *   The features of the L2 memory system include:
1703 			 *    - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
1704 			 */
1705 			return 4 * 1024 * 1024;
1706 		case cpuinfo_uarch_cortex_a73:
1707 			/*
1708 			 * ARM Cortex‑A73 MPCore Processor Technical Reference Manual
1709 			 * 7.1 About the L2 memory system
1710 			 *   The L2 memory system consists of:
1711 			 *    - A tightly-integrated L2 cache with:
1712 			 *       - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB.
1713 			 */
1714 			return 8 * 1024 * 1024;
1715 		case cpuinfo_uarch_cortex_a55:
1716 		case cpuinfo_uarch_neoverse_n1:
1717 		case cpuinfo_uarch_neoverse_v1:
1718 		case cpuinfo_uarch_neoverse_n2:
1719 		case cpuinfo_uarch_cortex_a75:
1720 		case cpuinfo_uarch_cortex_a76:
1721 		case cpuinfo_uarch_exynos_m4:
1722 		default:
1723 			/*
1724 			 * ARM DynamIQ Shared Unit Technical Reference Manual
1725 			 * 1.3 Implementation options
1726 			 *   L3_CACHE_SIZE
1727 			 *    - 256KB
1728 			 *    - 512KB
1729 			 *    - 1024KB
1730 			 *    - 1536KB
1731 			 *    - 2048KB
1732 			 *    - 3072KB
1733 			 *    - 4096KB
1734 			 */
1735 			return 4 * 1024 * 1024;
1736 	}
1737 }
1738