1 // Copyright 2022 Google LLC 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_ 16 #define CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_ 17 18 #include "cpu_features_cache_info.h" 19 #include "cpu_features_macros.h" 20 21 #if !defined(CPU_FEATURES_ARCH_RISCV) 22 #error "Including cpuinfo_riscv.h from a non-riscv target." 23 #endif 24 25 CPU_FEATURES_START_CPP_NAMESPACE 26 27 typedef struct { 28 // Base 29 int RV32I : 1; // Base Integer Instruction Set, 32-bit 30 int RV64I : 1; // Base Integer Instruction Set, 64-bit 31 32 // Extension 33 int M : 1; // Standard Extension for Integer Multiplication/Division 34 int A : 1; // Standard Extension for Atomic Instructions 35 int F : 1; // Standard Extension for Single-Precision Floating-Point 36 int D : 1; // Standard Extension for Double-Precision Floating-Point 37 int Q : 1; // Standard Extension for Quad-Precision Floating-Point 38 int C : 1; // Standard Extension for Compressed Instructions 39 int V : 1; // Standard Extension for Vector Instructions 40 int Zicsr : 1; // Control and Status Register (CSR) 41 int Zifencei : 1; // Instruction-Fetch Fence 42 } RiscvFeatures; 43 44 typedef struct { 45 RiscvFeatures features; 46 char uarch[64]; // 0 terminated string 47 char vendor[64]; // 0 terminated string 48 } RiscvInfo; 49 50 typedef enum { 51 RISCV_RV32I, 52 RISCV_RV64I, 53 RISCV_M, 54 RISCV_A, 55 RISCV_F, 56 RISCV_D, 57 RISCV_Q, 58 RISCV_C, 59 RISCV_V, 60 RISCV_Zicsr, 61 RISCV_Zifencei, 62 RISCV_LAST_, 63 } RiscvFeaturesEnum; 64 65 RiscvInfo GetRiscvInfo(void); 66 int GetRiscvFeaturesEnumValue(const RiscvFeatures* features, 67 RiscvFeaturesEnum value); 68 const char* GetRiscvFeaturesEnumName(RiscvFeaturesEnum); 69 70 CPU_FEATURES_END_CPP_NAMESPACE 71 72 #endif // CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_ 73