1
2 #include <stdio.h>
3 #include <stdlib.h>
4 #include "inteltool.h"
5
6 static const io_register_t ich6_bios_cntl_registers[] = {
7 { 0x0, 1, "BIOSWE - write enable" },
8 { 0x1, 1, "BLE - lock enable" },
9 { 0x2, 6, "reserved" },
10 };
11
12 static const io_register_t ich7_bios_cntl_registers[] = {
13 { 0x0, 1, "BIOSWE - write enable" },
14 { 0x1, 1, "BLE - lock enable" },
15 { 0x2, 2, "SPI Read configuration" },
16 { 0x4, 1, "TopSwapStatus" },
17 { 0x5, 3, "reserved" },
18 };
19
20 static const io_register_t pch_bios_cntl_registers[] = {
21 { 0x0, 1, "BIOSWE - write enable" },
22 { 0x1, 1, "BLE - lock enable" },
23 { 0x2, 2, "SPI Read configuration" },
24 { 0x4, 1, "TopSwapStatus" },
25 { 0x5, 1, "SMM BIOS Write Protect Disable" },
26 { 0x6, 2, "reserved" },
27 };
28
29 static const io_register_t adl_pch_bios_cntl_registers[] = {
30 { 0x0, 1, "WPD - Write Protect Disable" },
31 { 0x1, 1, "LE - Lock Enable" },
32 { 0x2, 1, "ESPI - eSPI Enable Pin Strap" },
33 { 0x3, 1, "Reserved" },
34 { 0x4, 1, "TS - Top Swap" },
35 { 0x5, 1, "EISS - Enable InSMM.STS" },
36 { 0x6, 1, "BBS - Boot BIOS Strap" },
37 { 0x7, 1, "BILD - BIOS Interface Lock-Down" },
38 { 0x8, 1, "BWPDS - BIOS Write Protect Disable Status" },
39 { 0x9, 1, "Reserved" },
40 { 0x10, 1, "BWRS - BIOS Write Status" },
41 { 0x11, 1, "BWRE - BIOS Write Reporting (Async-SMI)" },
42 { 0x12, 19, "Reserved" },
43 };
44
45 #define ICH9_SPIBAR 0x3800
46 #define ICH78_SPIBAR 0x3020
47
48 static const io_register_t spi_bar_registers[] = {
49 { 0x00, 4, "BFPR - BIOS Flash primary region" },
50 { 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
51 { 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
52 { 0x08, 4, "FADDR - Flash Address" },
53 { 0x0c, 4, "Reserved" },
54 { 0x10, 4, "FDATA0" },
55 /* 0x10 .. 0x4f are filled with data */
56 { 0x50, 4, "FRACC - Flash Region Access Permissions" },
57 { 0x54, 4, "Flash Region 0" },
58 { 0x58, 4, "Flash Region 1" },
59 { 0x5c, 4, "Flash Region 2" },
60 { 0x60, 4, "Flash Region 3" },
61 { 0x64, 4, "Flash Region 4" },
62 { 0x74, 4, "FPR0 Flash Protected Range 0" },
63 { 0x78, 4, "FPR0 Flash Protected Range 1" },
64 { 0x7c, 4, "FPR0 Flash Protected Range 2" },
65 { 0x80, 4, "FPR0 Flash Protected Range 3" },
66 { 0x84, 4, "FPR0 Flash Protected Range 4" },
67 { 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
68 { 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
69 { 0x94, 2, "PREOP - Prefix opcode Configuration" },
70 { 0x96, 2, "OPTYPE - Opcode Type Configuration" },
71 { 0x98, 8, "OPMENU - Opcode Menu Configuration" },
72 { 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
73 { 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
74 { 0xb8, 4, "Reserved" },
75 { 0xc0, 4, "AFC - Additional Flash Control" },
76 { 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
77 { 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
78 { 0xd0, 4, "FPB - Flash Partition Boundary" },
79 };
80
81 static const io_register_t ich7_spi_bar_registers[] = {
82 { 0x00, 2, "SPIS - SPI Status" },
83 { 0x02, 2, "SPIC - SPI Control" },
84 { 0x04, 4, "SPIA - SPI Address" },
85 /*
86 *0x08 .. 0x47 are filled with data
87 *0x48 .. 0x4f is not mentioned by datasheet
88 */
89 { 0x50, 4, "BBAR - BIOS Base Address Configuration" },
90 { 0x54, 2, "PREOP Prefix Opcode Configuration" },
91 { 0x56, 2, "OPTYPE Opcode Type Configuration" },
92 { 0x58, 8, "OPMENU Opcode Menu Configuration" },
93 { 0x60, 4, "PBR0 Protected BIOS Range 0" },
94 { 0x64, 4, "PBR1 Protected BIOS Range 1" },
95 { 0x68, 4, "PBR2 Protected BIOS Range 2" },
96 };
97
98
print_bioscntl(struct pci_dev * sb)99 static int print_bioscntl(struct pci_dev *sb)
100 {
101 int i, size = 0;
102 unsigned char bios_cntl = 0xff;
103 const io_register_t *bios_cntl_register = NULL;
104
105 printf("\n============= SPI / BIOS CNTL =============\n\n");
106
107 switch (sb->device_id) {
108 case PCI_DEVICE_ID_INTEL_ICH6:
109 bios_cntl = pci_read_byte(sb, 0xdc);
110 bios_cntl_register = ich6_bios_cntl_registers;
111 size = ARRAY_SIZE(ich6_bios_cntl_registers);
112 break;
113 case PCI_DEVICE_ID_INTEL_ICH7:
114 case PCI_DEVICE_ID_INTEL_ICH7M:
115 case PCI_DEVICE_ID_INTEL_ICH7DH:
116 case PCI_DEVICE_ID_INTEL_ICH7MDH:
117 case PCI_DEVICE_ID_INTEL_ICH8:
118 case PCI_DEVICE_ID_INTEL_ICH8M:
119 case PCI_DEVICE_ID_INTEL_ICH8ME:
120 case PCI_DEVICE_ID_INTEL_ICH9DH:
121 case PCI_DEVICE_ID_INTEL_ICH9DO:
122 case PCI_DEVICE_ID_INTEL_ICH9R:
123 case PCI_DEVICE_ID_INTEL_ICH9:
124 case PCI_DEVICE_ID_INTEL_ICH9M:
125 case PCI_DEVICE_ID_INTEL_ICH9ME:
126 case PCI_DEVICE_ID_INTEL_ICH10:
127 case PCI_DEVICE_ID_INTEL_ICH10D:
128 case PCI_DEVICE_ID_INTEL_ICH10DO:
129 case PCI_DEVICE_ID_INTEL_ICH10R:
130 case PCI_DEVICE_ID_INTEL_NM10:
131 bios_cntl = pci_read_byte(sb, 0xdc);
132 bios_cntl_register = ich7_bios_cntl_registers;
133 size = ARRAY_SIZE(ich7_bios_cntl_registers);
134 break;
135 case PCI_DEVICE_ID_INTEL_3400:
136 case PCI_DEVICE_ID_INTEL_3420:
137 case PCI_DEVICE_ID_INTEL_3450:
138 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
139 case PCI_DEVICE_ID_INTEL_B55_A:
140 case PCI_DEVICE_ID_INTEL_B55_B:
141 case PCI_DEVICE_ID_INTEL_H55:
142 case PCI_DEVICE_ID_INTEL_H57:
143 case PCI_DEVICE_ID_INTEL_P55:
144 case PCI_DEVICE_ID_INTEL_Q57:
145 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
146 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
147 case PCI_DEVICE_ID_INTEL_HM55:
148 case PCI_DEVICE_ID_INTEL_HM57:
149 case PCI_DEVICE_ID_INTEL_PM55:
150 case PCI_DEVICE_ID_INTEL_QM57:
151 case PCI_DEVICE_ID_INTEL_QS57:
152 case PCI_DEVICE_ID_INTEL_Z68:
153 case PCI_DEVICE_ID_INTEL_P67:
154 case PCI_DEVICE_ID_INTEL_UM67:
155 case PCI_DEVICE_ID_INTEL_HM65:
156 case PCI_DEVICE_ID_INTEL_H67:
157 case PCI_DEVICE_ID_INTEL_HM67:
158 case PCI_DEVICE_ID_INTEL_Q65:
159 case PCI_DEVICE_ID_INTEL_QS67:
160 case PCI_DEVICE_ID_INTEL_Q67:
161 case PCI_DEVICE_ID_INTEL_QM67:
162 case PCI_DEVICE_ID_INTEL_B65:
163 case PCI_DEVICE_ID_INTEL_C202:
164 case PCI_DEVICE_ID_INTEL_C204:
165 case PCI_DEVICE_ID_INTEL_C206:
166 case PCI_DEVICE_ID_INTEL_H61:
167 case PCI_DEVICE_ID_INTEL_Z77:
168 case PCI_DEVICE_ID_INTEL_Z75:
169 case PCI_DEVICE_ID_INTEL_Q77:
170 case PCI_DEVICE_ID_INTEL_Q75:
171 case PCI_DEVICE_ID_INTEL_B75:
172 case PCI_DEVICE_ID_INTEL_H77:
173 case PCI_DEVICE_ID_INTEL_C216:
174 case PCI_DEVICE_ID_INTEL_QM77:
175 case PCI_DEVICE_ID_INTEL_QS77:
176 case PCI_DEVICE_ID_INTEL_HM77:
177 case PCI_DEVICE_ID_INTEL_UM77:
178 case PCI_DEVICE_ID_INTEL_HM76:
179 case PCI_DEVICE_ID_INTEL_HM75:
180 case PCI_DEVICE_ID_INTEL_HM70:
181 case PCI_DEVICE_ID_INTEL_NM70:
182 case PCI_DEVICE_ID_INTEL_C8_MOBILE:
183 case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
184 case PCI_DEVICE_ID_INTEL_Z87:
185 case PCI_DEVICE_ID_INTEL_Z85:
186 case PCI_DEVICE_ID_INTEL_HM86:
187 case PCI_DEVICE_ID_INTEL_H87:
188 case PCI_DEVICE_ID_INTEL_HM87:
189 case PCI_DEVICE_ID_INTEL_Q85:
190 case PCI_DEVICE_ID_INTEL_Q87:
191 case PCI_DEVICE_ID_INTEL_QM87:
192 case PCI_DEVICE_ID_INTEL_B85:
193 case PCI_DEVICE_ID_INTEL_C222:
194 case PCI_DEVICE_ID_INTEL_C224:
195 case PCI_DEVICE_ID_INTEL_C226:
196 case PCI_DEVICE_ID_INTEL_H81:
197 case PCI_DEVICE_ID_INTEL_C9_MOBILE:
198 case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
199 case PCI_DEVICE_ID_INTEL_HM97:
200 case PCI_DEVICE_ID_INTEL_Z97:
201 case PCI_DEVICE_ID_INTEL_H97:
202 case PCI_DEVICE_ID_INTEL_H110:
203 case PCI_DEVICE_ID_INTEL_H170:
204 case PCI_DEVICE_ID_INTEL_Z170:
205 case PCI_DEVICE_ID_INTEL_Q170:
206 case PCI_DEVICE_ID_INTEL_Q150:
207 case PCI_DEVICE_ID_INTEL_B150:
208 case PCI_DEVICE_ID_INTEL_C236:
209 case PCI_DEVICE_ID_INTEL_C232:
210 case PCI_DEVICE_ID_INTEL_QM170:
211 case PCI_DEVICE_ID_INTEL_HM170:
212 case PCI_DEVICE_ID_INTEL_CM236:
213 case PCI_DEVICE_ID_INTEL_HM175:
214 case PCI_DEVICE_ID_INTEL_QM175:
215 case PCI_DEVICE_ID_INTEL_CM238:
216 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
217 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
218 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
219 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
220 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
221 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
222 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
223 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
224 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
225 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
226 bios_cntl = pci_read_byte(sb, 0xdc);
227 bios_cntl_register = pch_bios_cntl_registers;
228 size = ARRAY_SIZE(pch_bios_cntl_registers);
229 break;
230 case PCI_DEVICE_ID_INTEL_ADL_N:
231 bios_cntl = pci_read_byte(sb, 0xdc);
232 bios_cntl_register = adl_pch_bios_cntl_registers;
233 size = ARRAY_SIZE(adl_pch_bios_cntl_registers);
234 break;
235 default:
236 printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
237 return 1;
238 }
239
240 printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl);
241
242 if (bios_cntl_register) {
243 for (i = 0; i < size; i++) {
244 unsigned int val = bios_cntl >> bios_cntl_register[i].addr;
245 val &= ((1 << bios_cntl_register[i].size) -1);
246 printf("0x%04x = %s\n", val, bios_cntl_register[i].name);
247 }
248 }
249
250 return 0;
251 }
252
print_spibar(struct pci_dev * sb)253 static int print_spibar(struct pci_dev *sb) {
254 int i, size = 0, rcba_size = 0x4000;
255 volatile uint8_t *rcba;
256 uint32_t rcba_phys;
257 const io_register_t *spi_register = NULL;
258 uint32_t spibaroffset;
259
260 printf("\n============= SPI Bar ==============\n\n");
261
262 switch (sb->device_id) {
263 case PCI_DEVICE_ID_INTEL_ICH6:
264 printf("This southbridge does not have a SPI controller.\n");
265 return 1;
266 case PCI_DEVICE_ID_INTEL_ICH7:
267 case PCI_DEVICE_ID_INTEL_ICH7M:
268 case PCI_DEVICE_ID_INTEL_ICH7DH:
269 case PCI_DEVICE_ID_INTEL_ICH7MDH:
270 spibaroffset = ICH78_SPIBAR;
271 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
272 size = ARRAY_SIZE(ich7_spi_bar_registers);
273 spi_register = ich7_spi_bar_registers;
274 break;
275 case PCI_DEVICE_ID_INTEL_ICH8:
276 spibaroffset = ICH78_SPIBAR;
277 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
278 size = ARRAY_SIZE(spi_bar_registers);
279 spi_register = spi_bar_registers;
280 break;
281 case PCI_DEVICE_ID_INTEL_ICH8M:
282 case PCI_DEVICE_ID_INTEL_ICH8ME:
283 case PCI_DEVICE_ID_INTEL_ICH9DH:
284 case PCI_DEVICE_ID_INTEL_ICH9DO:
285 case PCI_DEVICE_ID_INTEL_ICH9R:
286 case PCI_DEVICE_ID_INTEL_ICH9:
287 case PCI_DEVICE_ID_INTEL_ICH9M:
288 case PCI_DEVICE_ID_INTEL_ICH9ME:
289 case PCI_DEVICE_ID_INTEL_ICH10:
290 case PCI_DEVICE_ID_INTEL_ICH10D:
291 case PCI_DEVICE_ID_INTEL_ICH10DO:
292 case PCI_DEVICE_ID_INTEL_ICH10R:
293 case PCI_DEVICE_ID_INTEL_NM10:
294 case PCI_DEVICE_ID_INTEL_I63XX:
295 case PCI_DEVICE_ID_INTEL_3400:
296 case PCI_DEVICE_ID_INTEL_3420:
297 case PCI_DEVICE_ID_INTEL_3450:
298 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
299 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
300 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
301 case PCI_DEVICE_ID_INTEL_B55_A:
302 case PCI_DEVICE_ID_INTEL_B55_B:
303 case PCI_DEVICE_ID_INTEL_H55:
304 case PCI_DEVICE_ID_INTEL_H57:
305 case PCI_DEVICE_ID_INTEL_HM55:
306 case PCI_DEVICE_ID_INTEL_HM57:
307 case PCI_DEVICE_ID_INTEL_P55:
308 case PCI_DEVICE_ID_INTEL_PM55:
309 case PCI_DEVICE_ID_INTEL_Q57:
310 case PCI_DEVICE_ID_INTEL_QM57:
311 case PCI_DEVICE_ID_INTEL_QS57:
312 case PCI_DEVICE_ID_INTEL_Z68:
313 case PCI_DEVICE_ID_INTEL_P67:
314 case PCI_DEVICE_ID_INTEL_UM67:
315 case PCI_DEVICE_ID_INTEL_HM65:
316 case PCI_DEVICE_ID_INTEL_H67:
317 case PCI_DEVICE_ID_INTEL_HM67:
318 case PCI_DEVICE_ID_INTEL_Q65:
319 case PCI_DEVICE_ID_INTEL_QS67:
320 case PCI_DEVICE_ID_INTEL_Q67:
321 case PCI_DEVICE_ID_INTEL_QM67:
322 case PCI_DEVICE_ID_INTEL_B65:
323 case PCI_DEVICE_ID_INTEL_C202:
324 case PCI_DEVICE_ID_INTEL_C204:
325 case PCI_DEVICE_ID_INTEL_C206:
326 case PCI_DEVICE_ID_INTEL_H61:
327 case PCI_DEVICE_ID_INTEL_Z77:
328 case PCI_DEVICE_ID_INTEL_Z75:
329 case PCI_DEVICE_ID_INTEL_Q77:
330 case PCI_DEVICE_ID_INTEL_Q75:
331 case PCI_DEVICE_ID_INTEL_B75:
332 case PCI_DEVICE_ID_INTEL_H77:
333 case PCI_DEVICE_ID_INTEL_C216:
334 case PCI_DEVICE_ID_INTEL_QM77:
335 case PCI_DEVICE_ID_INTEL_QS77:
336 case PCI_DEVICE_ID_INTEL_HM77:
337 case PCI_DEVICE_ID_INTEL_UM77:
338 case PCI_DEVICE_ID_INTEL_HM76:
339 case PCI_DEVICE_ID_INTEL_HM75:
340 case PCI_DEVICE_ID_INTEL_HM70:
341 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
342 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
343 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
344 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
345 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
346 case PCI_DEVICE_ID_INTEL_C8_MOBILE:
347 case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
348 case PCI_DEVICE_ID_INTEL_Z87:
349 case PCI_DEVICE_ID_INTEL_Z85:
350 case PCI_DEVICE_ID_INTEL_HM86:
351 case PCI_DEVICE_ID_INTEL_H87:
352 case PCI_DEVICE_ID_INTEL_HM87:
353 case PCI_DEVICE_ID_INTEL_Q85:
354 case PCI_DEVICE_ID_INTEL_Q87:
355 case PCI_DEVICE_ID_INTEL_QM87:
356 case PCI_DEVICE_ID_INTEL_B85:
357 case PCI_DEVICE_ID_INTEL_C222:
358 case PCI_DEVICE_ID_INTEL_C224:
359 case PCI_DEVICE_ID_INTEL_C226:
360 case PCI_DEVICE_ID_INTEL_H81:
361 case PCI_DEVICE_ID_INTEL_C9_MOBILE:
362 case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
363 case PCI_DEVICE_ID_INTEL_HM97:
364 case PCI_DEVICE_ID_INTEL_Z97:
365 case PCI_DEVICE_ID_INTEL_H97:
366 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
367 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
368 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
369 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
370 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
371 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
372 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
373 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
374 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
375 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
376 spibaroffset = ICH9_SPIBAR;
377 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
378 size = ARRAY_SIZE(spi_bar_registers);
379 spi_register = spi_bar_registers;
380 break;
381 case PCI_DEVICE_ID_INTEL_ICH:
382 case PCI_DEVICE_ID_INTEL_ICH0:
383 case PCI_DEVICE_ID_INTEL_ICH2:
384 case PCI_DEVICE_ID_INTEL_ICH4:
385 case PCI_DEVICE_ID_INTEL_ICH4M:
386 case PCI_DEVICE_ID_INTEL_ICH5:
387 case PCI_DEVICE_ID_INTEL_ADL_N:
388 printf("This southbridge does not have RCBA.\n");
389 return 1;
390 default:
391 printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
392 return 1;
393 }
394
395 rcba = map_physical(rcba_phys, rcba_size);
396 if (rcba == NULL) {
397 perror("Error mapping RCBA");
398 exit(1);
399 }
400
401 for (i = 0; i < size; i++) {
402 switch(spi_register[i].size) {
403 case 1:
404 printf("0x%08x = %s\n", read8(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
405 break;
406 case 2:
407 printf("0x%08x = %s\n", read16(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
408 break;
409 case 4:
410 printf("0x%08x = %s\n", read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
411 break;
412 case 8:
413 printf("0x%08x%08x = %s\n", read32(rcba + spibaroffset + spi_register[i].addr + 4),
414 read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
415 break;
416 }
417 }
418
419 unmap_physical((void *)rcba, rcba_size);
420 return 0;
421 }
422
print_spi(struct pci_dev * sb)423 int print_spi(struct pci_dev *sb) {
424 return (print_bioscntl(sb) || print_spibar(sb));
425 }
426