1package main 2 3import "fmt" 4import "strings" 5 6type sandybridgemc struct { 7} 8 9func MakeSPDMap(ctx Context) string { 10 var values []string 11 for _, addr := range GuessSPDMap(ctx) { 12 values = append(values, fmt.Sprintf("0x%02x", addr)) 13 } 14 return "{"+strings.Join(values, ", ")+"}" 15} 16 17func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { 18 inteltool := ctx.InfoSource.GetInteltool() 19 20 /* FIXME:XX Move this somewhere else. */ 21 MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") 22 MainboardEnable += (` /* FIXME: fix these values. */ 23 install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, 24 GMA_INT15_PANEL_FIT_DEFAULT, 25 GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); 26`) 27 28 DevTree = DevTreeNode{ 29 Chip: "northbridge/intel/sandybridge", 30 MissingParent: "northbridge", 31 Comment: "FIXME: GPU registers may not always apply.", 32 Registers: map[string]string{ 33 "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), 34 "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), 35 "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), 36 "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3), 37 "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), 38 "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), 39 "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), 40 "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), 41 "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), 42 "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), 43 "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), 44 "gfx": fmt.Sprintf("GMA_STATIC_DISPLAYS(%d)", (inteltool.IGD[0xc6200] >> 12) & 1), 45 "spd_addresses": MakeSPDMap(ctx)+"\" # FIXME: Put proper SPD map here", 46 }, 47 Children: []DevTreeNode{ 48 { 49 Chip: "domain", 50 Dev: 0, 51 PCIController: true, 52 ChildPCIBus: 0, 53 PCISlots: []PCISlot{ 54 PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"}, 55 PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"}, 56 PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"}, 57 }, 58 }, 59 }, 60 } 61 62 PutPCIDev(addr, "Host bridge") 63 64 /* FIXME:XX some configs are unsupported. */ 65 KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true 66 KconfigBool["USE_NATIVE_RAMINIT"] = true 67 KconfigBool["INTEL_INT15"] = true 68 KconfigBool["HAVE_ACPI_TABLES"] = true 69 KconfigBool["HAVE_ACPI_RESUME"] = true 70 71 DSDTIncludes = append(DSDTIncludes, DSDTInclude{ 72 File: "cpu/intel/common/acpi/cpu.asl", 73 }) 74 75 DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ 76 File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", 77 }, DSDTInclude{ 78 File: "drivers/intel/gma/acpi/default_brightness_levels.asl", 79 }) 80} 81 82func init() { 83 RegisterPCI(0x8086, 0x0100, sandybridgemc{}) 84 RegisterPCI(0x8086, 0x0104, sandybridgemc{}) 85 RegisterPCI(0x8086, 0x0150, sandybridgemc{}) 86 RegisterPCI(0x8086, 0x0154, sandybridgemc{}) 87 RegisterPCI(0x8086, 0x0158, sandybridgemc{}) 88 for _, id := range []uint16{ 89 0x0102, 0x0106, 0x010a, 90 0x0112, 0x0116, 0x0122, 0x0126, 91 0x0152, 0x0156, 0x0162, 0x0166, 92 } { 93 RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}}) 94 } 95 96 /* PCIe bridge */ 97 for _, id := range []uint16{ 98 0x0101, 0x0105, 0x0109, 0x010d, 99 0x0151, 0x0155, 0x0159, 0x015d, 100 } { 101 RegisterPCI(0x8086, id, GenericPCI{}) 102 } 103} 104