1## SPDX-License-Identifier: GPL-2.0-only 2 3config MISSING_BOARD_RESET 4 bool 5 help 6 Selected by boards that don't provide a do_board_reset() 7 implementation. This activates a stub that logs the missing 8 board reset and halts execution. 9 10config ROMSTAGE_ADA 11 bool 12 help 13 Selected by features that use Ada code in romstage. 14 15config RAMSTAGE_ADA 16 bool 17 help 18 Selected by features that use Ada code in ramstage. 19 20config RAMSTAGE_LIBHWBASE 21 bool 22 select RAMSTAGE_ADA 23 help 24 Selected by features that require `libhwbase` in ramstage. 25 26config ROMSTAGE_LIBHWBASE 27 bool 28 select ROMSTAGE_ADA 29 help 30 Selected by features that require `libhwbase` in romstage. 31 32config FLATTENED_DEVICE_TREE 33 bool 34 help 35 Selected by features that require to parse and manipulate a flattened 36 devicetree in ramstage. 37 38config HAVE_SPD_IN_CBFS 39 bool 40 help 41 If enabled, add support for adding spd.hex files in cbfs as spd.bin 42 and locating it runtime to load SPD. 43 44config DIMM_MAX 45 int 46 default 4 47 help 48 Total number of memory DIMM slots available on motherboard. 49 It is multiplication of number of channel to number of DIMMs per 50 channel 51 52config DIMM_SPD_SIZE 53 int 54 default 256 55 help 56 Total SPD size that will be used for DIMM. 57 Ex: DDR3 256, DDR4 512. 58 59config SPD_READ_BY_WORD 60 bool 61 62config SPD_CACHE_IN_FMAP 63 bool 64 default n 65 help 66 Enables capability to cache DIMM SPDs in a dedicated FMAP region 67 to speed loading of SPD data. Currently requires board-level 68 romstage implementation to read/write/utilize cached SPD data. 69 When the default FMAP is used, will create a region named RW_SPD_CACHE 70 to store the cached SPD data. 71 72config SPD_CACHE_FMAP_NAME 73 string 74 depends on SPD_CACHE_IN_FMAP 75 default "RW_SPD_CACHE" 76 help 77 Name of the FMAP region created in the default FMAP to cache SPD data. 78 79if RAMSTAGE_LIBHWBASE && !ROMSTAGE_LIBHWBASE 80 81config HWBASE_DYNAMIC_MMIO 82 def_bool y 83 84endif 85 86if ROMSTAGE_LIBHWBASE 87 88config HWBASE_STATIC_MMIO 89 def_bool y 90 91endif 92 93if RAMSTAGE_LIBHWBASE || ROMSTAGE_LIBHWBASE 94 95config HWBASE_DEFAULT_MMCONF 96 hex 97 default ECAM_MMCONF_BASE_ADDRESS 98 99config HWBASE_DIRECT_PCIDEV 100 def_bool y 101 102endif 103 104config NO_FMAP_CACHE 105 bool 106 help 107 If your platform really doesn't want to use an FMAP cache (e.g. due to 108 space constraints), you can select this to disable warnings and save 109 a bit more code. 110 111config ESPI_DEBUG 112 bool 113 help 114 This option enables eSPI library helper functions for displaying debug 115 information. 116 117config NO_CBFS_MCACHE 118 bool 119 help 120 Disables the CBFS metadata cache. This means that your platform does 121 not need to provide a CBFS_MCACHE section in memlayout and can save 122 the associated CAR/SRAM size. In that case every single CBFS file 123 lookup must re-read the same CBFS directory entries from flash to find 124 the respective file. 125 126config CBFS_CACHE_ALIGN 127 int 128 default 8 129 help 130 Sets the alignment of the buffers returned by the cbfs_cache. 131 132config CBFS_PRELOAD 133 bool 134 depends on COOP_MULTITASKING 135 help 136 When enabled it will be possible to preload CBFS files into the 137 cbfs_cache. This helps reduce boot time by loading the files 138 in the background before they are actually required. This feature 139 depends on the read-only boot_device having a DMA controller to 140 perform the background transfer. 141 142config DECOMPRESS_OFAST 143 bool 144 depends on COMPILER_GCC 145 default y 146 help 147 Compile the decompressing function in -Ofast instead of standard -Os 148 149config PROBE_RAM 150 def_bool y if VENDOR_EMULATION 151 help 152 When enabled it will be possible to detect usable RAM using probe_ram 153 function. 154 155config HAVE_CUSTOM_BMP_LOGO 156 def_bool n 157 depends on BMP_LOGO 158