1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef PC80_MC146818RTC_H
4 #define PC80_MC146818RTC_H
5
6 #include <arch/io.h>
7 #include <types.h>
8
9 #define RTC_BASE_PORT_BANK0 (CONFIG_PC_CMOS_BASE_PORT_BANK0)
10 #define RTC_BASE_PORT_BANK1 (CONFIG_PC_CMOS_BASE_PORT_BANK1)
11
12 #define RTC_PORT_BANK0(x) (RTC_BASE_PORT_BANK0 + (x))
13
14 /* control registers - Moto names
15 */
16 #define RTC_REG_A 10
17 #define RTC_REG_B 11
18 #define RTC_REG_C 12
19 #define RTC_REG_D 13
20
21 /**********************************************************************
22 * register details
23 **********************************************************************/
24 #define RTC_FREQ_SELECT RTC_REG_A
25
26 /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
27 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
28 * totaling to a max high interval of 2.228 ms.
29 */
30 # define RTC_UIP 0x80
31 # define RTC_DIV_CTL 0x70
32 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
33 # define RTC_REF_CLCK_4MHZ 0x00
34 # define RTC_REF_CLCK_1MHZ 0x10
35 # define RTC_REF_CLCK_32KHZ 0x20
36 /* 2 values for divider stage reset, others for "testing purposes only" */
37 # define RTC_DIV_RESET1 0x60
38 # define RTC_DIV_RESET2 0x70
39 /* Periodic intr. / Square wave rate select. 0 = none,
40 * 1 = 32.8kHz,... 15 = 2Hz
41 */
42 # define RTC_RATE_SELECT 0x0F
43 # define RTC_RATE_NONE 0x00
44 # define RTC_RATE_32786HZ 0x01
45 # define RTC_RATE_16384HZ 0x02
46 # define RTC_RATE_8192HZ 0x03
47 # define RTC_RATE_4096HZ 0x04
48 # define RTC_RATE_2048HZ 0x05
49 # define RTC_RATE_1024HZ 0x06
50 # define RTC_RATE_512HZ 0x07
51 # define RTC_RATE_256HZ 0x08
52 # define RTC_RATE_128HZ 0x09
53 # define RTC_RATE_64HZ 0x0a
54 # define RTC_RATE_32HZ 0x0b
55 # define RTC_RATE_16HZ 0x0c
56 # define RTC_RATE_8HZ 0x0d
57 # define RTC_RATE_4HZ 0x0e
58 # define RTC_RATE_2HZ 0x0f
59
60 /**********************************************************************/
61 #define RTC_CONTROL RTC_REG_B
62 # define RTC_SET 0x80 /* disable updates for clock setting */
63 # define RTC_PIE 0x40 /* periodic interrupt enable */
64 # define RTC_AIE 0x20 /* alarm interrupt enable */
65 # define RTC_UIE 0x10 /* update-finished interrupt enable */
66 # define RTC_SQWE 0x08 /* enable square-wave output */
67 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
68 # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
69 # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
70
71 /**********************************************************************/
72 #define RTC_INTR_FLAGS RTC_REG_C
73 /* caution - cleared by read */
74 # define RTC_IRQF 0x80 /* any of the following 3 is active */
75 # define RTC_PF 0x40
76 # define RTC_AF 0x20
77 # define RTC_UF 0x10
78
79 /**********************************************************************/
80 #define RTC_VALID RTC_REG_D
81 # define RTC_VRT 0x80 /* valid RAM and time */
82 /**********************************************************************/
83
84 /* Date and Time in RTC CMOS */
85 #define RTC_CLK_SECOND 0
86 #define RTC_CLK_SECOND_ALARM 1
87 #define RTC_CLK_MINUTE 2
88 #define RTC_CLK_MINUTE_ALARM 3
89 #define RTC_CLK_HOUR 4
90 #define RTC_CLK_HOUR_ALARM 5
91 #define RTC_CLK_DAYOFWEEK 6
92 #define RTC_CLK_DAYOFMONTH 7
93 #define RTC_CLK_MONTH 8
94 #define RTC_CLK_YEAR 9
95 #define RTC_CLK_ALTCENTURY 0x32
96
97 #define RTC_DATE_ALARM RTC_REG_D
98 #define RTC_MONTH_ALARM 0
99
100 /* On PCs, the checksum is built only over bytes 16..45 */
101 #define PC_CKS_RANGE_START 16
102 #define PC_CKS_RANGE_END 45
103 #define PC_CKS_LOC 46
104
105 /* Tracking of fallback/normal boot. */
106 #define RTC_BOOT_BYTE 48
107 #define RTC_BOOT_NORMAL 0x1
108
cmos_read(unsigned char addr)109 static inline unsigned char cmos_read(unsigned char addr)
110 {
111 int port = RTC_BASE_PORT_BANK0;
112 if (addr >= 128) {
113 port = RTC_BASE_PORT_BANK1;
114 addr -= 128;
115 }
116 outb(addr, port + 0);
117 return inb(port + 1);
118 }
119
cmos_write_inner(unsigned char val,unsigned char addr)120 static inline void cmos_write_inner(unsigned char val, unsigned char addr)
121 {
122 int port = RTC_BASE_PORT_BANK0;
123 if (addr >= 128) {
124 port = RTC_BASE_PORT_BANK1;
125 addr -= 128;
126 }
127 outb(addr, port + 0);
128 outb(val, port + 1);
129 }
130
cmos_disable_rtc(void)131 static inline u8 cmos_disable_rtc(void)
132 {
133 u8 control_state = cmos_read(RTC_CONTROL);
134 if (!(control_state & RTC_SET))
135 cmos_write_inner(control_state | RTC_SET, RTC_CONTROL);
136 return control_state;
137 }
138
cmos_restore_rtc(u8 control_state)139 static inline void cmos_restore_rtc(u8 control_state)
140 {
141 if (!(control_state & RTC_SET))
142 cmos_write_inner(control_state, RTC_CONTROL);
143 }
144
cmos_write(unsigned char val,unsigned char addr)145 static inline void cmos_write(unsigned char val, unsigned char addr)
146 {
147 u8 control_state;
148
149 /*
150 * There are various places where RTC bits might be hiding,
151 * eg. the Century / AltCentury byte. So to be safe, disable
152 * RTC before changing any value.
153 */
154 if (addr != RTC_CONTROL)
155 control_state = cmos_disable_rtc();
156 cmos_write_inner(val, addr);
157 if (addr != RTC_CONTROL)
158 cmos_restore_rtc(control_state);
159 }
160
cmos_read32(u8 offset)161 static inline u32 cmos_read32(u8 offset)
162 {
163 u32 value = 0;
164 u8 i;
165 for (i = 0; i < sizeof(value); ++i)
166 value |= cmos_read(offset + i) << (i << 3);
167 return value;
168 }
169
cmos_write32(u32 value,u8 offset)170 static inline void cmos_write32(u32 value, u8 offset)
171 {
172 u8 i;
173 for (i = 0; i < sizeof(value); ++i)
174 cmos_write((value >> (i << 3)) & 0xff, offset + i);
175 }
176
177 void cmos_init(bool invalid);
178 void cmos_check_update_date(void);
179 int cmos_error(void);
180 int cmos_lb_cks_valid(void);
181
182 int cmos_checksum_valid(int range_start, int range_end, int cks_loc);
183 void cmos_set_checksum(int range_start, int range_end, int cks_loc);
184
185 #endif /* PC80_MC146818RTC_H */
186