1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ops.h>
7 #include <device/pcix.h>
8 #include <stdint.h>
9
pcix_tune_dev(struct device * dev)10 static void pcix_tune_dev(struct device *dev)
11 {
12 u32 status;
13 u16 orig_cmd, cmd;
14 unsigned int cap, max_read, max_tran;
15
16 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
17 return;
18
19 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
20 if (!cap)
21 return;
22
23 printk(BIOS_DEBUG, "%s PCI-X tuning\n", dev_path(dev));
24
25 status = pci_read_config32(dev, cap + PCI_X_STATUS);
26 orig_cmd = cmd = pci_read_config16(dev, cap + PCI_X_CMD);
27
28 max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
29 max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
30 if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
31 cmd &= ~PCI_X_CMD_MAX_READ;
32 cmd |= max_read << 2;
33 }
34 if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
35 cmd &= ~PCI_X_CMD_MAX_SPLIT;
36 cmd |= max_tran << 4;
37 }
38
39 /* Don't attempt to handle PCI-X errors. */
40 cmd &= ~PCI_X_CMD_DPERR_E;
41
42 /* Enable relaxed ordering. */
43 cmd |= PCI_X_CMD_ERO;
44
45 if (orig_cmd != cmd)
46 pci_write_config16(dev, cap + PCI_X_CMD, cmd);
47 }
48
pcix_tune_bus(struct bus * bus)49 static void pcix_tune_bus(struct bus *bus)
50 {
51 struct device *child;
52
53 for (child = bus->children; child; child = child->sibling)
54 pcix_tune_dev(child);
55 }
56
pcix_speed(u16 sstatus)57 const char *pcix_speed(u16 sstatus)
58 {
59 static const char conventional[] = "Conventional PCI";
60 static const char pcix_66mhz[] = "66MHz PCI-X";
61 static const char pcix_100mhz[] = "100MHz PCI-X";
62 static const char pcix_133mhz[] = "133MHz PCI-X";
63 static const char pcix_266mhz[] = "266MHz PCI-X";
64 static const char pcix_533mhz[] = "533MHZ PCI-X";
65 static const char unknown[] = "Unknown";
66 const char *result;
67
68 result = unknown;
69
70 switch (PCI_X_SSTATUS_MFREQ(sstatus)) {
71 case PCI_X_SSTATUS_CONVENTIONAL_PCI:
72 result = conventional;
73 break;
74 case PCI_X_SSTATUS_MODE1_66MHZ:
75 result = pcix_66mhz;
76 break;
77 case PCI_X_SSTATUS_MODE1_100MHZ:
78 result = pcix_100mhz;
79 break;
80 case PCI_X_SSTATUS_MODE1_133MHZ:
81 result = pcix_133mhz;
82 break;
83 case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ:
84 case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ:
85 case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ:
86 result = pcix_266mhz;
87 break;
88 case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ:
89 case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ:
90 case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ:
91 result = pcix_533mhz;
92 break;
93 }
94
95 return result;
96 }
97
pcix_scan_bridge(struct device * dev)98 void pcix_scan_bridge(struct device *dev)
99 {
100 unsigned int pos;
101 u16 sstatus;
102
103 do_pci_scan_bridge(dev, pci_scan_bus);
104
105 /* Find the PCI-X capability. */
106 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
107 sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
108
109 if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI)
110 pcix_tune_bus(dev->downstream);
111
112 /* Print the PCI-X bus speed. */
113 printk(BIOS_DEBUG, "PCI: %02x:%02x: %s\n", dev->downstream->segment_group,
114 dev->downstream->secondary, pcix_speed(sstatus));
115 }
116
117 /** Default device operations for PCI-X bridges */
118 static struct pci_operations pcix_bus_ops_pci = {
119 .set_subsystem = 0,
120 };
121
122 struct device_operations default_pcix_ops_bus = {
123 .read_resources = pci_bus_read_resources,
124 .set_resources = pci_dev_set_resources,
125 .enable_resources = pci_bus_enable_resources,
126 .scan_bus = pcix_scan_bridge,
127 .reset_bus = pci_bus_reset,
128 .ops_pci = &pcix_bus_ops_pci,
129 };
130