xref: /aosp_15_r20/external/coreboot/src/cpu/x86/entry32.S (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3/* For starting coreboot in protected mode */
4
5/*
6 * This is the modern bootblock. It prepares the system for C environment runtime
7 * setup. The actual setup is done by hardware-specific code.
8 *
9 * It provides a bootflow similar to other architectures, and thus is considered
10 * to be the modern approach.
11 *
12 */
13
14#include <arch/rom_segs.h>
15#include <cpu/x86/cr.h>
16#include <cpu/x86/post_code.h>
17
18.section .init, "ax", @progbits
19
20	.code32
21/*
22 *	When we come here we are in protected mode.
23 *	NOTE aligned to 4 so that we are sure that the prefetch
24 *	cache will be reloaded.
25 */
26	.align	4
27
28.globl bootblock_protected_mode_entry
29bootblock_protected_mode_entry:
30
31	/* Save the BIST value */
32	movl	%eax, %ebp
33
34	post_code(POSTCODE_ENTER_PROTECTED_MODE)
35
36	movw	$ROM_DATA_SEG, %ax
37	movw	%ax, %ds
38	movw	%ax, %es
39	movw	%ax, %ss
40	xor	%ax, %ax /* zero out the gs and fs segment index */
41	movw	%ax, %fs
42	movw	%ax, %gs /* Will be used for cpu_info */
43
44	/* Restore the BIST value to %eax */
45	movl	%ebp, %eax
46
47#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
48
49	/* Wait for a JTAG debugger to break in and set EBX non-zero */
50	xor	%ebx, %ebx
51
52debug_spinloop:
53	cmp	$0, %ebx
54	jz	debug_spinloop
55#endif
56
57	/* MMX registers required here */
58
59	/* BIST result in eax */
60	movd	%eax, %mm0
61
62__timestamp:
63
64	/* Get an early timestamp */
65	rdtsc
66	movd	%eax, %mm1
67	movd	%edx, %mm2
68
69#if CONFIG(SSE)
70enable_sse:
71	mov	%cr4, %eax
72	or	$CR4_OSFXSR, %ax
73	mov	%eax, %cr4
74#endif /* CONFIG(SSE) */
75
76	/* We're done. Now it's up to platform-specific code */
77	jmp	bootblock_pre_c_entry
78