1## SPDX-License-Identifier: GPL-2.0-only 2 3if ARCH_X86 4 5config PARALLEL_MP 6 def_bool y 7 help 8 This option uses common MP infrastructure for bringing up APs 9 in parallel. It additionally provides a more flexible mechanism 10 for sequencing the steps of bringing up the APs. 11 The code also works for just initialising the BSP in case there 12 are no APs. 13 14config PARALLEL_MP_AP_WORK 15 def_bool n 16 depends on PARALLEL_MP 17 help 18 Allow APs to do other work after initialization instead of going 19 to sleep. 20 21config X86_SMM_SKIP_RELOCATION_HANDLER 22 bool 23 default n 24 depends on PARALLEL_MP && HAVE_SMI_HANDLER 25 help 26 Skip SMM relocation using a relocation handler running in SMM 27 with a stub at 0x30000. This is useful on platforms that have 28 an alternative way to set SMBASE. 29 30config DEFAULT_X2APIC 31 def_bool n 32 help 33 Allow SoC code to set LAPIC access mode to X2APIC. 34 35config DEFAULT_X2APIC_RUNTIME 36 def_bool n 37 help 38 Allow SoC code to set LAPIC access mode to X2APIC_RUNTIME. 39 40config DEFAULT_X2APIC_LATE_WORKAROUND 41 def_bool n 42 help 43 Allow SoC code to set LAPIC access mode to X2APIC_LATE_WORKAROUND. 44 45choice 46 prompt "APIC operation mode" 47 default X2APIC_ONLY if DEFAULT_X2APIC 48 default X2APIC_RUNTIME if DEFAULT_X2APIC_RUNTIME 49 default X2APIC_LATE_WORKAROUND if DEFAULT_X2APIC_LATE_WORKAROUND 50 default XAPIC_ONLY 51 52config XAPIC_ONLY 53 prompt "Set XAPIC mode" 54 bool 55 help 56 coreboot and SMM runtime only use XAPIC mode. 57 FIXME: DMAR should have X2APIC optout bit set. 58 59config X2APIC_ONLY 60 prompt "Set X2APIC mode" 61 bool 62 depends on PARALLEL_MP 63 help 64 coreboot and SMM runtime only use X2APIC mode. 65 Note: OS switches back to XAPIC mode if VT-d is disabled. 66 FIXME: S3 resume (and SMM runtime) will break if OS makes the switch. 67 68config X2APIC_RUNTIME 69 prompt "Support both XAPIC and X2APIC" 70 bool 71 depends on PARALLEL_MP 72 help 73 The switch to X2APIC mode happens early in ramstage. SMM runtime can 74 support either mode in case the OS switches back to XAPIC. 75 76config X2APIC_LATE_WORKAROUND 77 prompt "Use XAPIC for AP bringup, then change to X2APIC" 78 bool 79 depends on PARALLEL_MP && MAX_CPUS < 256 80 help 81 Choose this option if the platform supports dynamic switching between 82 XAPIC to X2APIC. The initial Application Processors (APs) are configured 83 in XAPIC mode at reset and later enable X2APIC as a CPU feature. 84 All access mechanisms between XAPIC (mmio) and X2APIC (msr) switches 85 at runtime when this option is enabled. 86 87endchoice 88 89config UDELAY_LAPIC 90 bool 91 default n 92 93config LAPIC_MONOTONIC_TIMER 94 def_bool n 95 depends on UDELAY_LAPIC 96 help 97 Expose monotonic time using the local APIC. 98 99config UDELAY_LAPIC_FIXED_FSB 100 int 101 102config UDELAY_TSC 103 bool 104 default n 105 106config UNKNOWN_TSC_RATE 107 bool 108 default y if LAPIC_MONOTONIC_TIMER 109 110config TSC_MONOTONIC_TIMER 111 def_bool n 112 depends on UDELAY_TSC 113 help 114 Expose monotonic time using the TSC. 115 116config TSC_SYNC_LFENCE 117 bool 118 default n 119 help 120 The CPU driver should select this if the CPU needs 121 to execute an lfence instruction in order to synchronize 122 rdtsc. This is true for all modern AMD CPUs. 123 124config TSC_SYNC_MFENCE 125 bool 126 default n 127 help 128 The CPU driver should select this if the CPU needs 129 to execute an mfence instruction in order to synchronize 130 rdtsc. This is true for all modern Intel CPUs. 131 132config SETUP_XIP_CACHE 133 bool 134 depends on !NO_XIP_EARLY_STAGES 135 help 136 Select this option to set up an MTRR to cache XIP stages loaded 137 from the bootblock. This is useful on platforms lacking a 138 non-eviction mode and therefore need to be careful to avoid 139 eviction. 140 141config X86_CLFLUSH_CAR 142 bool 143 help 144 Select this on platforms that allow CLFLUSH while operating in CAR. 145 146config HAVE_SMI_HANDLER 147 bool 148 default n 149 depends on (SMM_ASEG || SMM_TSEG) 150 151config NO_SMM 152 bool 153 default n 154 155config NEED_SMALL_2MB_PAGE_TABLES 156 bool 157 default n 158 help 159 Select this option from boards/SoCs that do not support the Page1GB 160 CPUID feature (CPUID.80000001H:EDX.bit26). 161 162config SMM_ASEG 163 bool 164 default n 165 depends on !NO_SMM 166 help 167 Legacy memory region of SMM (System Management Mode). It has been 168 replaced by TSEG and is currently only used for QEMU emulation target. 169 170config SMM_TSEG 171 bool 172 default y 173 depends on !(NO_SMM || SMM_ASEG) 174 help 175 Top of Low Memory Segment (TSEG) is comprised of the SMRAM and IEDRAM. 176 SMRAM is a memory region used in SMM (System Management Mode) only. 177 IEDRAM is a memory region used for enhanced debug features. 178 SMM-mode processor access to TSEG always targets the physical DRAM. 179 180if HAVE_SMI_HANDLER 181 182config SMM_MODULE_STACK_SIZE 183 hex 184 default 0x800 if ARCH_RAMSTAGE_X86_64 185 default 0x400 186 help 187 This option determines the size of the stack within the SMM handler 188 modules. 189 190endif 191 192config SMM_LAPIC_REMAP_MITIGATION 193 bool 194 default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \ 195 || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \ 196 || NORTHBRIDGE_INTEL_E7505 || NORTHBRIDGE_INTEL_IRONLAKE 197 default n 198 199config SMM_PCI_RESOURCE_STORE 200 bool 201 default n 202 help 203 This option enables support for storing PCI resources in SMRAM so 204 SMM can tell if they've been altered. 205 206config SMM_PCI_RESOURCE_STORE_NUM_SLOTS 207 int 208 default 8 209 help 210 Number of slots available to store PCI BARs in SMRAM 211 212config X86_AMD_FIXED_MTRRS 213 bool 214 default n 215 help 216 This option informs the MTRR code to use the RdMem and WrMem fields 217 in the fixed MTRR MSRs. 218 219config X86_INIT_NEED_1_SIPI 220 bool 221 default n 222 help 223 This option limits the number of SIPI signals sent during the 224 common AP setup. Intel documentation specifies an INIT SIPI SIPI 225 sequence, however this doesn't work on some AMD and Intel platforms. 226 These newer AMD and Intel platforms don't need the 10ms wait between 227 INIT and SIPI, so skip that too to save some time. 228 229config SOC_SETS_MSRS 230 bool 231 default n 232 help 233 The SoC requires different access methods for reading and writing 234 the MSRs. Use SoC specific routines to handle the MSR access. 235 236config RESERVE_MTRRS_FOR_OS 237 bool 238 default n 239 help 240 This option allows a platform to reserve 2 MTRRs for the OS usage. 241 The Intel SDM documents that the first 6 MTRRs are intended for 242 the system BIOS and the last 2 are to be reserved for OS usage. 243 However, modern OSes use PAT to control cacheability instead of 244 using MTRRs. 245 246config AP_STACK_SIZE 247 hex 248 default 0x800 249 help 250 This is the amount of stack each AP needs. The BSP stack size can be 251 larger and is set with STACK_SIZE. 252 253config RUNTIME_CONFIGURABLE_SMM_LOGLEVEL 254 bool 255 default n 256 depends on DEBUG_SMI && CONSOLE_OVERRIDE_LOGLEVEL 257 help 258 This enables setting the SMM console log level at runtime for more 259 flexibility to use different log levels for each stage. Another reason 260 is that reading the log level from non-volatile memory such as flash 261 VPD or CMOS is not very ideal to be done in SMM, with this option the 262 value can be passed via the member variable in struct smm_runtime and 263 be referenced directly in SMM. 264 265endif # ARCH_X86 266