xref: /aosp_15_r20/external/coreboot/src/arch/x86/postcar.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/romstage.h>
4 #include <cbmem.h>
5 #include <console/console.h>
6 #include <cpu/x86/mtrr.h>
7 #include <main_decl.h>
8 #include <program_loading.h>
9 #include <timestamp.h>
10 
11 /*
12  * Systems without a native coreboot cache-as-ram teardown may implement
13  * this to use an alternate method.
14  */
late_car_teardown(void)15 __weak void late_car_teardown(void) { /* do nothing */ }
16 
main(void)17 void main(void)
18 {
19 	late_car_teardown();
20 
21 	console_init();
22 
23 	/*
24 	 * CBMEM needs to be recovered because timestamps rely on
25 	 * the cbmem infrastructure being around. Explicitly recover it.
26 	 *
27 	 * On some platforms CBMEM needs to be initialized earlier.
28 	 * Use cbmem_online() to avoid init CBMEM twice.
29 	 */
30 	if (!cbmem_online())
31 		cbmem_initialize();
32 
33 	timestamp_add_now(TS_POSTCAR_START);
34 
35 	display_mtrrs();
36 
37 	/* Load and run ramstage. */
38 	run_ramstage();
39 }
40