1## SPDX-License-Identifier: GPL-2.0-only 2 3config ARCH_X86 4 bool 5 select PCI 6 select RELOCATABLE_MODULES 7 select HAVE_ASAN_IN_RAMSTAGE 8 select ARCH_SUPPORTS_CLANG 9 10if ARCH_X86 11 12# stage selectors for x86 13 14config ARCH_BOOTBLOCK_X86_32 15 bool 16 17config ARCH_VERSTAGE_X86_32 18 bool 19 20config ARCH_ROMSTAGE_X86_32 21 bool 22 23config ARCH_POSTCAR_X86_32 24 bool 25 default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE 26 27config ARCH_RAMSTAGE_X86_32 28 bool 29 30config ARCH_ALL_STAGES_X86_32 31 bool 32 default !ARCH_ALL_STAGES_X86_64 33 select ARCH_BOOTBLOCK_X86_32 34 select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK 35 select ARCH_ROMSTAGE_X86_32 36 select ARCH_RAMSTAGE_X86_32 37 38# stage selectors for x64 39 40config ARCH_BOOTBLOCK_X86_64 41 bool 42 select SSE2 43 44config ARCH_VERSTAGE_X86_64 45 bool 46 select SSE2 47 48config ARCH_ROMSTAGE_X86_64 49 bool 50 select SSE2 51 52config ARCH_POSTCAR_X86_64 53 bool 54 default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE 55 select SSE2 56 57config ARCH_RAMSTAGE_X86_64 58 bool 59 select SSE2 60 61config ARCH_ALL_STAGES_X86_64 62 bool 63 select ARCH_BOOTBLOCK_X86_64 64 select ARCH_VERSTAGE_X86_64 if !VBOOT_STARTS_BEFORE_BOOTBLOCK 65 select ARCH_ROMSTAGE_X86_64 66 select ARCH_RAMSTAGE_X86_64 67 68config HAVE_X86_64_SUPPORT 69 bool 70 help 71 Enable support to build and run coreboot in 64-bit mode. 72 When enabling this option for a new platform, it is recommended to 73 provide a config file for Jenkins to build-test the 64-bit option. 74 75config USE_X86_64_SUPPORT 76 bool "Run coreboot in long (64-bit) mode" 77 depends on HAVE_X86_64_SUPPORT 78 select ARCH_ALL_STAGES_X86_64 79 help 80 When set, most of coreboot runs in long (64-bit) mode instead of the 81 usual protected flat (32-bit) mode. 64-bit CPUs and OSes can be used 82 irrespective of whether coreboot runs in 32-bit or 64-bit mode. 83 84config PAGE_TABLES_IN_CBFS 85 bool 86 default n 87 88config ARCH_X86_64_PGTBL_LOC 89 hex "x86_64 page table location in CBFS" 90 depends on ARCH_BOOTBLOCK_X86_64 && PAGE_TABLES_IN_CBFS 91 default 0xfffe9000 92 help 93 The position where to place pagetables. Needs to be known at 94 compile time. Must not overlap other files in CBFS. 95 96config RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT 97 bool 98 help 99 On some systems, the upper physical address bits are reserved and 100 used as a tag which is typically related to a memory encryption 101 feature. When selecting this option, the SoC code needs to implement 102 get_reserved_phys_addr_bits so that the common code knows how many of 103 the most significant physical address bits are reserved and can't be 104 used as address bits. 105 106# This is an SMP option. It relates to starting up APs. 107# It is usually set in mainboard/*/Kconfig. 108# TODO: Improve description. 109config AP_IN_SIPI_WAIT 110 bool 111 default n 112 depends on ARCH_X86 && SMP 113 114config RESET_VECTOR_IN_RAM 115 bool 116 depends on ARCH_X86 117 select NO_XIP_EARLY_STAGES 118 help 119 Select this option if the x86 processor's reset vector is in 120 preinitialized DRAM instead of the traditional 0xfffffff0 location. 121 122# Aligns 16bit entry code in bootblock so that hyper-threading CPUs 123# can boot AP CPUs to enable their shared caches. 124config SIPI_VECTOR_IN_ROM 125 bool 126 default n 127 depends on ARCH_X86 128 129# Traditionally BIOS region on SPI flash boot media was memory mapped right below 130# 4G and it was the last region in the IFD. This way translation between CPU 131# address space to flash address was trivial. However some IFDs on newer SoCs 132# have BIOS region sandwiched between descriptor and other regions. Turning on 133# X86_CUSTOM_BOOTMEDIA disables X86_TOP4G_BOOTMEDIA_MAP which allows the 134# soc code to provide custom mmap_boot.c. 135config X86_CUSTOM_BOOTMEDIA 136 bool 137 138config X86_TOP4G_BOOTMEDIA_MAP 139 bool 140 depends on !X86_CUSTOM_BOOTMEDIA 141 default y 142 143config PRERAM_CBMEM_CONSOLE_SIZE 144 hex 145 default 0xc00 146 help 147 Increase this value if preram cbmem console is getting truncated 148 149config CBFS_MCACHE_SIZE 150 hex 151 depends on !NO_CBFS_MCACHE 152 default 0x4000 153 help 154 Increase this value if you see CBFS mcache overflow warnings. Do NOT 155 change this value for vboot RW updates! 156 157config PRERAM_CBFS_CACHE_SIZE 158 hex 159 default 0x4000 160 help 161 Define the size of the Pre-RAM stages CBFS cache. A size of 162 zero disables the CBFS cache feature in pre-memory stages. 163 164config POSTRAM_CBFS_CACHE_IN_BSS 165 bool 166 default y if !SOC_AMD_COMMON_BLOCK_NONCAR 167 help 168 Allocate the post-memory CBFS cache scratchpad in the .bss 169 section. CBFS cache will rely on a simple static C buffer 170 while traditionally CBFS cache memory region is reserved in 171 the device memory layout. 172 173config RAMSTAGE_CBFS_CACHE_SIZE 174 hex 175 default 0x4000 176 depends on POSTRAM_CBFS_CACHE_IN_BSS 177 help 178 Define the size of the ramstage CBFS cache. A size of zero 179 disables the CBFS cache feature in ramstage. 180 181config PC80_SYSTEM 182 bool 183 default y if ARCH_X86 184 185config BOOTBLOCK_DEBUG_SPINLOOP 186 bool 187 default n 188 help 189 Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait 190 for a JTAG debugger to break into the execution sequence. 191 192config HAVE_CMOS_DEFAULT 193 def_bool n 194 depends on HAVE_OPTION_TABLE 195 196config CMOS_DEFAULT_FILE 197 string 198 default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" 199 depends on HAVE_CMOS_DEFAULT 200 201config HPET_MIN_TICKS 202 hex 203 204config C_ENV_BOOTBLOCK_SIZE 205 hex 206 default 0x40000 if !FIXED_BOOTBLOCK_SIZE 207 help 208 This is only the default maximum of bootblock size for linking 209 purposes. Platforms may provide different limit and need to 210 specify this when FIXED_BOOTBLOCK_SIZE is selected. 211 212config FIXED_BOOTBLOCK_SIZE 213 bool 214 215# Default address romstage is to be linked at 216config ROMSTAGE_ADDR 217 hex 218 default 0x2000000 219 220# Default address verstage is to be linked at 221config VERSTAGE_ADDR 222 hex 223 default 0x2000000 224 225# Use the post CAR infrastructure for tearing down cache-as-ram 226# from a program loaded in RAM and subsequently loading ramstage. 227config POSTCAR_STAGE 228 def_bool y 229 depends on ARCH_X86 230 depends on !RESET_VECTOR_IN_RAM 231 232config VERSTAGE_DEBUG_SPINLOOP 233 bool 234 default n 235 help 236 Add a spin (JMP .) in assembly_entry.S during early verstage to wait 237 for a JTAG debugger to break into the execution sequence. 238 239config ROMSTAGE_DEBUG_SPINLOOP 240 bool 241 default n 242 help 243 Add a spin (JMP .) in assembly_entry.S during early romstage to wait 244 for a JTAG debugger to break into the execution sequence. 245 246choice 247 prompt "Bootblock behaviour" 248 default BOOTBLOCK_SIMPLE 249 depends on !VBOOT 250 251config BOOTBLOCK_SIMPLE 252 bool "Always load fallback" 253 254config BOOTBLOCK_NORMAL 255 bool "Switch to normal if CMOS says so" 256 select CONFIGURABLE_CBFS_PREFIX 257 select SEPARATE_ROMSTAGE 258 259endchoice 260 261config SKIP_MAX_REBOOT_CNT_CLEAR 262 bool "Do not clear reboot count after successful boot" 263 depends on BOOTBLOCK_NORMAL 264 help 265 Do not clear the reboot count immediately after successful boot. 266 Set to allow the payload to control normal/fallback image recovery. 267 Note that it is the responsibility of the payload to reset the 268 normal boot bit to 1 after each successful boot. 269 270config ACPI_BERT 271 bool 272 depends on HAVE_ACPI_TABLES 273 help 274 Build an ACPI Boot Error Record Table. 275 276config COLLECT_TIMESTAMPS_NO_TSC 277 bool 278 default n 279 depends on COLLECT_TIMESTAMPS 280 help 281 Use a non-TSC platform-dependent source for timestamps. 282 283config COLLECT_TIMESTAMPS_TSC 284 bool 285 default y if !COLLECT_TIMESTAMPS_NO_TSC 286 default n 287 depends on COLLECT_TIMESTAMPS 288 help 289 Use the TSC as the timestamp source. 290 291config PAGING_IN_CACHE_AS_RAM 292 bool 293 default n 294 depends on ARCH_X86 295 help 296 Chipsets scan select this option to preallocate area in cache-as-ram 297 for storing paging data structures. PAE paging is currently the 298 only thing being supported. 299 300config NUM_CAR_PAGE_TABLE_PAGES 301 int 302 default 5 303 depends on PAGING_IN_CACHE_AS_RAM 304 help 305 The number of 4KiB pages that should be pre-allocated for page tables. 306 307# Provide the interrupt handlers to every stage. Not all 308# stages may take advantage. 309config IDT_IN_EVERY_STAGE 310 bool 311 default n 312 depends on ARCH_X86 313 314config HAVE_CF9_RESET 315 bool 316 317config HAVE_CF9_RESET_PREPARE 318 bool 319 depends on HAVE_CF9_RESET 320 321config HAVE_CONFIGURABLE_APMC_SMI_PORT 322 bool 323 help 324 SoCs that have a configurable APMC SMI command port, should select 325 this option and implement pm_acpi_smi_cmd_port() that returns the IO 326 port. 327 328config PIRQ_ROUTE 329 bool 330 default n 331 332config MAX_PIRQ_LINKS 333 int 334 default 4 335 depends on PIRQ_ROUTE 336 help 337 This variable specifies the number of PIRQ interrupt links which are 338 routable. On most chipsets, this is 4, INTA through INTD. Some 339 chipsets offer more than four links, commonly up to INTH. They may 340 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ 341 table specifies links greater than 4, pirq_route_irqs will not 342 function properly, unless this variable is correctly set. 343 344config MEMLAYOUT_LD_FILE 345 string 346 default "src/arch/x86/memlayout.ld" 347 348config DEBUG_HW_BREAKPOINTS 349 bool 350 default y 351 help 352 Enable support for hardware data and instruction breakpoints through 353 the x86 debug registers 354 355config DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES 356 bool 357 default y 358 depends on DEBUG_HW_BREAKPOINTS && IDT_IN_EVERY_STAGE 359 360config DEBUG_NULL_DEREF_BREAKPOINTS 361 bool 362 default y 363 depends on DEBUG_HW_BREAKPOINTS 364 help 365 Enable support for catching null dereferences and instruction execution 366 367config DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES 368 bool 369 default y 370 depends on DEBUG_NULL_DEREF_BREAKPOINTS && DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES 371 372config DEBUG_NULL_DEREF_HALT 373 bool 374 default n 375 depends on DEBUG_NULL_DEREF_BREAKPOINTS 376 help 377 When enabled null dereferences and instruction fetches will halt execution. 378 Otherwise an error will be printed. 379 380# Some EC need an "EC firmware pointer" (a data structure hinting the address 381# of its firmware blobs) being put at a fixed position. Its space 382# (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a 383# stage. Different EC may have different format and/or value for it. The actual 384# address of EC firmware pointer should be provided in the Kconfig of the EC 385# requiring it, and its value could be filled by linking a read-only global 386# data object to the section above. 387 388config ECFW_PTR_ADDR 389 hex 390 help 391 Address of reserved space for EC firmware pointer, which should not 392 overlap other data such as reset vector or FIT pointer if present. 393 394config ECFW_PTR_SIZE 395 int 396 help 397 Size of reserved space for EC firmware pointer 398 399config DUMP_SMBIOS_TYPE17 400 bool "Dump part of SMBIOS type17 dimm information" 401 depends on GENERATE_SMBIOS_TABLES 402 403config SOC_PHYSICAL_ADDRESS_WIDTH 404 int 405 default 0 406 help 407 On some System-on-Chip the physical address size available 408 at the SoC level may be different than at the CPU 409 level. This configuration can be use to set the physical 410 address width (in bits) of the SoC. 411 412 If not set, both CPU and SoC physical address width are 413 assume to be the same. 414 415config X86_BOOTBLOCK_EXTRA_PROGRAM_SZ 416 int 417 default 1024 if CHROMEOS 418 default 0 419 help 420 Add extra space to prevent overlap between .text and .init sections. 421 This is necessary for older linkers (pre-binutils 2.4x) like those used 422 on ChromeOS platforms. 423 424 The default value is 1024 bytes (1 KiB) for ChromeOS and 0 for other platforms. 425 426endif 427