1## SPDX-License-Identifier: GPL-2.0-only 2 3config ARCH_RISCV_RV64 4 bool 5 select ARCH_RISCV 6 7config ARCH_RISCV_RV32 8 bool 9 select ARCH_RISCV 10 11config ARCH_RISCV 12 bool 13 select ARCH_SUPPORTS_CLANG 14 15if ARCH_RISCV 16 17config RISCV_ARCH 18 string 19 20config RISCV_ABI 21 string 22 23config RISCV_CODEMODEL 24 string 25 26config ARCH_RISCV_M_DISABLED 27 bool 28 29config ARCH_RISCV_M 30 # Whether a SOC implements M mode. 31 # M mode is the most privileged mode, it is 32 # the equivalent in some ways of x86 SMM mode 33 # save that in M mode it is impossible to turn 34 # on paging. 35 # While the spec requires it, there is at least 36 # one implementation that will not have it due 37 # to security concerns. 38 bool 39 default y if ARCH_RISCV && !ARCH_RISCV_M_DISABLED 40 default n 41 42config ARCH_RISCV_S 43 # S (supervisor) mode is for kernels. It is optional. 44 bool 45 default n 46 47config RISCV_HAS_OPENSBI 48 def_bool n 49 50config RISCV_OPENSBI 51 bool "Use OpenSBI to hand over control to payload" 52 depends on ARCH_RISCV_M && ARCH_RISCV_S 53 depends on RISCV_HAS_OPENSBI 54 default n 55 help 56 Load OpenSBI after payload has been loaded and use it to 57 provide the SBI and to handover control to payload. 58 59config OPENSBI_PLATFORM 60 string 61 depends on RISCV_HAS_OPENSBI 62 help 63 The OpenSBI platform to build for. 64 65config OPENSBI_TEXT_START 66 hex 67 depends on RISCV_HAS_OPENSBI 68 help 69 The linking address used to build opensbi. 70 71config OPENSBI_FW_DYNAMIC_BOOT_HART 72 int 73 default RISCV_WORKING_HARTID 74 help 75 This specifies the hart that OpenSBI will use to boot the payload. If set to 76 value -1, OpenSBI will use a 'lottery' scheme to figure it out itself. 77 This hart must be able to execute in the Supervisor priviledged mode, since 78 that is the mode usually used for the payload. If the hart does not support 79 Supervisor mode OpenSBI will again look for a hart that does support it. 80 81config ARCH_RISCV_U 82 # U (user) mode is for programs. 83 bool 84 default n 85 86config ARCH_RISCV_PMP 87 bool 88 default n 89 90config ARCH_BOOTBLOCK_RISCV 91 bool 92 default n 93 94config ARCH_VERSTAGE_RISCV 95 bool 96 default n 97 98config ARCH_ROMSTAGE_RISCV 99 bool 100 default n 101 102config ARCH_RAMSTAGE_RISCV 103 bool 104 default n 105 106config RISCV_USE_ARCH_TIMER 107 bool 108 default n 109 110config RISCV_WORKING_HARTID 111 int 112 113# Newer SoC have the menvconfig register. 114# Very few SOC do not have this. 115# Older SoC, such as the SiFive FU[57]40, that 116# do not have this register, should set this 117# to n. 118config RISCV_SOC_HAS_MENVCFG 119 bool 120 default y 121 122endif # if ARCH_RISCV 123