xref: /aosp_15_r20/external/coreboot/Documentation/superio/nuvoton/npcd378.md (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1# NPCD378
2
3This page describes the [Nuvoton] SuperIO chip that can be found on various [HP]
4mainboards.
5
6As no datasheet is available most of the functions have been reverse engineered and
7might be inaccurate or wrong.
8
9## LDNs
10
11```{eval-rst}
12+-------+---------------------------+
13| LDN # | Function                  |
14+=======+===========================+
15| 0     | FDC                       |
16+-------+---------------------------+
17| 1     | Parallel Port             |
18+-------+---------------------------+
19| 2     | Com1                      |
20+-------+---------------------------+
21| 3     | Com2 / IR                 |
22+-------+---------------------------+
23| 4     | LED and PWR button CTRL   |
24+-------+---------------------------+
25| 5     | PS/2 AUX                  |
26+-------+---------------------------+
27| 6     | PS/2 KB                   |
28+-------+---------------------------+
29| 7     | WDT1                      |
30+-------+---------------------------+
31| 8     | HWM                       |
32+-------+---------------------------+
33| 0xf   | GPIO                      |
34+-------+---------------------------+
35| 0x15  | I2C ?                     |
36+-------+---------------------------+
37| 0x1e  | SUSPEND CTL ?             |
38+-------+---------------------------+
39| 0x1c  | GPIO ?                    |
40+-------+---------------------------+
41```
42
43### LDN0
44
45Follows [Nuvoton]'s default FDC register set. See [NCT6102D] for more details.
46
47### LDN1
48
49Follows [Nuvoton]'s default LPT register set. See [NCT6102D] for more details.
50
51### LDN2
52
53Follows [Nuvoton]'s default COM1 register set. See [NCT6102D] for more details.
54
55### LDN3
56
57Follows [Nuvoton]'s default COM2 register set. See [NCT6102D] for more details.
58
59### LDN4
60
61On most SuperIOs the use of LDN4 is forbidden. That's not the case on NPCD378.
62
63It exposes 16 byte of IO config space to control the front LEDs PWM duty cycle
64and power button behaviour on normal / during S3 resume.
65
66### LDN5
67
68A custom PS/2 AUX port.
69
70### LDN6
71
72Follows [Nuvoton]'s default KBC register set. See [NCT6102D] for more details.
73
74### LDN7
75
76Looks like a WDT.
77
78### LDN8
79
80Custom HWM space. It exposes 256 byte of IO config space.
81See [HWM](#HWM) for more details.
82
83## HWM
84
85### Register
86
87The registers are accessible via IO space and are located at LDN8's IOBASE.
88
89```{eval-rst}
90+---------------+-----------------------+
91| IOBASE offset | Register              |
92+---------------+-----------------------+
93| 0x4           | Host Write CTRL       |
94+---------------+-----------------------+
95| 0x10 - 0xfe   | HWM Page #            |
96+---------------+-----------------------+
97| 0xff          | Page index select     |
98+---------------+-----------------------+
99```
100
101### Host Write CTRL
102Bit 0 must be cleared prior to writing any of the HWM register and it must be
103set after writing to HWM register to signal the SuperIO that data has changed.
104Reading register is possible at any time and doesn't need special locking.
105
106### HWM Page
107The SuperIO exposes 16 different pages. Nearly all registers are unknown.
108
109**Page 1**
110
111```{eval-rst}
112+---------------+-----------------------+
113| IOBASE offset | Register              |
114+---------------+-----------------------+
115| 0x98          | PSU fan PWM           |
116+---------------+-----------------------+
117```
118
119### Page index
120The 4 LSB of the page index register selects which HWM page is active.
121A write takes effect immediately.
122
123[NCT6102D]: https://www.nuvoton.com/resource-files/NCT6102D_NCT6106D_Datasheet_V1_0.pdf
124[Nuvoton]: http://www.nuvoton.com/hq/
125[HP]: https://www.hp.com/
126