1coreboot 4.9 release notes 2========================== 3 4The 4.9 release covers commit 532b8d5f25 to commit 7f520c8fe6 5There is a pgp signed 4.9 tag in the git repository, and a branch will 6be created as needed. 7 8In the little more than 7 months since 4.8.1 we had 175 authors commit 92610 changes to master. The changes were, for the most part, all over 10the place, touching every part of the repository: chipsets, mainboards, 11tools, build system, documentation. 12 13In that time we also had 70 authors made their first commit to coreboot: 14Welcome and to many more! 15 16Finally, a big Thank You to all contributors who helped shape the 17coreboot project, community and code with their effort, no matter if 18through development, review, testing, documentation or by helping people 19asking questions on our venues like IRC or our mailing list. 20 21Clean up 22-------- 23If there's any topic to give to this release, "clean up" might be the 24most appropriate: There was lots of effort to bring the codebase into 25compliance with our coding style, to remove old idioms that we'd like 26to retire like the overloaded `device_t` data type, and to let features 27percolate through the entire tree to bring more uniformity to its parts. 28 29For example, during the coreboot 4.4 cycle, coreboot gained the notion 30of mainboard variants to avoid duplication of code in rather similar 31mainboards. 32 33Back then, this feature was developed and used mostly for the benefit 34of Chrome OS devices, but more recently the code for various Lenovo 35Thinkpads was deduplicated in the same way. 36 37Another part of cleaning up our tree is improving our tools that help 38developers follow coding style and avoid mistakes, as well as the 39infrastructure we have for automated build tests and we've seen quite 40some activity in that space as well. 41 42Documentation 43------------- 44Since the last release we also moved the documentation into the 45repository. No need for a special wiki account to edit the documentation, 46and by colocating sources and documentation, it's easier to keep the 47latter in sync with the code, too. 48 49This effort is still under way, which is why we still host the old wiki (now 50read-only) in parallel to the [new documentation 51site](https://doc.coreboot.org) that is rendered from coreboot.git's 52Documentation/ directory. 53 54Blobs handling 55-------------- 56Another big change is in our blobs handling: Given that Intel now 57provides a reasonably licensed repository with FSP binaries, we were 58able to mirror it to coreboot.org and integrate it in the build system. 59This makes it easier to have working images out of the box for devices 60that depend on Intel's proprietary init code. 61 62As usual the blobs aren't part of the coreboot tree and only downloaded 63with the `USE_BLOBS` options. 64 65Deprecations 66------------ 67One of the first changes to coreboot after the 4.8 release was to remove 68boards that didn't support certain new features and were apparently 69unmaintained, as discussed in the release notes of coreboot 4.6. 70 71We didn't follow up on all plans made back then to deprecate boards more 72aggressively: The board status reporting mechanism is still rather raw 73and therefore places quite a burden on otherwise sympathetic contributors 74of build results. 75 76Also, there will be no deprecations after 4.10: Due to its slipping 77schedule, coreboot 4.9 is released rather late, and as a result 4.10 78will only see about 4 months of development. We considered that a rather 79short timeframe in which to bring old boards up to new standards, and 80so the next deprecation cycle may be announced with 4.10 to occur after 814.11 is released, in late 2019. 82 83General changes 84--------------- 85* Various code cleanups 86 * Removed `device_t` in favor of `struct device*` in ramstage code 87 * Removed unnecessary include directives 88 * Improved adherence to coding style 89 * Deduplicated boards by using the variants mechanism 90* Expand use of the postcar stage 91* Add bootblock compression capability: on systems that copy the bootblock 92 from very slow flash to SRAM, allow adding a stub that decompresses the 93 bootblock into SRAM to minimize the amount of flash reads 94* Rename the POWER8 architecture port to PPC64 to reflect that it isn't limited 95 to POWER8 96* Added support for booting FIT (uImage) payloads on arm64 97* Added SPI flash write protection API 98 * Implemented on Winbond 99* Implemented TCPA log for measured boot 100* Implemented GDB support for arm64 architecture in libpayload 101* Dropped support for unmaintained code paths 102* Measured boot support 103 104Added 56 mainboards 105------------------- 106* ASROCK G41C-GS 107* ASROCK G41M-GS 108* ASROCK G41M-S3 109* ASROCK G41M-VS3 R2.0 110* ASROCK H81M-HDS 111* ASUS P5QC 112* ASUS P5QL-PRO 113* ASUS P5Q-PRO 114* ASUS P8H61-M-LX 115* ASUS P8H61-M-PRO 116* CAVIUM CN8100-SFF-EVB 117* FACEBOOK WATSON 118* FOXCONN D41S 119* GIGABYTE GA-H61M-S2PV 120* GOOGLE ALEENA 121* GOOGLE AMPTON 122* GOOGLE ARCADA 123* GOOGLE ASUKA 124* GOOGLE BOBBA 125* GOOGLE BUDDY 126* GOOGLE CAREENA 127* GOOGLE CAROLINE 128* GOOGLE CASTA 129* GOOGLE CAVE 130* GOOGLE DELAN 131* GOOGLE DRAGONEGG 132* GOOGLE FLEEX 133* GOOGLE HATCH 134* GOOGLE KARMA 135* GOOGLE KUKUI 136* GOOGLE LIARA 137* GOOGLE MEEP 138* GOOGLE RAMMUS 139* GOOGLE SARIEN 140* GOOGLE SENTRY 141* HEWLETT PACKARD HP COMPAQ 8200 ELITE SFF PC 142* INTEL COFFEELAKE RVP11 143* INTEL COFFEELAKE RVP8 144* INTEL COFFEELAKE RVPU 145* INTEL DG41WV 146* INTEL ICELAKE RVPU 147* INTEL ICELAKE RVPY 148* INTEL WHISKEYLAKE RVP 149* LENOVO T431S 150* LENOVO THINKCENTRE A58 151* LENOVO W500 152* LENOVO W530 153* OPENCELLULAR ELGON 154* OPENCELLULAR ROTUNDU 155* OPENCELLULAR SUPABRCKV1 156* SIEMENS MC-APL2 157* SIEMENS MC-APL3 158* SIEMENS MC-APL4 159* SIEMENS MC-APL5 160 161Dropped 71 mainboards 162--------------------- 163* AAEON PFM-540I REVB 164* AMD DB800 165* AMD DBM690T 166* AMD F2950 167* AMD MAHOGANY 168* AMD NORWICH 169* AMD PISTACHIO 170* AMD SERENGETI-CHEETAH 171* ARTECGROUP DBE61 172* ASROCK 939A785GMH 173* ASUS A8N-E 174* ASUS A8N-SLI 175* ASUS A8V-E DELUXE 176* ASUS A8V-E SE 177* ASUS K8V-X 178* ASUS KFSN4-DRE K8 179* ASUS M2N-E 180* ASUS M2V 181* ASUS M2V MX-SE 182* BACHMANN OT200 183* BCOM WINNETP680 184* BROADCOM BLAST 185* DIGITALLOGIC MSM800SEV 186* GIGABYTE GA-2761GXDK 187* GIGABYTE M57SLI 188* GOOGLE KAHLEE 189* GOOGLE MEOWTH 190* GOOGLE PURIN 191* GOOGLE ROTOR 192* GOOGLE ZOOMBINI 193* HP DL145-G1 194* HP DL145-G3 195* IEI PCISA LX-800 R10 196* IEI PM LX2-800 R10 197* IEI PM LX-800 R11 198* INTEL COUGAR-CANYON2 199* INTEL STARGO2 200* IWILL DK8 HTX 201* JETWAY J7F2 202* JETWAY J7F4K1G2E 203* JETWAY J7F4K1G5D 204* KONTRON KT690 205* LINUTOP LINUTOP1 206* LIPPERT HURRICANE LX 207* LIPPERT LITERUNNER LX 208* LIPPERT ROADRUNNER LX 209* LIPPERT SPACERUNNER LX 210* LOWRISC NEXYS4DDR 211* MSI MS7135 212* MSI MS7260 213* MSI MS9185 214* MSI MS9282 215* NVIDIA L1-2PVV 216* SIEMENS SITEMP-G1P1 217* SUNW ULTRA40 218* SUNW ULTRA40M2 219* SUPERMICRO H8DME 220* SUPERMICRO H8DMR 221* TECHNEXION TIM5690 222* TECHNEXION TIM8690 223* TRAVERSE GEOS 224* TYAN S2912 225* VIA EPIA-CN 226* VIA EPIA-M700 227* VIA PC2500E 228* VIA VT8454C 229* WINENT MB6047 230* WINENT PL6064 231* WINNET G170 232 233CPU changes 234----------- 235* cpu/intel/model\_2065x,206ax,haswell: Switch to `POSTCAR_STAGE` 236* cpu/intel/slot\_1: Switch to different CAR setup 237* Dropped support for the FSP1.0 sandy-/ivy-bridge bootpath 238 239SoC changes 240----------- 241* Added Cavium CN81xx, Intel Ice Lake and Mediatek MT8183 242* Dropped Broadcom Cygnus, Lowrisc and Marvell mvmap2315 243 244Northbridge changes 245------------------- 246* Dropped AMD K8, VIA CN700, VIA CX700, VIA VX800 because they lack `EARLY_CBMEM` support 247* intel/e7505: Moved to `EARLY_CBMEM` 248* nb/intel/i945,e7505,pineview,x4x,gm45,i440bx: Moved to `POSTCAR_STAGE` 249* nb/intel/i440bx, e7505: Moved to `RELOCATABLE_RAMSTAGE` 250* intel/x4x: Add DDR3 support 251* nb/intel/pineview: Speed up fetching SPD 252* nb/intel/i945,gm45,x4x,pineview: Use TSEG in SMI 253 254Southbridge changes 255------------------- 256* sb/intel/i82801{g,i,j}x, lynxpoint: Use the common ACPI pirq generator 257* sb/intel/i82801{g,i,j}x: Use common code to set up SMM and for the smihandler 258* Use common functions for PMBASE configuration 259 260Payload changes 261--------------- 262* Support initrd in uImage/FIT to be placed above 4GiB 263* Added documentation for uImage/FIT payloads 264 265Toolchain 266--------- 267* Update to gcc 8.1.0, binutils 2.30, IASL 20180810, clang 6 268