1coreboot 4.14 2============= 3 4coreboot 4.14 was released on May 10th, 2021. 5 6Since 4.13 there have been 3660 new commits by 215 developers. 7Of these, about 50 contributed to coreboot for the first time. 8Welcome to the project! 9 10These changes have been all over the place, so that there's no 11particular area to focus on when describing this release: We had 12improvements to mainboards, to chipsets (including much welcomed 13work to open source implementations of what has been blobs before), 14to the overall architecture. 15 16Thank you to all developers who made coreboot the great open source 17firmware project that it is, and made our code better than ever. 18 19New mainboards 20-------------- 21 22* AMD Bilby 23* AMD Majolica 24* GIGABYTE GA-D510UD 25* Google Blipper 26* Google Brya 27* Google Cherry 28* Google Collis 29* Google Copano 30* Google Cozmo 31* Google Cret 32* Google Drobit 33* Google Galtic 34* Google Gumboz 35* Google Guybrush 36* Google Herobrine 37* Google Homestar 38* Google Katsu 39* Google Kracko 40* Google Lalala 41* Google Makomo 42* Google Mancomb 43* Google Marzipan 44* Google Pirika 45* Google Sasuke 46* Google Sasukette 47* Google Spherion 48* Google Storo 49* Google Volet 50* HP 280 G2 51* Intel Alderlake-M RVP 52* Intel Alderlake-M RVP with Chrome EC 53* Intel Elkhartlake LPDDR4x CRB 54* Intel shadowmountain 55* Kontron COMe-mAL10 56* MSI H81M-P33 (MS-7817 v1.2) 57* Pine64 ROCKPro64 58* Purism Librem 14 59* System76 darp5 60* System76 galp3-c 61* System76 gaze15 62* System76 oryp5 63* System76 oryp6 64 65Removed mainboards 66------------------ 67 68* Google Boldar 69* Intel Cannonlake U LPDDR4 RVP 70* Intel Cannonlake Y LPDDR4 RVP 71 72Deprecations and incompatible changes 73------------------------------------- 74 75### SAR support in VPD for Chrome OS 76 77SAR support in VPD has been deprecated for Chrome OS platforms for > 1 78year now. All new Chrome OS platforms have switched to using SAR 79tables from CBFS. For the next release, coreboot is updated to align 80with the Chrome OS factory changes and hence SAR support in VPD is 81deprecated in [CB:51483](https://review.coreboot.org/51483). Starting 82with this release, anyone building coreboot for an already released 83Chrome OS platform with SAR table in VPD will have to extract the 84"wifi_sar" key from VPD and add it as a file to CBFS using following 85steps: 86 * On DUT, read SAR value using `vpd -i RO_VPD -g wifi_sar` 87 * In coreboot repo, generate CBFS SAR file using: 88 `echo ${SAR_STRING} > site-local/${BOARD}-sar.hex` 89 * Add to site-local/Kconfig: 90 ``` 91 config WIFI_SAR_CBFS_FILEPATH 92 string 93 default "site-local/${BOARD}-sar.hex" 94 ``` 95 96### CBFS stage file format change 97 98[CB:46484](https://review.coreboot.org/46484) changed the in-flash 99file format of coreboot stages to prepare for per-file signature 100verification. As described in the commit message in more details, 101when manipulating stages in a CBFS, the cbfstool build must match the 102coreboot image so that they're using the same format: coreboot.rom 103and cbfstool must be built from coreboot sources that either both 104contain this change or both do not contain this change. 105 106Since stages are usually only handled by the coreboot build system 107which builds its own cbfstool (and therefore it always matches 108coreboot.rom) this shouldn't be a concern in the vast majority of 109scenarios. 110 111Significant changes 112------------------- 113 114### AMD SoC cleanup and initial Cezanne APU support 115 116There's initial support for the AMD Cezanne APUs in the tree. This code 117hasn't started as a copy of the previous generation, but was based on a 118slightly modified version of the example/min86 SoC. During the cleanup 119of the existing Picasso SoC code the common parts of the code were 120moved to the common AMD SoC code, so that they could be used by the 121Cezanne code instead of adding another slightly different copy. 122 123### X86 bootblock layout 124 125The static size C_ENV_BOOTBLOCK_SIZE was mostly dropped in favor of 126dynamically allocating the stage size; the Kconfig is still available 127to use as a fixed size and to enforce a maximum for selected chipsets. 128Linker sections are now top-aligned for a reduced flash footprint and to 129maintain the requirements of near jump from reset vector. 130 131### ACPI GNVS framework 132 133SMI handlers for APM_CNT_GNVS_UDPATE were dropped; GNVS pointer to SMM is 134now passed from within SMM_MODULE_LOADER. Allocation and initialisations 135for common ACPI GNVS table entries were largely moved to one centralized 136implementation. 137 138### Intel Xeon Scalable Processor support is now considered mature 139 140Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed 141primarily to serve the needs of the server market. 142 143coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory. 144This release has support for SkyLake-SP (SKX-SP) which is the 2nd 145generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation 146or the latest generation [2] on market. 147 148With this release, the codebase for multiple generations of Xeon-SP 149were unified and optimized: 150* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for 151this board is in Proof Of Concept Status. 152* CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for 153this board is in DVT (Design Validation Test) exit equivalent status. 154Features supported, (performance/stability) test scopes, known issues, 155features gaps are described in [4]. 156 157 158[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/scalable.html 159[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-gen-xeon-scalable-processors-brief.html 160[3] ../mainboard/ocp/tiogapass.md 161[4] ../mainboard/ocp/deltalake.md 162