1coreboot 4.11 2============= 3 4coreboot 4.11 was released on November 19th. 5 6This release cycle was a bit shorter to get closer to our regular 7schedule of releasing in spring and autumn. 8 9Since 4.10 there were 1630 new commits by over 130 developers. 10Of these, about 30 contributed to coreboot for the first time. 11 12Thank you to all contributors who made 4.11 what it is and welcome 13to the project to all new contributors! 14 15Clean Up 16-------- 17 18The past few months saw lots of cleanup across the source tree: 19 20The included headers in source files were stripped down to avoid reading 21unused headers, and unused code fragments, duplicate preprocessor symbols 22and configuration options were eliminated. Even ACPI got its share 23of attention, making our tables and bytecode more standards compliant 24than ever. 25 26The code across Intel's chipsets was unified some more into drivers for 27common function blocks, an effort we're more confident will succeed now 28that Intel itself is driving it. 29 30Chipset work 31------------ 32 33Most activity in the last couple months was on Intel support, 34specifically the Kaby Lake and Cannon Lake drivers were extended 35for the generations following them. 36 37On ARM, the Mediatek 8173 chipset support saw significant work while 38the AMD side worked on getting Picasso support in. 39 40But everything else also saw some action, the relatively old 41(e.g. Intel GM45, Via VX900), the tiny (RISC-V) and the obscure 42(Quark). 43 44Verified Boot 45------------- 46 47The vboot feature that Chromebooks brought into coreboot was extended 48to work on devices that weren't specially adapted for it: In addition 49to its original device family it's now supported on various Lenovo 50laptops, Open Compute Project systems and Siemens industrial machines. 51 52Eltan's support for measured boot continues to be integrated with 53vboot, sharing data structures and generally working together where 54possible. 55 56New devices 57----------- 58 59With 4.11 there's the beginning of support for Intel Tiger Lake and 60Qualcomm's SC7180 SoCs, while we removed the unmaintained support 61for Allwinner's A10 SoC. 62 63There are also 25 new mainboards in our tree: 64 65* AMD PADMELON 66* ASUS P5QL-EM 67* EMULATION QEMU-AARCH64 68* GOOGLE AKEMI 69* GOOGLE ARCADA CML 70* GOOGLE DAMU 71* GOOGLE DOOD 72* GOOGLE DRALLION 73* GOOGLE DRATINI 74* GOOGLE JACUZZI 75* GOOGLE JUNIPER 76* GOOGLE KAKADU 77* GOOGLE KAPPA 78* GOOGLE PUFF 79* GOOGLE SARIEN CML 80* GOOGLE TREEYA 81* GOOGLE TROGDOR 82* LENOVO R60 83* LENOVO T410 84* LENOVO THINKPAD T440P 85* LENOVO X301 86* RAZER BLADE-STEALTH KBL 87* SIEMENS MC-APL6 88* SUPERMICRO X11SSH-TF 89* SUPERMICRO X11SSM-F 90 91In addition to the Cubieboard (which uses the A10 SoC), we also 92removed Google Hatch WHL. 93 94Deprecations 95------------ 96 97Because there was only a single developer board (AMD Torpedo) 98using AGESA family 12h, and because there were multiple, 99unique Coverity issues with it, the associated vendorcode will 100be removed shortly after this release. 101 102Support for the MIPS architecture will also be removed shortly after 103this release as the only board in the tree was a discontinued development 104board and no other work has picked up MIPS support, so it's very likely 105broken already. 106 107After more than a year of planning and following the announcement in 108coreboot 4.10, platforms not using relocatable ramstage, a C bootblock 109and, on systems using Cache as RAM, a postcar stage, won't be supported 110going forward. 111 112Significant changes 113------------------- 114 115### `__PRE_RAM__` is deprecated 116 117Preprocessor use of `defined(__PRE_RAM__)` have been mostly replaced with 118`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`. 119 120The remaining cases and `-D__PRE_RAM__` are to be removed soon after release. 121 122### `__BOOTBLOCK__` et.al. are converted 123 124This applies to all `ENV_xxx` definitions found in `<rules.h>`. 125 126Write code without preprocessor directives whenever possible, replacing 127`#ifdef __BOOTBLOCK__` with `if (ENV_BOOTBLOCK)` 128 129In cases where preprocessor is needed use `#if ENV_BOOTBLOCK` instead. 130 131### `CAR_GLOBAL` is removed where possible 132 133For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL` 134attributes have been removed. Remaining cases from common code are to be 135removed soon after release. 136 137### `TSEG` and `cbmem_top()` mapping 138 139Significant refactoring has been done to achieve some consistency across platforms 140and to reduce code duplication. 141 142### Build system amenities ### 143 144The build system now has an `all` class of source files to remove the need to 145list source files for each and every source class (romstage, ramstage, ...) 146 147The site-local/ mechanism became more robust. 148 149### Stricter coding standards to improve security ### 150 151The build now fails on variable length arrays (that make it way too easy to 152smash a stack) and case statements falling through without a note that it is 153intentional. 154 155### Shorter file headers ### 156 157This project is still under way, but we started moving author information 158from individual files into the global AUTHORS file (and there's the git 159history for more details). 160 161In the future, we also want to replace the license headers (lots of lines) 162in each file with spdx identifiers (one line) and so we added a LICENSES/ 163directory that contains the full text of all the licenses that are used 164throughout our tree. 165 166### Variant creation scripts ### 167 168To ease the creation of variant boards, `util/mainboard/` now contains 169scripts to generate a new variant to a given board. These are still 170specific to google/hatch at this time, but they're written with the idea 171of becoming more generally useful. 172 173### Payloads ### 174 175Payload integration has been updated, coreinfo learned to cope with 176UPPER CASE commands and libpayload knows how to deal with USB3 hubs. 177 178### Added vboot support to the following platforms: 179 180* intel/gm45 181* intel/nehalem 182 183### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK: 184 185* intel/i945 186* intel/x4x 187* intel/gm45 188* intel/nehalem 189* intel/sandybridge 190* intel/braswell 191 192### libgfxinit ### 193 194Most notable, dynamic CDClk configuration was added to libgfxinit, 195to support higher resolution displays without changes in the static 196configuration. It also received some fixes for better DP and eDP 197compatibility, better error recovery for Intel's fickle GMBus and 198updated platform support: 199* Correct HDMI clock limit for G45. 200* DP support for Ibex Peak (Ironlake graphics). 201* Fixed scaling on eDP for Broadwell. 202* Support for ULX variants of Haswell and later. 203* Support for Kaby, Amber, Coffee and Whiskey Lake. 204 205### Other 206* Did cleanups around TSC timer 207* Improved automatic VR configuration on SKL/KBL 208* Filled additional fields in SMBIOS type 4 209* Removed magic value replay from Intel Nehalem/ibexpeak code base 210* Added OpenSBI on RISCV platforms 211* Did more preparations for Intel TXT support 212* Did more preparations for x86_64 stage support 213* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb 214