1# Supermicro X10SLM+-F 2 3This section details how to run coreboot on the [Supermicro X10SLM+-F]. 4 5## Required proprietary blobs 6 7```{eval-rst} 8Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. 9``` 10 11## Building coreboot 12 13```{eval-rst} 14If you haven't already, build the coreboot toolchain as described in 15:doc:`../../tutorial/part1`. 16``` 17 18A fully working image should be possible so long as you have the 19Haswell `mrc.bin` file. You can set the basic config with the following 20commands. However, it is strongly advised to use `make menuconfig` 21afterwards (or instead), so that you can see all of the settings. 22 23```bash 24make distclean # Note: this will remove your current config, if it exists. 25touch .config 26./util/scripts/config --enable VENDOR_SUPERMICRO 27./util/scripts/config --enable BOARD_SUPERMICRO_X10SLM_PLUS_F 28./util/scripts/config --enable HAVE_MRC 29make olddefconfig 30``` 31 32If you don't plan on using coreboot's serial console to collect logs, 33you might want to disable it at this point (`./util/scripts/config 34--disable CONSOLE_SERIAL`). It should reduce the boot time by several 35seconds. However, a more flexible method is to change the console log 36level from within an OS using `util/nvramtool`, or with the `nvramcui` 37payload. 38 39Now, run `make` to build the coreboot image. 40 41## Flashing coreboot 42 43```{eval-rst} 44In addition to the information here, please see the 45:doc:`../../tutorial/flashing_firmware/index`. 46``` 47 48### Internal programming 49 50Under the vendor firmware, the BIOS region of the flash chip is 51write-protected. Additionally, the vendor flashing tool does not work 52with a coreboot image. So, [external programming](#external-programming) 53needs to be used when first installing coreboot. By default, coreboot is 54not configured to write-protect the BIOS region, so internal programming 55can be used thereafter. 56 57[flashrom] may be used to flash coreboot internally: 58 59```bash 60sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom 61``` 62 63The use of `--noverify-all` is required since the Management Engine 64region is not readable even by the host. 65 66### External programming 67 68The main firmware flash chip is an SOIC-8 package located near the CMOS 69battery and SATA ports. It should come with a sticker attached that 70states the firmware revision (e.g. "X10SLH 4.424"). The chip model is 71an N25Q128A ([datasheet][N25Q128A]). 72 73As with [internal programming](#internal-programming), [flashrom] works 74reliably: 75 76```bash 77flashrom -p <your-programmer> --ifd -i bios -w coreboot.rom 78``` 79 80For flashing to work, power to the board should be disconnected (ACPI 81G3), and power should be supplied from the external programmer. There is 82a diode attached to Vcc, so such flashing should not damage the board. 83During testing, a single X10SLM+-F has been flashed dozens of times this 84way without issue. 85 86## BMC (IPMI) 87 88This board has an ASPEED [AST2400], which has BMC functionality. The 89BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400]. 90This chip is an MX25L25635F ([datasheet][MX25L25635F]). 91 92### Removing the BMC functionality 93 94The BMC functionality on this board can be removed. If you do not need 95its features, removing the BMC functionality might increase security. 96This topic has not been widely explored, and you should only **undertake 97this process at your own risk.** 98 99There is a jumper labelled `JPB1` on the board that states the ability 100to disable the BMC. Though, pins 1 and 2 are fixed together, keeping 101the BMC enabled. It might be possible to disable the BMC by cutting the 102connection between pins 1 and 2 (and then connecting pins 2 and 3). This 103has not been tested so far. 104 105Another approach is to erase the entire BMC firmware chip. However, if 106this is done, and the board's power cycled, the voltage changes on some 107pins of the flash chip, **so it will be harder to flash it again!** 108 109To remove the firmware, connect an external programmer to the BMC 110firmware chip. Vcc should **not** be connected via the external 111programmer. The system should be turned off, but the power still 112connected (ACPI S5). Then, erase the chip with [flashrom]. Power cycle 113the board, and the BMC should no longer be active. 114 115If you erase the BMC firmware while using the **vendor BIOS**, you 116will need to cut the connection between pins 1 and 2 of `JPB1`. The 117system will stall for two minutes each time when booting, but it will 118eventually start. There is no such delay when running coreboot. 119 120## ECC DRAM 121 122```{eval-rst} 123ECC DRAM seems to work, but please see 124:doc:`../../northbridge/intel/haswell/mrc.bin` 125for caveats. 126``` 127 128## Known issues 129 130- Broadwell CPUs are not supported. They might work with minimal changes 131 to the code, but this has not been tested. 132 133- The PCH thermal sensor doesn't yet have a driver in coreboot, so it 134 can't be used for temperature readings. 135 136- There is no automatic, OS-independent fan control. This is because 137 the Super I/O hardware monitor can only obtain valid CPU temperature 138 readings from the PECI agent, but the required driver doesn't exist 139 in coreboot. The `coretemp` driver can still be used for accurate CPU 140 temperature readings from an OS, and hence the OS can do fan control. 141 142```{eval-rst} 143Please also see :doc:`../../northbridge/intel/haswell/known-issues`. 144``` 145 146## Untested 147 148- TPM 149- PCIe (likely to work, but maybe not at Gen 3 speeds) 150- BMC (IPMI) functionality 151- internal serial port 152- chassis intrusion header 153- SATA DOM header 154- standby power header 155- serial GPIO headers 156- power supply SMBus header 157- jumpers not otherwise mentioned 158- LEDs 159 160## Working 161 162- USB 163- S3 suspend/resume 164- Gigabit Ethernet 165- SATA 166- external serial port 167- VGA graphics 168- disabling VGA graphics using the jumper 169- hiding the AST2400 using the CMOS setting 170- Super I/O hardware monitor (see [Known issues](#known-issues)) 171- initialisation with Haswell MRC version 1.6.1 build 2 172- flashrom under coreboot 173- Wake-on-LAN 174- front panel header 175- internal buzzer 176 177## Technology 178 179```{eval-rst} 180+------------------+--------------------------------------------------+ 181| CPU | :doc:`../../northbridge/intel/haswell/index` | 182+------------------+--------------------------------------------------+ 183| PCH | Intel Lynx Point (C224) | 184+------------------+--------------------------------------------------+ 185| Super I/O | Nuvoton NCT6776 | 186+------------------+--------------------------------------------------+ 187| Coprocessor | Intel SPS (server version of the ME) | 188+------------------+--------------------------------------------------+ 189| Coprocessor | ASPEED AST2400 | 190+------------------+--------------------------------------------------+ 191``` 192 193## Extra links 194 195- [Board manual] 196 197[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 198[Board manual]: https://www.supermicro.com/manuals/motherboard/C224/MNL-1500.pdf 199[flashrom]: https://flashrom.org/Flashrom 200[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf 201[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf 202[Supermicro X10SLM+-F]: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm 203