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1# Protectli Vault VP2420
2
3This page describes how to run coreboot on the [Protectli VP2420].
4
5![](VP2420_back.jpg)
6![](VP2420_front.jpg)
7
8## Required proprietary blobs
9
10To build a minimal working coreboot image some blobs are required (assuming
11only the BIOS region is being modified).
12
13```{eval-rst}
14+-----------------+---------------------------------+---------------------+
15| Binary file     | Apply                           | Required / Optional |
16+=================+=================================+=====================+
17| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
18+-----------------+---------------------------------+---------------------+
19| microcode       | CPU microcode                   | Required            |
20+-----------------+---------------------------------+---------------------+
21```
22
23FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done
24automatically by the coreboot build system and included into the image) from
25the `3rdparty/fsp` submodule.
26
27Microcode updates are automatically included into the coreboot image by build
28system from the `3rdparty/intel-microcode` submodule.
29
30## Flashing coreboot
31
32### Internal programming
33
34The main SPI flash can be accessed using [flashrom]. Firmware can be easily
35flashed with internal programmer (either BIOS region or full image).
36
37### External programming
38
39The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
40This chip is located on the top side of the case (the lid side). One has to
41remove 4 top cover screws and lift up the lid. The flash chip is soldered in
42under RAM, easily accessed after taking out the memory. Specifically, it's a
43KH25L12835F (3.3V) which is a clone of Macronix
44MX25L12835F - [datasheet][MX25L12835F].
45
46![](VP2420_internal.jpg)
47
48## Working
49
50- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
51- 4 Ethernet ports
52- HDMI, DisplayPort
53- flashrom
54- M.2 WiFi
55- M.2 4G LTE
56- M.2 SATA and NVMe
57- 2.5'' SATA SSD
58- eMMC
59- Super I/O serial port 0 via front microUSB connector
60- SMBus (reading SPD from DIMMs)
61- Initialization with Elkhart Lake FSP 2.0
62- SeaBIOS payload (version rel-1.16.0)
63- TianoCore UEFIPayload
64- Reset switch
65- Booting Debian, Ubuntu, FreeBSD
66
67## Technology
68
69```{eval-rst}
70+------------------+--------------------------------------------------+
71| CPU              | Intel Celeron J6412                              |
72+------------------+--------------------------------------------------+
73| PCH              | Intel Elkhart Lake                               |
74+------------------+--------------------------------------------------+
75| Super I/O, EC    | ITE IT8613E                                      |
76+------------------+--------------------------------------------------+
77| Coprocessor      | Intel Management Engine                          |
78+------------------+--------------------------------------------------+
79```
80
81## Useful links
82
83```{toctree}
84:maxdepth: 1
85
86VP2420 Hardware Overview <https://protectli.com/kb/vp2400-series-hardware-overview/>
87VP2420 Product Page <https://protectli.com/product/vp2420/>
88Protectli TPM module <https://protectli.com/product/tpm-module/>
89MX25L12835F <https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf>
90flashrom <https://flashrom.org/Flashrom>
91```
92