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1# PC Engines APU2
2
3This page describes how to run coreboot on PC Engines APU2 platform.
4
5## Technology
6
7```{eval-rst}
8+------------+---------------------------------------------------------------+
9| CPU        | AMD G series GX-412TC                                         |
10+------------+---------------------------------------------------------------+
11| CPU core   | 1 GHz quad Puma core with 64 bit support                      |
12|            | 32K data + 32K instruction cache per core, shared 2MB L2 cache|
13+------------+---------------------------------------------------------------+
14| DRAM       | 2 or 4 GB DDR3-1333 DRAM                                      |
15+------------+---------------------------------------------------------------+
16| Boot       | From SD card, USB, mSATA SSD, SATA                            |
17+------------+---------------------------------------------------------------+
18| Power      | 6 to 12W of 12V power                                         |
19+------------+---------------------------------------------------------------+
20| Firmware   | coreboot with support for iPXE and USB boot                   |
21+------------+---------------------------------------------------------------+
22```
23
24## Required proprietary blobs
25
26To build working coreboot image some blobs are needed.
27
28```{eval-rst}
29+-----------------+---------------------------------+---------------------+
30| Binary file     | Apply                           | Required / Optional |
31+=================+=================================+=====================+
32| amdfw.rom*      | AMD Platform Security Processor | Required            |
33+-----------------+---------------------------------+---------------------+
34| AGESA.bin       | AGESA Platform Initialization   | Required            |
35+-----------------+---------------------------------+---------------------+
36| xhci.bin        | AMD XHCI controller             | Optional            |
37+-----------------+---------------------------------+---------------------+
38```
39(\*) - package containing all required blobs for PSP. Directory, in which all
40blobs are listed and available is: *3rdparty/southbridge/amd/avalon/PSP*
41
42## Flashing coreboot
43
44```{eval-rst}
45+---------------------+--------------------------+
46| Type                | Value                    |
47+=====================+==========================+
48| Socketed flash      | no                       |
49+---------------------+--------------------------+
50| Model               | W25Q64                   |
51+---------------------+--------------------------+
52| Size                | 8 MiB                    |
53+---------------------+--------------------------+
54| Package             | SOIC-8                   |
55+---------------------+--------------------------+
56| Write protection    | jumper on WP# pin*       |
57+---------------------+--------------------------+
58| Dual BIOS feature   | no                       |
59+---------------------+--------------------------+
60| Internal flashing   | yes                      |
61+---------------------+--------------------------+
62```
63(\*) - It is used in normal SPI mode, but can be dangerous when using Quad SPI
64Flash. Then, pull-down resistors should be considered rather than jumper.
65
66### Internal programming
67
68The SPI flash can be accessed using [flashrom].
69
70    flashrom -p internal -w coreboot.rom
71
72### External programming
73
74**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5
75(Soft-off) power state. S5 state can be forced by shorting power button pin on
76J2 header.
77
78The external access to flash chip is available through standard SOP-8 clip or
79SOP-8 header next to the flash chip on the board. Notice that not all boards
80have a header soldered down originally. Hence, there could be an empty slot with
818 eyelets, so you can solder down a header on your own. The SPI flash chip and
82SPI header are marked in the picture below. Also there is SPI header and SPI
83flash pin layout included. Depend on using header or clip there are important
84rules:
85- using header J6 - don't connect 1,7,8 pins
86- using clip U23 - don't connect 3,7,8 pins
87
88Also signatures at the schematic can be ambiguous:
89- J6 SPIDI = U23 SO = MISO
90- J6 SPIDO = U23 SI = MOSI
91
92There is no restrictions as to the programmer device. It is only recommended to
93flash firmware without supplying power. External programming can be performed,
94for example using OrangePi and Armbian. You can exploit linux_spi driver which
95provides communication with SPI devices. Example command to program SPI flash
96with OrangePi using linux_spi:
97
98    flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000
99
100**apu2 platform with marked in SPI header and SPI flash chip**
101
102![][apu2_flash]
103
104**SPI header pin layout**
105
106![][spi_header]
107
108## Schematics
109
110PC Engines APU2 [platform schematics](https://pcengines.ch/schema/apu2d.pdf)
111are available for free on PC Engines official site. Both configurations
112(2GB/4GB) have the same PCB and schematic.
113
114[apu2_flash]: apu2.jpg
115[spi_header]: apu2_spi.jpg
116[flashrom]: https://flashrom.org/Flashrom
117