1# ASRock H81M-HDS 2 3This page describes how to run coreboot on the [ASRock H81M-HDS]. 4 5## Required proprietary blobs 6 7```{eval-rst} 8Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. 9``` 10 11## Building coreboot 12 13A fully working image should be possible just by setting your MAC 14address and obtaining the Haswell mrc. You can set the basic config 15with the following commands. However, it is strongly advised to use 16`make menuconfig` afterwards (or instead), so that you can see all of 17the settings. 18 19```bash 20make distclean # Note: this will remove your current config, if it exists. 21touch .config 22./util/scripts/config --enable VENDOR_ASROCK 23./util/scripts/config --enable BOARD_ASROCK_H81M_HDS 24./util/scripts/config --enable HAVE_MRC 25./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" # Fill this in! 26make olddefconfig 27``` 28 29If you don't plan on using coreboot's serial console to collect logs, 30you might want to disable it at this point (`./util/scripts/config 31--disable CONSOLE_SERIAL`). It should reduce the boot time by several 32seconds. However, a more flexible method is to change the console log 33level from within an OS using `util/nvramtool`, or with the `nvramcui` 34payload. 35 36Now, run `make` to build the coreboot image. 37 38## Flashing coreboot 39 40### Internal programming 41 42The main SPI flash can be accessed using [flashrom]. By default, only 43the BIOS region of the flash is writable. If you wish to change any 44other region, such as the Management Engine or firmware descriptor, then 45an external programmer is required (unless you find a clever way around 46the flash protection). 47 48The following command may be used to flash coreboot: 49 50```bash 51sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom 52``` 53 54The use of `--noverify-all` is required since the Management Engine 55region is not readable even by the host. 56 57### External programming 58 59The flash chip is a 4 MiB socketed DIP-8 chip. Specifically, it's a 60Winbond W25Q32FV, whose datasheet can be found [here][W25Q32FV]. 61The chip is located to the bottom right-hand side of the board. For 62a precise location, refer to section 1.4 (Motherboard Layout) of the 63[board manual], where the chip is labelled "32Mb BIOS". Take note of 64the chip's orientation, remove it from its socket, and flash it with 65an external programmer. For reference, the notch in the chip should be 66facing towards the bottom of the board. 67 68## Known issues 69 70- The VGA port doesn't work until the OS reinitialises the display. 71 72- There is no automatic, OS-independent fan control. This is because 73 the Super I/O hardware monitor can only obtain valid CPU temperature 74 readings from the PECI agent, but the required driver doesn't exist 75 in coreboot. The `coretemp` driver can still be used for accurate CPU 76 temperature readings from an OS. 77 78```{eval-rst} 79Please also see :doc:`../../northbridge/intel/haswell/known-issues`. 80``` 81 82## Untested 83 84- parallel port 85- PS/2 keyboard 86- EHCI debug 87- TPM 88- infrared module 89- chassis intrusion header 90- chassis speaker header 91 92## Working 93 94- USB 95- S3 suspend/resume 96- Gigabit Ethernet 97- integrated graphics 98- PCIe 99- SATA 100- PS/2 mouse 101- serial port 102- hardware monitor (see [Known issues](#known-issues)) 103- onboard audio 104- front panel audio 105- initialisation with Haswell mrc version 1.6.1 build 2 106- graphics init with libgfxinit (see [Known issues](#known-issues)) 107- flashrom under the vendor firmware 108- flashrom under coreboot 109- Wake-on-LAN 110- Using `me_cleaner` 111 112## Technology 113 114```{eval-rst} 115+------------------+--------------------------------------------------+ 116| Northbridge | :doc:`../../northbridge/intel/haswell/index` | 117+------------------+--------------------------------------------------+ 118| Southbridge | Intel Lynx Point (H81) | 119+------------------+--------------------------------------------------+ 120| CPU | Intel Haswell (LGA1150) | 121+------------------+--------------------------------------------------+ 122| Super I/O | Nuvoton NCT6776 | 123+------------------+--------------------------------------------------+ 124| EC | None | 125+------------------+--------------------------------------------------+ 126| Coprocessor | Intel Management Engine | 127+------------------+--------------------------------------------------+ 128``` 129 130[ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/ 131[W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf 132[flashrom]: https://flashrom.org/Flashrom 133[Board manual]: https://web.archive.org/web/20191231093418/http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf 134