1# RISC-V architecture documentation 2 3This section contains documentation about coreboot on RISC-V architecture. 4 5## Mode usage 6All stages run in M mode. 7 8Payloads have a choice of managing M mode activity: they can control 9everything or nothing. 10 11Payloads run from the romstage (i.e. rampayloads) are started in M mode. 12The payload must, for example, prepare and install its own SBI. 13 14Payloads run from the ramstage are started in S mode, and trap delegation 15will have been done. These payloads rely on the SBI and can not replace it. 16 17## Stage handoff protocol 18On entry to a stage or payload (including SELF payloads), 19* all harts are running. 20* A0 is the hart ID. 21* A1 is the pointer to the Flattened Device Tree (FDT). 22* A2 contains the additional program calling argument: 23 - cbmem_top for ramstage 24 - the address of the payload for opensbi 25 26## Additional payload handoff requirements 27The location of cbmem should be placed in a node in the FDT. 28 29## OpenSBI 30In case the payload doesn't install it's own SBI, like the [RISCV-PK] does, 31[OpenSBI] can be used instead. 32It's loaded into RAM after coreboot has finished loading the payload. 33coreboot then will jump to OpenSBI providing a pointer to the real payload, 34which OpenSBI will jump to once the SBI is installed. 35 36Besides providing SBI it also sets protected memory regions and provides 37a platform independent console. 38 39The OpenSBI code is always run in M mode. 40 41## Trap delegation 42Traps are delegated to the payload. 43 44## SMP within a stage 45At the beginning of each stage, all harts save 0 are spinning in a loop on 46a semaphore. At the end of the stage harts 1..max are released by changing 47the semaphore. 48 49A possible way to do this is to have a pointer to a struct containing 50variables, e.g. 51 52```c 53struct blocker { 54 void (*fn)(); // never returns 55} 56``` 57 58The hart blocks until fn is non-null, and then calls it. If fn returns, we 59will panic if possible, but behavior is largely undefined. 60 61Only hart 0 runs through most of the code in each stage. 62 63[RISCV-PK]: https://github.com/riscv/riscv-pk 64[OpenSBI]: https://github.com/riscv/opensbi 65