1 /* Copyright (c) 2018, Google Inc.
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
14
15 #ifndef OPENSSL_HEADER_SHA_INTERNAL_H
16 #define OPENSSL_HEADER_SHA_INTERNAL_H
17
18 #include <openssl/base.h>
19
20 #include "../../internal.h"
21
22 #if defined(__cplusplus)
23 extern "C" {
24 #endif
25
26 // Define SHA{n}[_{variant}]_ASM if sha{n}_block_data_order[_{variant}] is
27 // defined in assembly.
28
29 #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM)
30
31 #define SHA1_ASM_NOHW
32 #define SHA256_ASM_NOHW
33 #define SHA512_ASM_NOHW
34
35 #define SHA1_ASM_HW
sha1_hw_capable(void)36 OPENSSL_INLINE int sha1_hw_capable(void) {
37 return CRYPTO_is_ARMv8_SHA1_capable();
38 }
39
40 #define SHA1_ASM_NEON
41 void sha1_block_data_order_neon(uint32_t state[5], const uint8_t *data,
42 size_t num);
43
44 #define SHA256_ASM_HW
sha256_hw_capable(void)45 OPENSSL_INLINE int sha256_hw_capable(void) {
46 return CRYPTO_is_ARMv8_SHA256_capable();
47 }
48
49 #define SHA256_ASM_NEON
50 void sha256_block_data_order_neon(uint32_t state[8], const uint8_t *data,
51 size_t num);
52
53 // Armv8.2 SHA-512 instructions are not available in 32-bit.
54 #define SHA512_ASM_NEON
55 void sha512_block_data_order_neon(uint64_t state[8], const uint8_t *data,
56 size_t num);
57
58 #elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64)
59
60 #define SHA1_ASM_NOHW
61 #define SHA256_ASM_NOHW
62 #define SHA512_ASM_NOHW
63
64 #define SHA1_ASM_HW
65 OPENSSL_INLINE int sha1_hw_capable(void) {
66 return CRYPTO_is_ARMv8_SHA1_capable();
67 }
68
69 #define SHA256_ASM_HW
70 OPENSSL_INLINE int sha256_hw_capable(void) {
71 return CRYPTO_is_ARMv8_SHA256_capable();
72 }
73
74 #define SHA512_ASM_HW
75 OPENSSL_INLINE int sha512_hw_capable(void) {
76 return CRYPTO_is_ARMv8_SHA512_capable();
77 }
78
79 #elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86)
80
81 #define SHA1_ASM_NOHW
82 #define SHA256_ASM_NOHW
83 #define SHA512_ASM_NOHW
84
85 #define SHA1_ASM_SSSE3
86 OPENSSL_INLINE int sha1_ssse3_capable(void) {
87 // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
88 // say to.
89 return CRYPTO_is_SSSE3_capable() && CRYPTO_is_FXSR_capable();
90 }
91 void sha1_block_data_order_ssse3(uint32_t state[5], const uint8_t *data,
92 size_t num);
93
94 #define SHA1_ASM_AVX
95 OPENSSL_INLINE int sha1_avx_capable(void) {
96 // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
97 // discussion in sha1-586.pl.
98 //
99 // TODO(davidben): Should we enable SHAEXT on 32-bit x86?
100 // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
101 // say to.
102 return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu() &&
103 CRYPTO_is_FXSR_capable();
104 }
105 void sha1_block_data_order_avx(uint32_t state[5], const uint8_t *data,
106 size_t num);
107
108 #define SHA256_ASM_SSSE3
109 OPENSSL_INLINE int sha256_ssse3_capable(void) {
110 // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
111 // say to.
112 return CRYPTO_is_SSSE3_capable() && CRYPTO_is_FXSR_capable();
113 }
114 void sha256_block_data_order_ssse3(uint32_t state[8], const uint8_t *data,
115 size_t num);
116
117 #define SHA256_ASM_AVX
118 OPENSSL_INLINE int sha256_avx_capable(void) {
119 // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
120 // discussion in sha1-586.pl.
121 //
122 // TODO(davidben): Should we enable SHAEXT on 32-bit x86?
123 // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
124 // say to.
125 return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu() &&
126 CRYPTO_is_FXSR_capable();
127 }
128 void sha256_block_data_order_avx(uint32_t state[8], const uint8_t *data,
129 size_t num);
130
131 #define SHA512_ASM_SSSE3
132 OPENSSL_INLINE int sha512_ssse3_capable(void) {
133 // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
134 // say to.
135 return CRYPTO_is_SSSE3_capable() && CRYPTO_is_FXSR_capable();
136 }
137 void sha512_block_data_order_ssse3(uint64_t state[8], const uint8_t *data,
138 size_t num);
139
140 #elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64)
141
142 #define SHA1_ASM_NOHW
143 #define SHA256_ASM_NOHW
144 #define SHA512_ASM_NOHW
145
146 #define SHA1_ASM_HW
147 OPENSSL_INLINE int sha1_hw_capable(void) {
148 return CRYPTO_is_x86_SHA_capable() && CRYPTO_is_SSSE3_capable();
149 }
150
151 #define SHA1_ASM_AVX2
152 OPENSSL_INLINE int sha1_avx2_capable(void) {
153 return CRYPTO_is_AVX2_capable() && CRYPTO_is_BMI2_capable() &&
154 CRYPTO_is_BMI1_capable();
155 }
156 void sha1_block_data_order_avx2(uint32_t state[5], const uint8_t *data,
157 size_t num);
158
159 #define SHA1_ASM_AVX
160 OPENSSL_INLINE int sha1_avx_capable(void) {
161 // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
162 // discussion in sha1-586.pl.
163 return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
164 }
165 void sha1_block_data_order_avx(uint32_t state[5], const uint8_t *data,
166 size_t num);
167
168 #define SHA1_ASM_SSSE3
169 OPENSSL_INLINE int sha1_ssse3_capable(void) {
170 return CRYPTO_is_SSSE3_capable();
171 }
172 void sha1_block_data_order_ssse3(uint32_t state[5], const uint8_t *data,
173 size_t num);
174
175 #define SHA256_ASM_HW
176 OPENSSL_INLINE int sha256_hw_capable(void) {
177 // Note that the original assembly did not check SSSE3.
178 return CRYPTO_is_x86_SHA_capable() && CRYPTO_is_SSSE3_capable();
179 }
180
181 #define SHA256_ASM_AVX
182 OPENSSL_INLINE int sha256_avx_capable(void) {
183 // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
184 // discussion in sha1-586.pl.
185 return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
186 }
187 void sha256_block_data_order_avx(uint32_t state[8], const uint8_t *data,
188 size_t num);
189
190 #define SHA256_ASM_SSSE3
191 OPENSSL_INLINE int sha256_ssse3_capable(void) {
192 return CRYPTO_is_SSSE3_capable();
193 }
194 void sha256_block_data_order_ssse3(uint32_t state[8], const uint8_t *data,
195 size_t num);
196
197 #define SHA512_ASM_AVX
198 OPENSSL_INLINE int sha512_avx_capable(void) {
199 // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
200 // discussion in sha1-586.pl.
201 return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
202 }
203 void sha512_block_data_order_avx(uint64_t state[8], const uint8_t *data,
204 size_t num);
205
206 #endif
207
208 #if defined(SHA1_ASM_HW)
209 void sha1_block_data_order_hw(uint32_t state[5], const uint8_t *data,
210 size_t num);
211 #endif
212 #if defined(SHA1_ASM_NOHW)
213 void sha1_block_data_order_nohw(uint32_t state[5], const uint8_t *data,
214 size_t num);
215 #endif
216
217 #if defined(SHA256_ASM_HW)
218 void sha256_block_data_order_hw(uint32_t state[8], const uint8_t *data,
219 size_t num);
220 #endif
221 #if defined(SHA256_ASM_NOHW)
222 void sha256_block_data_order_nohw(uint32_t state[8], const uint8_t *data,
223 size_t num);
224 #endif
225
226 #if defined(SHA512_ASM_HW)
227 void sha512_block_data_order_hw(uint64_t state[8], const uint8_t *data,
228 size_t num);
229 #endif
230
231 #if defined(SHA512_ASM_NOHW)
232 void sha512_block_data_order_nohw(uint64_t state[8], const uint8_t *data,
233 size_t num);
234 #endif
235
236 #if defined(__cplusplus)
237 } // extern "C"
238 #endif
239
240 #endif // OPENSSL_HEADER_SHA_INTERNAL_H
241