1#! /usr/bin/env perl 2# Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved. 3# 4# Licensed under the OpenSSL license (the "License"). You may not use 5# this file except in compliance with the License. You can obtain a copy 6# in the file LICENSE in the source distribution or at 7# https://www.openssl.org/source/license.html 8 9 10# ==================================================================== 11# Written by Andy Polyakov <[email protected]> for the OpenSSL 12# project. The module is, however, dual licensed under OpenSSL and 13# CRYPTOGAMS licenses depending on where you obtain it. For further 14# details see http://www.openssl.org/~appro/cryptogams/. 15# 16# Permission to use under GPL terms is granted. 17# ==================================================================== 18 19# SHA512 block procedure for ARMv4. September 2007. 20 21# This code is ~4.5 (four and a half) times faster than code generated 22# by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue 23# Xscale PXA250 core]. 24# 25# July 2010. 26# 27# Rescheduling for dual-issue pipeline resulted in 6% improvement on 28# Cortex A8 core and ~40 cycles per processed byte. 29 30# February 2011. 31# 32# Profiler-assisted and platform-specific optimization resulted in 7% 33# improvement on Coxtex A8 core and ~38 cycles per byte. 34 35# March 2011. 36# 37# Add NEON implementation. On Cortex A8 it was measured to process 38# one byte in 23.3 cycles or ~60% faster than integer-only code. 39 40# August 2012. 41# 42# Improve NEON performance by 12% on Snapdragon S4. In absolute 43# terms it's 22.6 cycles per byte, which is disappointing result. 44# Technical writers asserted that 3-way S4 pipeline can sustain 45# multiple NEON instructions per cycle, but dual NEON issue could 46# not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html 47# for further details. On side note Cortex-A15 processes one byte in 48# 16 cycles. 49 50# Byte order [in]dependence. ========================================= 51# 52# Originally caller was expected to maintain specific *dword* order in 53# h[0-7], namely with most significant dword at *lower* address, which 54# was reflected in below two parameters as 0 and 4. Now caller is 55# expected to maintain native byte order for whole 64-bit values. 56$hi="HI"; 57$lo="LO"; 58# ==================================================================== 59 60$flavour = shift; 61if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; } 62else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} } 63 64if ($flavour && $flavour ne "void") { 65 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 66 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or 67 ( $xlate="${dir}../../../perlasm/arm-xlate.pl" and -f $xlate) or 68 die "can't locate arm-xlate.pl"; 69 70 open OUT,"| \"$^X\" \"$xlate\" $flavour \"$output\""; 71 *STDOUT=*OUT; 72} else { 73 open OUT,">$output"; 74 *STDOUT=*OUT; 75} 76 77$ctx="r0"; # parameter block 78$inp="r1"; 79$len="r2"; 80 81$Tlo="r3"; 82$Thi="r4"; 83$Alo="r5"; 84$Ahi="r6"; 85$Elo="r7"; 86$Ehi="r8"; 87$t0="r9"; 88$t1="r10"; 89$t2="r11"; 90$t3="r12"; 91############ r13 is stack pointer 92$Ktbl="r14"; 93############ r15 is program counter 94 95$Aoff=8*0; 96$Boff=8*1; 97$Coff=8*2; 98$Doff=8*3; 99$Eoff=8*4; 100$Foff=8*5; 101$Goff=8*6; 102$Hoff=8*7; 103$Xoff=8*8; 104 105sub BODY_00_15() { 106my $magic = shift; 107$code.=<<___; 108 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) 109 @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 110 @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 111 mov $t0,$Elo,lsr#14 112 str $Tlo,[sp,#$Xoff+0] 113 mov $t1,$Ehi,lsr#14 114 str $Thi,[sp,#$Xoff+4] 115 eor $t0,$t0,$Ehi,lsl#18 116 ldr $t2,[sp,#$Hoff+0] @ h.lo 117 eor $t1,$t1,$Elo,lsl#18 118 ldr $t3,[sp,#$Hoff+4] @ h.hi 119 eor $t0,$t0,$Elo,lsr#18 120 eor $t1,$t1,$Ehi,lsr#18 121 eor $t0,$t0,$Ehi,lsl#14 122 eor $t1,$t1,$Elo,lsl#14 123 eor $t0,$t0,$Ehi,lsr#9 124 eor $t1,$t1,$Elo,lsr#9 125 eor $t0,$t0,$Elo,lsl#23 126 eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e) 127 adds $Tlo,$Tlo,$t0 128 ldr $t0,[sp,#$Foff+0] @ f.lo 129 adc $Thi,$Thi,$t1 @ T += Sigma1(e) 130 ldr $t1,[sp,#$Foff+4] @ f.hi 131 adds $Tlo,$Tlo,$t2 132 ldr $t2,[sp,#$Goff+0] @ g.lo 133 adc $Thi,$Thi,$t3 @ T += h 134 ldr $t3,[sp,#$Goff+4] @ g.hi 135 136 eor $t0,$t0,$t2 137 str $Elo,[sp,#$Eoff+0] 138 eor $t1,$t1,$t3 139 str $Ehi,[sp,#$Eoff+4] 140 and $t0,$t0,$Elo 141 str $Alo,[sp,#$Aoff+0] 142 and $t1,$t1,$Ehi 143 str $Ahi,[sp,#$Aoff+4] 144 eor $t0,$t0,$t2 145 ldr $t2,[$Ktbl,#$lo] @ K[i].lo 146 eor $t1,$t1,$t3 @ Ch(e,f,g) 147 ldr $t3,[$Ktbl,#$hi] @ K[i].hi 148 149 adds $Tlo,$Tlo,$t0 150 ldr $Elo,[sp,#$Doff+0] @ d.lo 151 adc $Thi,$Thi,$t1 @ T += Ch(e,f,g) 152 ldr $Ehi,[sp,#$Doff+4] @ d.hi 153 adds $Tlo,$Tlo,$t2 154 and $t0,$t2,#0xff 155 adc $Thi,$Thi,$t3 @ T += K[i] 156 adds $Elo,$Elo,$Tlo 157 ldr $t2,[sp,#$Boff+0] @ b.lo 158 adc $Ehi,$Ehi,$Thi @ d += T 159 teq $t0,#$magic 160 161 ldr $t3,[sp,#$Coff+0] @ c.lo 162#if __ARM_ARCH>=7 163 it eq @ Thumb2 thing, sanity check in ARM 164#endif 165 orreq $Ktbl,$Ktbl,#1 166 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) 167 @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 168 @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 169 mov $t0,$Alo,lsr#28 170 mov $t1,$Ahi,lsr#28 171 eor $t0,$t0,$Ahi,lsl#4 172 eor $t1,$t1,$Alo,lsl#4 173 eor $t0,$t0,$Ahi,lsr#2 174 eor $t1,$t1,$Alo,lsr#2 175 eor $t0,$t0,$Alo,lsl#30 176 eor $t1,$t1,$Ahi,lsl#30 177 eor $t0,$t0,$Ahi,lsr#7 178 eor $t1,$t1,$Alo,lsr#7 179 eor $t0,$t0,$Alo,lsl#25 180 eor $t1,$t1,$Ahi,lsl#25 @ Sigma0(a) 181 adds $Tlo,$Tlo,$t0 182 and $t0,$Alo,$t2 183 adc $Thi,$Thi,$t1 @ T += Sigma0(a) 184 185 ldr $t1,[sp,#$Boff+4] @ b.hi 186 orr $Alo,$Alo,$t2 187 ldr $t2,[sp,#$Coff+4] @ c.hi 188 and $Alo,$Alo,$t3 189 and $t3,$Ahi,$t1 190 orr $Ahi,$Ahi,$t1 191 orr $Alo,$Alo,$t0 @ Maj(a,b,c).lo 192 and $Ahi,$Ahi,$t2 193 adds $Alo,$Alo,$Tlo 194 orr $Ahi,$Ahi,$t3 @ Maj(a,b,c).hi 195 sub sp,sp,#8 196 adc $Ahi,$Ahi,$Thi @ h += T 197 tst $Ktbl,#1 198 add $Ktbl,$Ktbl,#8 199___ 200} 201$code=<<___; 202#ifndef __KERNEL__ 203# include <openssl/arm_arch.h> 204# define VFP_ABI_PUSH vstmdb sp!,{d8-d15} 205# define VFP_ABI_POP vldmia sp!,{d8-d15} 206#else 207# define __ARM_MAX_ARCH__ 7 208# define VFP_ABI_PUSH 209# define VFP_ABI_POP 210#endif 211 212@ Silence ARMv8 deprecated IT instruction warnings. This file is used by both 213@ ARMv7 and ARMv8 processors and does not use ARMv8 instructions. 214.arch armv7-a 215 216#ifdef __ARMEL__ 217# define LO 0 218# define HI 4 219# define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1 220#else 221# define HI 0 222# define LO 4 223# define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1 224#endif 225 226.text 227#if defined(__thumb2__) 228.syntax unified 229.thumb 230# define adrl adr 231#else 232.code 32 233#endif 234 235.type K512,%object 236.align 5 237K512: 238WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd) 239WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc) 240WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019) 241WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118) 242WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe) 243WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2) 244WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1) 245WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694) 246WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3) 247WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65) 248WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483) 249WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5) 250WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210) 251WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4) 252WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725) 253WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70) 254WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926) 255WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df) 256WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8) 257WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b) 258WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001) 259WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30) 260WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910) 261WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8) 262WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53) 263WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8) 264WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb) 265WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3) 266WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60) 267WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec) 268WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9) 269WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b) 270WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207) 271WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178) 272WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6) 273WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b) 274WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493) 275WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c) 276WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a) 277WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817) 278.size K512,.-K512 279 280.global sha512_block_data_order_nohw 281.type sha512_block_data_order_nohw,%function 282sha512_block_data_order_nohw: 283 add $len,$inp,$len,lsl#7 @ len to point at the end of inp 284 stmdb sp!,{r4-r12,lr} 285 adr $Ktbl,K512 286 sub sp,sp,#9*8 287 288 ldr $Elo,[$ctx,#$Eoff+$lo] 289 ldr $Ehi,[$ctx,#$Eoff+$hi] 290 ldr $t0, [$ctx,#$Goff+$lo] 291 ldr $t1, [$ctx,#$Goff+$hi] 292 ldr $t2, [$ctx,#$Hoff+$lo] 293 ldr $t3, [$ctx,#$Hoff+$hi] 294.Loop: 295 str $t0, [sp,#$Goff+0] 296 str $t1, [sp,#$Goff+4] 297 str $t2, [sp,#$Hoff+0] 298 str $t3, [sp,#$Hoff+4] 299 ldr $Alo,[$ctx,#$Aoff+$lo] 300 ldr $Ahi,[$ctx,#$Aoff+$hi] 301 ldr $Tlo,[$ctx,#$Boff+$lo] 302 ldr $Thi,[$ctx,#$Boff+$hi] 303 ldr $t0, [$ctx,#$Coff+$lo] 304 ldr $t1, [$ctx,#$Coff+$hi] 305 ldr $t2, [$ctx,#$Doff+$lo] 306 ldr $t3, [$ctx,#$Doff+$hi] 307 str $Tlo,[sp,#$Boff+0] 308 str $Thi,[sp,#$Boff+4] 309 str $t0, [sp,#$Coff+0] 310 str $t1, [sp,#$Coff+4] 311 str $t2, [sp,#$Doff+0] 312 str $t3, [sp,#$Doff+4] 313 ldr $Tlo,[$ctx,#$Foff+$lo] 314 ldr $Thi,[$ctx,#$Foff+$hi] 315 str $Tlo,[sp,#$Foff+0] 316 str $Thi,[sp,#$Foff+4] 317 318.L00_15: 319#if __ARM_ARCH<7 320 ldrb $Tlo,[$inp,#7] 321 ldrb $t0, [$inp,#6] 322 ldrb $t1, [$inp,#5] 323 ldrb $t2, [$inp,#4] 324 ldrb $Thi,[$inp,#3] 325 ldrb $t3, [$inp,#2] 326 orr $Tlo,$Tlo,$t0,lsl#8 327 ldrb $t0, [$inp,#1] 328 orr $Tlo,$Tlo,$t1,lsl#16 329 ldrb $t1, [$inp],#8 330 orr $Tlo,$Tlo,$t2,lsl#24 331 orr $Thi,$Thi,$t3,lsl#8 332 orr $Thi,$Thi,$t0,lsl#16 333 orr $Thi,$Thi,$t1,lsl#24 334#else 335 ldr $Tlo,[$inp,#4] 336 ldr $Thi,[$inp],#8 337#ifdef __ARMEL__ 338 rev $Tlo,$Tlo 339 rev $Thi,$Thi 340#endif 341#endif 342___ 343 &BODY_00_15(0x94); 344$code.=<<___; 345 tst $Ktbl,#1 346 beq .L00_15 347 ldr $t0,[sp,#`$Xoff+8*(16-1)`+0] 348 ldr $t1,[sp,#`$Xoff+8*(16-1)`+4] 349 bic $Ktbl,$Ktbl,#1 350.L16_79: 351 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) 352 @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25 353 @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7 354 mov $Tlo,$t0,lsr#1 355 ldr $t2,[sp,#`$Xoff+8*(16-14)`+0] 356 mov $Thi,$t1,lsr#1 357 ldr $t3,[sp,#`$Xoff+8*(16-14)`+4] 358 eor $Tlo,$Tlo,$t1,lsl#31 359 eor $Thi,$Thi,$t0,lsl#31 360 eor $Tlo,$Tlo,$t0,lsr#8 361 eor $Thi,$Thi,$t1,lsr#8 362 eor $Tlo,$Tlo,$t1,lsl#24 363 eor $Thi,$Thi,$t0,lsl#24 364 eor $Tlo,$Tlo,$t0,lsr#7 365 eor $Thi,$Thi,$t1,lsr#7 366 eor $Tlo,$Tlo,$t1,lsl#25 367 368 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)) 369 @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26 370 @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6 371 mov $t0,$t2,lsr#19 372 mov $t1,$t3,lsr#19 373 eor $t0,$t0,$t3,lsl#13 374 eor $t1,$t1,$t2,lsl#13 375 eor $t0,$t0,$t3,lsr#29 376 eor $t1,$t1,$t2,lsr#29 377 eor $t0,$t0,$t2,lsl#3 378 eor $t1,$t1,$t3,lsl#3 379 eor $t0,$t0,$t2,lsr#6 380 eor $t1,$t1,$t3,lsr#6 381 ldr $t2,[sp,#`$Xoff+8*(16-9)`+0] 382 eor $t0,$t0,$t3,lsl#26 383 384 ldr $t3,[sp,#`$Xoff+8*(16-9)`+4] 385 adds $Tlo,$Tlo,$t0 386 ldr $t0,[sp,#`$Xoff+8*16`+0] 387 adc $Thi,$Thi,$t1 388 389 ldr $t1,[sp,#`$Xoff+8*16`+4] 390 adds $Tlo,$Tlo,$t2 391 adc $Thi,$Thi,$t3 392 adds $Tlo,$Tlo,$t0 393 adc $Thi,$Thi,$t1 394___ 395 &BODY_00_15(0x17); 396$code.=<<___; 397#if __ARM_ARCH>=7 398 ittt eq @ Thumb2 thing, sanity check in ARM 399#endif 400 ldreq $t0,[sp,#`$Xoff+8*(16-1)`+0] 401 ldreq $t1,[sp,#`$Xoff+8*(16-1)`+4] 402 beq .L16_79 403 bic $Ktbl,$Ktbl,#1 404 405 ldr $Tlo,[sp,#$Boff+0] 406 ldr $Thi,[sp,#$Boff+4] 407 ldr $t0, [$ctx,#$Aoff+$lo] 408 ldr $t1, [$ctx,#$Aoff+$hi] 409 ldr $t2, [$ctx,#$Boff+$lo] 410 ldr $t3, [$ctx,#$Boff+$hi] 411 adds $t0,$Alo,$t0 412 str $t0, [$ctx,#$Aoff+$lo] 413 adc $t1,$Ahi,$t1 414 str $t1, [$ctx,#$Aoff+$hi] 415 adds $t2,$Tlo,$t2 416 str $t2, [$ctx,#$Boff+$lo] 417 adc $t3,$Thi,$t3 418 str $t3, [$ctx,#$Boff+$hi] 419 420 ldr $Alo,[sp,#$Coff+0] 421 ldr $Ahi,[sp,#$Coff+4] 422 ldr $Tlo,[sp,#$Doff+0] 423 ldr $Thi,[sp,#$Doff+4] 424 ldr $t0, [$ctx,#$Coff+$lo] 425 ldr $t1, [$ctx,#$Coff+$hi] 426 ldr $t2, [$ctx,#$Doff+$lo] 427 ldr $t3, [$ctx,#$Doff+$hi] 428 adds $t0,$Alo,$t0 429 str $t0, [$ctx,#$Coff+$lo] 430 adc $t1,$Ahi,$t1 431 str $t1, [$ctx,#$Coff+$hi] 432 adds $t2,$Tlo,$t2 433 str $t2, [$ctx,#$Doff+$lo] 434 adc $t3,$Thi,$t3 435 str $t3, [$ctx,#$Doff+$hi] 436 437 ldr $Tlo,[sp,#$Foff+0] 438 ldr $Thi,[sp,#$Foff+4] 439 ldr $t0, [$ctx,#$Eoff+$lo] 440 ldr $t1, [$ctx,#$Eoff+$hi] 441 ldr $t2, [$ctx,#$Foff+$lo] 442 ldr $t3, [$ctx,#$Foff+$hi] 443 adds $Elo,$Elo,$t0 444 str $Elo,[$ctx,#$Eoff+$lo] 445 adc $Ehi,$Ehi,$t1 446 str $Ehi,[$ctx,#$Eoff+$hi] 447 adds $t2,$Tlo,$t2 448 str $t2, [$ctx,#$Foff+$lo] 449 adc $t3,$Thi,$t3 450 str $t3, [$ctx,#$Foff+$hi] 451 452 ldr $Alo,[sp,#$Goff+0] 453 ldr $Ahi,[sp,#$Goff+4] 454 ldr $Tlo,[sp,#$Hoff+0] 455 ldr $Thi,[sp,#$Hoff+4] 456 ldr $t0, [$ctx,#$Goff+$lo] 457 ldr $t1, [$ctx,#$Goff+$hi] 458 ldr $t2, [$ctx,#$Hoff+$lo] 459 ldr $t3, [$ctx,#$Hoff+$hi] 460 adds $t0,$Alo,$t0 461 str $t0, [$ctx,#$Goff+$lo] 462 adc $t1,$Ahi,$t1 463 str $t1, [$ctx,#$Goff+$hi] 464 adds $t2,$Tlo,$t2 465 str $t2, [$ctx,#$Hoff+$lo] 466 adc $t3,$Thi,$t3 467 str $t3, [$ctx,#$Hoff+$hi] 468 469 add sp,sp,#640 470 sub $Ktbl,$Ktbl,#640 471 472 teq $inp,$len 473 bne .Loop 474 475 add sp,sp,#8*9 @ destroy frame 476#if __ARM_ARCH>=5 477 ldmia sp!,{r4-r12,pc} 478#else 479 ldmia sp!,{r4-r12,lr} 480 tst lr,#1 481 moveq pc,lr @ be binary compatible with V4, yet 482 bx lr @ interoperable with Thumb ISA:-) 483#endif 484.size sha512_block_data_order_nohw,.-sha512_block_data_order_nohw 485___ 486 487{ 488my @Sigma0=(28,34,39); 489my @Sigma1=(14,18,41); 490my @sigma0=(1, 8, 7); 491my @sigma1=(19,61,6); 492 493my $Ktbl="r3"; 494my $cnt="r12"; # volatile register known as ip, intra-procedure-call scratch 495 496my @X=map("d$_",(0..15)); 497my @V=($A,$B,$C,$D,$E,$F,$G,$H)=map("d$_",(16..23)); 498 499sub NEON_00_15() { 500my $i=shift; 501my ($a,$b,$c,$d,$e,$f,$g,$h)=@_; 502my ($t0,$t1,$t2,$T1,$K,$Ch,$Maj)=map("d$_",(24..31)); # temps 503 504$code.=<<___ if ($i<16 || $i&1); 505 vshr.u64 $t0,$e,#@Sigma1[0] @ $i 506#if $i<16 507 vld1.64 {@X[$i%16]},[$inp]! @ handles unaligned 508#endif 509 vshr.u64 $t1,$e,#@Sigma1[1] 510#if $i>0 511 vadd.i64 $a,$Maj @ h+=Maj from the past 512#endif 513 vshr.u64 $t2,$e,#@Sigma1[2] 514___ 515$code.=<<___; 516 vld1.64 {$K},[$Ktbl,:64]! @ K[i++] 517 vsli.64 $t0,$e,#`64-@Sigma1[0]` 518 vsli.64 $t1,$e,#`64-@Sigma1[1]` 519 vmov $Ch,$e 520 vsli.64 $t2,$e,#`64-@Sigma1[2]` 521#if $i<16 && defined(__ARMEL__) 522 vrev64.8 @X[$i],@X[$i] 523#endif 524 veor $t1,$t0 525 vbsl $Ch,$f,$g @ Ch(e,f,g) 526 vshr.u64 $t0,$a,#@Sigma0[0] 527 veor $t2,$t1 @ Sigma1(e) 528 vadd.i64 $T1,$Ch,$h 529 vshr.u64 $t1,$a,#@Sigma0[1] 530 vsli.64 $t0,$a,#`64-@Sigma0[0]` 531 vadd.i64 $T1,$t2 532 vshr.u64 $t2,$a,#@Sigma0[2] 533 vadd.i64 $K,@X[$i%16] 534 vsli.64 $t1,$a,#`64-@Sigma0[1]` 535 veor $Maj,$a,$b 536 vsli.64 $t2,$a,#`64-@Sigma0[2]` 537 veor $h,$t0,$t1 538 vadd.i64 $T1,$K 539 vbsl $Maj,$c,$b @ Maj(a,b,c) 540 veor $h,$t2 @ Sigma0(a) 541 vadd.i64 $d,$T1 542 vadd.i64 $Maj,$T1 543 @ vadd.i64 $h,$Maj 544___ 545} 546 547sub NEON_16_79() { 548my $i=shift; 549 550if ($i&1) { &NEON_00_15($i,@_); return; } 551 552# 2x-vectorized, therefore runs every 2nd round 553my @X=map("q$_",(0..7)); # view @X as 128-bit vector 554my ($t0,$t1,$s0,$s1) = map("q$_",(12..15)); # temps 555my ($d0,$d1,$d2) = map("d$_",(24..26)); # temps from NEON_00_15 556my $e=@_[4]; # $e from NEON_00_15 557$i /= 2; 558$code.=<<___; 559 vshr.u64 $t0,@X[($i+7)%8],#@sigma1[0] 560 vshr.u64 $t1,@X[($i+7)%8],#@sigma1[1] 561 vadd.i64 @_[0],d30 @ h+=Maj from the past 562 vshr.u64 $s1,@X[($i+7)%8],#@sigma1[2] 563 vsli.64 $t0,@X[($i+7)%8],#`64-@sigma1[0]` 564 vext.8 $s0,@X[$i%8],@X[($i+1)%8],#8 @ X[i+1] 565 vsli.64 $t1,@X[($i+7)%8],#`64-@sigma1[1]` 566 veor $s1,$t0 567 vshr.u64 $t0,$s0,#@sigma0[0] 568 veor $s1,$t1 @ sigma1(X[i+14]) 569 vshr.u64 $t1,$s0,#@sigma0[1] 570 vadd.i64 @X[$i%8],$s1 571 vshr.u64 $s1,$s0,#@sigma0[2] 572 vsli.64 $t0,$s0,#`64-@sigma0[0]` 573 vsli.64 $t1,$s0,#`64-@sigma0[1]` 574 vext.8 $s0,@X[($i+4)%8],@X[($i+5)%8],#8 @ X[i+9] 575 veor $s1,$t0 576 vshr.u64 $d0,$e,#@Sigma1[0] @ from NEON_00_15 577 vadd.i64 @X[$i%8],$s0 578 vshr.u64 $d1,$e,#@Sigma1[1] @ from NEON_00_15 579 veor $s1,$t1 @ sigma0(X[i+1]) 580 vshr.u64 $d2,$e,#@Sigma1[2] @ from NEON_00_15 581 vadd.i64 @X[$i%8],$s1 582___ 583 &NEON_00_15(2*$i,@_); 584} 585 586$code.=<<___; 587#if __ARM_MAX_ARCH__>=7 588.arch armv7-a 589.fpu neon 590 591.global sha512_block_data_order_neon 592.type sha512_block_data_order_neon,%function 593.align 4 594sha512_block_data_order_neon: 595 dmb @ errata #451034 on early Cortex A8 596 add $len,$inp,$len,lsl#7 @ len to point at the end of inp 597 adr $Ktbl,K512 598 VFP_ABI_PUSH 599 vldmia $ctx,{$A-$H} @ load context 600.Loop_neon: 601___ 602for($i=0;$i<16;$i++) { &NEON_00_15($i,@V); unshift(@V,pop(@V)); } 603$code.=<<___; 604 mov $cnt,#4 605.L16_79_neon: 606 subs $cnt,#1 607___ 608for(;$i<32;$i++) { &NEON_16_79($i,@V); unshift(@V,pop(@V)); } 609$code.=<<___; 610 bne .L16_79_neon 611 612 vadd.i64 $A,d30 @ h+=Maj from the past 613 vldmia $ctx,{d24-d31} @ load context to temp 614 vadd.i64 q8,q12 @ vectorized accumulate 615 vadd.i64 q9,q13 616 vadd.i64 q10,q14 617 vadd.i64 q11,q15 618 vstmia $ctx,{$A-$H} @ save context 619 teq $inp,$len 620 sub $Ktbl,#640 @ rewind K512 621 bne .Loop_neon 622 623 VFP_ABI_POP 624 ret @ bx lr 625.size sha512_block_data_order_neon,.-sha512_block_data_order_neon 626#endif 627___ 628} 629$code.=<<___; 630.asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>" 631.align 2 632___ 633 634$code =~ s/\`([^\`]*)\`/eval $1/gem; 635$code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4 636$code =~ s/\bret\b/bx lr/gm; 637 638open SELF,$0; 639while(<SELF>) { 640 next if (/^#!/); 641 last if (!s/^#/@/ and !/^$/); 642 print; 643} 644close SELF; 645 646print $code; 647close STDOUT or die "error closing STDOUT: $!"; # enforce flush 648