1#! /usr/bin/env perl 2# Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved. 3# 4# Licensed under the OpenSSL license (the "License"). You may not use 5# this file except in compliance with the License. You can obtain a copy 6# in the file LICENSE in the source distribution or at 7# https://www.openssl.org/source/license.html 8 9 10# ==================================================================== 11# Written by Andy Polyakov <[email protected]> for the OpenSSL 12# project. The module is, however, dual licensed under OpenSSL and 13# CRYPTOGAMS licenses depending on where you obtain it. For further 14# details see http://www.openssl.org/~appro/cryptogams/. 15# ==================================================================== 16 17# sha1_block procedure for ARMv4. 18# 19# January 2007. 20 21# Size/performance trade-off 22# ==================================================================== 23# impl size in bytes comp cycles[*] measured performance 24# ==================================================================== 25# thumb 304 3212 4420 26# armv4-small 392/+29% 1958/+64% 2250/+96% 27# armv4-compact 740/+89% 1552/+26% 1840/+22% 28# armv4-large 1420/+92% 1307/+19% 1370/+34%[***] 29# full unroll ~5100/+260% ~1260/+4% ~1300/+5% 30# ==================================================================== 31# thumb = same as 'small' but in Thumb instructions[**] and 32# with recurring code in two private functions; 33# small = detached Xload/update, loops are folded; 34# compact = detached Xload/update, 5x unroll; 35# large = interleaved Xload/update, 5x unroll; 36# full unroll = interleaved Xload/update, full unroll, estimated[!]; 37# 38# [*] Manually counted instructions in "grand" loop body. Measured 39# performance is affected by prologue and epilogue overhead, 40# i-cache availability, branch penalties, etc. 41# [**] While each Thumb instruction is twice smaller, they are not as 42# diverse as ARM ones: e.g., there are only two arithmetic 43# instructions with 3 arguments, no [fixed] rotate, addressing 44# modes are limited. As result it takes more instructions to do 45# the same job in Thumb, therefore the code is never twice as 46# small and always slower. 47# [***] which is also ~35% better than compiler generated code. Dual- 48# issue Cortex A8 core was measured to process input block in 49# ~990 cycles. 50 51# August 2010. 52# 53# Rescheduling for dual-issue pipeline resulted in 13% improvement on 54# Cortex A8 core and in absolute terms ~870 cycles per input block 55# [or 13.6 cycles per byte]. 56 57# February 2011. 58# 59# Profiler-assisted and platform-specific optimization resulted in 10% 60# improvement on Cortex A8 core and 12.2 cycles per byte. 61 62# September 2013. 63# 64# Add NEON implementation (see sha1-586.pl for background info). On 65# Cortex A8 it was measured to process one byte in 6.7 cycles or >80% 66# faster than integer-only code. Because [fully unrolled] NEON code 67# is ~2.5x larger and there are some redundant instructions executed 68# when processing last block, improvement is not as big for smallest 69# blocks, only ~30%. Snapdragon S4 is a tad faster, 6.4 cycles per 70# byte, which is also >80% faster than integer-only code. Cortex-A15 71# is even faster spending 5.6 cycles per byte outperforming integer- 72# only code by factor of 2. 73 74# May 2014. 75# 76# Add ARMv8 code path performing at 2.35 cpb on Apple A7. 77 78$flavour = shift; 79if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; } 80else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} } 81 82if ($flavour && $flavour ne "void") { 83 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 84 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or 85 ( $xlate="${dir}../../../perlasm/arm-xlate.pl" and -f $xlate) or 86 die "can't locate arm-xlate.pl"; 87 88 open OUT,"| \"$^X\" \"$xlate\" $flavour \"$output\""; 89 *STDOUT=*OUT; 90} else { 91 open OUT,">$output"; 92 *STDOUT=*OUT; 93} 94 95$ctx="r0"; 96$inp="r1"; 97$len="r2"; 98$a="r3"; 99$b="r4"; 100$c="r5"; 101$d="r6"; 102$e="r7"; 103$K="r8"; 104$t0="r9"; 105$t1="r10"; 106$t2="r11"; 107$t3="r12"; 108$Xi="r14"; 109@V=($a,$b,$c,$d,$e); 110 111sub Xupdate { 112my ($a,$b,$c,$d,$e,$opt1,$opt2)=@_; 113$code.=<<___; 114 ldr $t0,[$Xi,#15*4] 115 ldr $t1,[$Xi,#13*4] 116 ldr $t2,[$Xi,#7*4] 117 add $e,$K,$e,ror#2 @ E+=K_xx_xx 118 ldr $t3,[$Xi,#2*4] 119 eor $t0,$t0,$t1 120 eor $t2,$t2,$t3 @ 1 cycle stall 121 eor $t1,$c,$d @ F_xx_xx 122 mov $t0,$t0,ror#31 123 add $e,$e,$a,ror#27 @ E+=ROR(A,27) 124 eor $t0,$t0,$t2,ror#31 125 str $t0,[$Xi,#-4]! 126 $opt1 @ F_xx_xx 127 $opt2 @ F_xx_xx 128 add $e,$e,$t0 @ E+=X[i] 129___ 130} 131 132sub BODY_00_15 { 133my ($a,$b,$c,$d,$e)=@_; 134$code.=<<___; 135#if __ARM_ARCH<7 136 ldrb $t1,[$inp,#2] 137 ldrb $t0,[$inp,#3] 138 ldrb $t2,[$inp,#1] 139 add $e,$K,$e,ror#2 @ E+=K_00_19 140 ldrb $t3,[$inp],#4 141 orr $t0,$t0,$t1,lsl#8 142 eor $t1,$c,$d @ F_xx_xx 143 orr $t0,$t0,$t2,lsl#16 144 add $e,$e,$a,ror#27 @ E+=ROR(A,27) 145 orr $t0,$t0,$t3,lsl#24 146#else 147 ldr $t0,[$inp],#4 @ handles unaligned 148 add $e,$K,$e,ror#2 @ E+=K_00_19 149 eor $t1,$c,$d @ F_xx_xx 150 add $e,$e,$a,ror#27 @ E+=ROR(A,27) 151#ifdef __ARMEL__ 152 rev $t0,$t0 @ byte swap 153#endif 154#endif 155 and $t1,$b,$t1,ror#2 156 add $e,$e,$t0 @ E+=X[i] 157 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D) 158 str $t0,[$Xi,#-4]! 159 add $e,$e,$t1 @ E+=F_00_19(B,C,D) 160___ 161} 162 163sub BODY_16_19 { 164my ($a,$b,$c,$d,$e)=@_; 165 &Xupdate(@_,"and $t1,$b,$t1,ror#2"); 166$code.=<<___; 167 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D) 168 add $e,$e,$t1 @ E+=F_00_19(B,C,D) 169___ 170} 171 172sub BODY_20_39 { 173my ($a,$b,$c,$d,$e)=@_; 174 &Xupdate(@_,"eor $t1,$b,$t1,ror#2"); 175$code.=<<___; 176 add $e,$e,$t1 @ E+=F_20_39(B,C,D) 177___ 178} 179 180sub BODY_40_59 { 181my ($a,$b,$c,$d,$e)=@_; 182 &Xupdate(@_,"and $t1,$b,$t1,ror#2","and $t2,$c,$d"); 183$code.=<<___; 184 add $e,$e,$t1 @ E+=F_40_59(B,C,D) 185 add $e,$e,$t2,ror#2 186___ 187} 188 189$code=<<___; 190#include <openssl/arm_arch.h> 191 192.text 193#if defined(__thumb2__) 194.syntax unified 195.thumb 196#else 197.code 32 198#endif 199 200.global sha1_block_data_order_nohw 201.type sha1_block_data_order_nohw,%function 202 203.align 5 204sha1_block_data_order_nohw: 205 stmdb sp!,{r4-r12,lr} 206 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp 207 ldmia $ctx,{$a,$b,$c,$d,$e} 208.Lloop: 209 ldr $K,.LK_00_19 210 mov $Xi,sp 211 sub sp,sp,#15*4 212 mov $c,$c,ror#30 213 mov $d,$d,ror#30 214 mov $e,$e,ror#30 @ [6] 215.L_00_15: 216___ 217for($i=0;$i<5;$i++) { 218 &BODY_00_15(@V); unshift(@V,pop(@V)); 219} 220$code.=<<___; 221#if defined(__thumb2__) 222 mov $t3,sp 223 teq $Xi,$t3 224#else 225 teq $Xi,sp 226#endif 227 bne .L_00_15 @ [((11+4)*5+2)*3] 228 sub sp,sp,#25*4 229___ 230 &BODY_00_15(@V); unshift(@V,pop(@V)); 231 &BODY_16_19(@V); unshift(@V,pop(@V)); 232 &BODY_16_19(@V); unshift(@V,pop(@V)); 233 &BODY_16_19(@V); unshift(@V,pop(@V)); 234 &BODY_16_19(@V); unshift(@V,pop(@V)); 235$code.=<<___; 236 237 ldr $K,.LK_20_39 @ [+15+16*4] 238 cmn sp,#0 @ [+3], clear carry to denote 20_39 239.L_20_39_or_60_79: 240___ 241for($i=0;$i<5;$i++) { 242 &BODY_20_39(@V); unshift(@V,pop(@V)); 243} 244$code.=<<___; 245#if defined(__thumb2__) 246 mov $t3,sp 247 teq $Xi,$t3 248#else 249 teq $Xi,sp @ preserve carry 250#endif 251 bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4] 252 bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes 253 254 ldr $K,.LK_40_59 255 sub sp,sp,#20*4 @ [+2] 256.L_40_59: 257___ 258for($i=0;$i<5;$i++) { 259 &BODY_40_59(@V); unshift(@V,pop(@V)); 260} 261$code.=<<___; 262#if defined(__thumb2__) 263 mov $t3,sp 264 teq $Xi,$t3 265#else 266 teq $Xi,sp 267#endif 268 bne .L_40_59 @ [+((12+5)*5+2)*4] 269 270 ldr $K,.LK_60_79 271 sub sp,sp,#20*4 272 cmp sp,#0 @ set carry to denote 60_79 273 b .L_20_39_or_60_79 @ [+4], spare 300 bytes 274.L_done: 275 add sp,sp,#80*4 @ "deallocate" stack frame 276 ldmia $ctx,{$K,$t0,$t1,$t2,$t3} 277 add $a,$K,$a 278 add $b,$t0,$b 279 add $c,$t1,$c,ror#2 280 add $d,$t2,$d,ror#2 281 add $e,$t3,$e,ror#2 282 stmia $ctx,{$a,$b,$c,$d,$e} 283 teq $inp,$len 284 bne .Lloop @ [+18], total 1307 285 286#if __ARM_ARCH>=5 287 ldmia sp!,{r4-r12,pc} 288#else 289 ldmia sp!,{r4-r12,lr} 290 tst lr,#1 291 moveq pc,lr @ be binary compatible with V4, yet 292 bx lr @ interoperable with Thumb ISA:-) 293#endif 294.size sha1_block_data_order_nohw,.-sha1_block_data_order_nohw 295 296.align 5 297.LK_00_19: .word 0x5a827999 298.LK_20_39: .word 0x6ed9eba1 299.LK_40_59: .word 0x8f1bbcdc 300.LK_60_79: .word 0xca62c1d6 301.asciz "SHA1 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro\@openssl.org>" 302.align 5 303___ 304##################################################################### 305# NEON stuff 306# 307{{{ 308my @V=($a,$b,$c,$d,$e); 309my ($K_XX_XX,$Ki,$t0,$t1,$Xfer,$saved_sp)=map("r$_",(8..12,14)); 310my $Xi=4; 311my @X=map("q$_",(8..11,0..3)); 312my @Tx=("q12","q13"); 313my ($K,$zero)=("q14","q15"); 314my $j=0; 315 316sub AUTOLOAD() # thunk [simplified] x86-style perlasm 317{ my $opcode = $AUTOLOAD; $opcode =~ s/.*:://; $opcode =~ s/_/\./; 318 my $arg = pop; 319 $arg = "#$arg" if ($arg*1 eq $arg); 320 $code .= "\t$opcode\t".join(',',@_,$arg)."\n"; 321} 322 323sub body_00_19 () { 324 ( 325 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'. 326 '&bic ($t0,$d,$b)', 327 '&add ($e,$e,$Ki)', # e+=X[i]+K 328 '&and ($t1,$c,$b)', 329 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))', 330 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27) 331 '&eor ($t1,$t1,$t0)', # F_00_19 332 '&mov ($b,$b,"ror#2")', # b=ROR(b,2) 333 '&add ($e,$e,$t1);'. # e+=F_00_19 334 '$j++; unshift(@V,pop(@V));' 335 ) 336} 337sub body_20_39 () { 338 ( 339 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'. 340 '&eor ($t0,$b,$d)', 341 '&add ($e,$e,$Ki)', # e+=X[i]+K 342 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15)) if ($j<79)', 343 '&eor ($t1,$t0,$c)', # F_20_39 344 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27) 345 '&mov ($b,$b,"ror#2")', # b=ROR(b,2) 346 '&add ($e,$e,$t1);'. # e+=F_20_39 347 '$j++; unshift(@V,pop(@V));' 348 ) 349} 350sub body_40_59 () { 351 ( 352 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'. 353 '&add ($e,$e,$Ki)', # e+=X[i]+K 354 '&and ($t0,$c,$d)', 355 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))', 356 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27) 357 '&eor ($t1,$c,$d)', 358 '&add ($e,$e,$t0)', 359 '&and ($t1,$t1,$b)', 360 '&mov ($b,$b,"ror#2")', # b=ROR(b,2) 361 '&add ($e,$e,$t1);'. # e+=F_40_59 362 '$j++; unshift(@V,pop(@V));' 363 ) 364} 365 366sub Xupdate_16_31 () 367{ use integer; 368 my $body = shift; 369 my @insns = (&$body,&$body,&$body,&$body); 370 my ($a,$b,$c,$d,$e); 371 372 &vext_8 (@X[0],@X[-4&7],@X[-3&7],8); # compose "X[-14]" in "X[0]" 373 eval(shift(@insns)); 374 eval(shift(@insns)); 375 eval(shift(@insns)); 376 &vadd_i32 (@Tx[1],@X[-1&7],$K); 377 eval(shift(@insns)); 378 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0); 379 eval(shift(@insns)); 380 &vext_8 (@Tx[0],@X[-1&7],$zero,4); # "X[-3]", 3 words 381 eval(shift(@insns)); 382 eval(shift(@insns)); 383 eval(shift(@insns)); 384 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"^="X[-16]" 385 eval(shift(@insns)); 386 eval(shift(@insns)); 387 &veor (@Tx[0],@Tx[0],@X[-2&7]); # "X[-3]"^"X[-8]" 388 eval(shift(@insns)); 389 eval(shift(@insns)); 390 &veor (@Tx[0],@Tx[0],@X[0]); # "X[0]"^="X[-3]"^"X[-8] 391 eval(shift(@insns)); 392 eval(shift(@insns)); 393 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer 394 &sub ($Xfer,$Xfer,64) if ($Xi%4==0); 395 eval(shift(@insns)); 396 eval(shift(@insns)); 397 &vext_8 (@Tx[1],$zero,@Tx[0],4); # "X[0]"<<96, extract one dword 398 eval(shift(@insns)); 399 eval(shift(@insns)); 400 &vadd_i32 (@X[0],@Tx[0],@Tx[0]); 401 eval(shift(@insns)); 402 eval(shift(@insns)); 403 &vsri_32 (@X[0],@Tx[0],31); # "X[0]"<<<=1 404 eval(shift(@insns)); 405 eval(shift(@insns)); 406 eval(shift(@insns)); 407 &vshr_u32 (@Tx[0],@Tx[1],30); 408 eval(shift(@insns)); 409 eval(shift(@insns)); 410 &vshl_u32 (@Tx[1],@Tx[1],2); 411 eval(shift(@insns)); 412 eval(shift(@insns)); 413 &veor (@X[0],@X[0],@Tx[0]); 414 eval(shift(@insns)); 415 eval(shift(@insns)); 416 &veor (@X[0],@X[0],@Tx[1]); # "X[0]"^=("X[0]">>96)<<<2 417 418 foreach (@insns) { eval; } # remaining instructions [if any] 419 420 $Xi++; push(@X,shift(@X)); # "rotate" X[] 421} 422 423sub Xupdate_32_79 () 424{ use integer; 425 my $body = shift; 426 my @insns = (&$body,&$body,&$body,&$body); 427 my ($a,$b,$c,$d,$e); 428 429 &vext_8 (@Tx[0],@X[-2&7],@X[-1&7],8); # compose "X[-6]" 430 eval(shift(@insns)); 431 eval(shift(@insns)); 432 eval(shift(@insns)); 433 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"="X[-32]"^"X[-16]" 434 eval(shift(@insns)); 435 eval(shift(@insns)); 436 &veor (@X[0],@X[0],@X[-7&7]); # "X[0]"^="X[-28]" 437 eval(shift(@insns)); 438 eval(shift(@insns)); 439 &vadd_i32 (@Tx[1],@X[-1&7],$K); 440 eval(shift(@insns)); 441 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0); 442 eval(shift(@insns)); 443 &veor (@Tx[0],@Tx[0],@X[0]); # "X[-6]"^="X[0]" 444 eval(shift(@insns)); 445 eval(shift(@insns)); 446 &vshr_u32 (@X[0],@Tx[0],30); 447 eval(shift(@insns)); 448 eval(shift(@insns)); 449 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer 450 &sub ($Xfer,$Xfer,64) if ($Xi%4==0); 451 eval(shift(@insns)); 452 eval(shift(@insns)); 453 &vsli_32 (@X[0],@Tx[0],2); # "X[0]"="X[-6]"<<<2 454 455 foreach (@insns) { eval; } # remaining instructions [if any] 456 457 $Xi++; push(@X,shift(@X)); # "rotate" X[] 458} 459 460sub Xuplast_80 () 461{ use integer; 462 my $body = shift; 463 my @insns = (&$body,&$body,&$body,&$body); 464 my ($a,$b,$c,$d,$e); 465 466 &vadd_i32 (@Tx[1],@X[-1&7],$K); 467 eval(shift(@insns)); 468 eval(shift(@insns)); 469 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); 470 &sub ($Xfer,$Xfer,64); 471 472 &teq ($inp,$len); 473 &sub ($K_XX_XX,$K_XX_XX,16); # rewind $K_XX_XX 474 &it ("eq"); 475 &subeq ($inp,$inp,64); # reload last block to avoid SEGV 476 &vld1_8 ("{@X[-4&7]-@X[-3&7]}","[$inp]!"); 477 eval(shift(@insns)); 478 eval(shift(@insns)); 479 &vld1_8 ("{@X[-2&7]-@X[-1&7]}","[$inp]!"); 480 eval(shift(@insns)); 481 eval(shift(@insns)); 482 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!"); # load K_00_19 483 eval(shift(@insns)); 484 eval(shift(@insns)); 485 &vrev32_8 (@X[-4&7],@X[-4&7]); 486 487 foreach (@insns) { eval; } # remaining instructions 488 489 $Xi=0; 490} 491 492sub Xloop() 493{ use integer; 494 my $body = shift; 495 my @insns = (&$body,&$body,&$body,&$body); 496 my ($a,$b,$c,$d,$e); 497 498 &vrev32_8 (@X[($Xi-3)&7],@X[($Xi-3)&7]); 499 eval(shift(@insns)); 500 eval(shift(@insns)); 501 &vadd_i32 (@X[$Xi&7],@X[($Xi-4)&7],$K); 502 eval(shift(@insns)); 503 eval(shift(@insns)); 504 &vst1_32 ("{@X[$Xi&7]}","[$Xfer,:128]!");# X[]+K xfer to IALU 505 506 foreach (@insns) { eval; } 507 508 $Xi++; 509} 510 511$code.=<<___; 512#if __ARM_MAX_ARCH__>=7 513.arch armv7-a 514.fpu neon 515 516.global sha1_block_data_order_neon 517.type sha1_block_data_order_neon,%function 518.align 4 519sha1_block_data_order_neon: 520 stmdb sp!,{r4-r12,lr} 521 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp 522 @ dmb @ errata #451034 on early Cortex A8 523 @ vstmdb sp!,{d8-d15} @ ABI specification says so 524 mov $saved_sp,sp 525 sub $Xfer,sp,#64 526 adr $K_XX_XX,.LK_00_19 527 bic $Xfer,$Xfer,#15 @ align for 128-bit stores 528 529 ldmia $ctx,{$a,$b,$c,$d,$e} @ load context 530 mov sp,$Xfer @ alloca 531 532 vld1.8 {@X[-4&7]-@X[-3&7]},[$inp]! @ handles unaligned 533 veor $zero,$zero,$zero 534 vld1.8 {@X[-2&7]-@X[-1&7]},[$inp]! 535 vld1.32 {${K}\[]},[$K_XX_XX,:32]! @ load K_00_19 536 vrev32.8 @X[-4&7],@X[-4&7] @ yes, even on 537 vrev32.8 @X[-3&7],@X[-3&7] @ big-endian... 538 vrev32.8 @X[-2&7],@X[-2&7] 539 vadd.i32 @X[0],@X[-4&7],$K 540 vrev32.8 @X[-1&7],@X[-1&7] 541 vadd.i32 @X[1],@X[-3&7],$K 542 vst1.32 {@X[0]},[$Xfer,:128]! 543 vadd.i32 @X[2],@X[-2&7],$K 544 vst1.32 {@X[1]},[$Xfer,:128]! 545 vst1.32 {@X[2]},[$Xfer,:128]! 546 ldr $Ki,[sp] @ big RAW stall 547 548.Loop_neon: 549___ 550 &Xupdate_16_31(\&body_00_19); 551 &Xupdate_16_31(\&body_00_19); 552 &Xupdate_16_31(\&body_00_19); 553 &Xupdate_16_31(\&body_00_19); 554 &Xupdate_32_79(\&body_00_19); 555 &Xupdate_32_79(\&body_20_39); 556 &Xupdate_32_79(\&body_20_39); 557 &Xupdate_32_79(\&body_20_39); 558 &Xupdate_32_79(\&body_20_39); 559 &Xupdate_32_79(\&body_20_39); 560 &Xupdate_32_79(\&body_40_59); 561 &Xupdate_32_79(\&body_40_59); 562 &Xupdate_32_79(\&body_40_59); 563 &Xupdate_32_79(\&body_40_59); 564 &Xupdate_32_79(\&body_40_59); 565 &Xupdate_32_79(\&body_20_39); 566 &Xuplast_80(\&body_20_39); 567 &Xloop(\&body_20_39); 568 &Xloop(\&body_20_39); 569 &Xloop(\&body_20_39); 570$code.=<<___; 571 ldmia $ctx,{$Ki,$t0,$t1,$Xfer} @ accumulate context 572 add $a,$a,$Ki 573 ldr $Ki,[$ctx,#16] 574 add $b,$b,$t0 575 add $c,$c,$t1 576 add $d,$d,$Xfer 577 it eq 578 moveq sp,$saved_sp 579 add $e,$e,$Ki 580 it ne 581 ldrne $Ki,[sp] 582 stmia $ctx,{$a,$b,$c,$d,$e} 583 itt ne 584 addne $Xfer,sp,#3*16 585 bne .Loop_neon 586 587 @ vldmia sp!,{d8-d15} 588 ldmia sp!,{r4-r12,pc} 589.size sha1_block_data_order_neon,.-sha1_block_data_order_neon 590#endif 591___ 592}}} 593##################################################################### 594# ARMv8 stuff 595# 596{{{ 597my ($ABCD,$E,$E0,$E1)=map("q$_",(0..3)); 598my @MSG=map("q$_",(4..7)); 599my @Kxx=map("q$_",(8..11)); 600my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14)); 601 602$code.=<<___; 603#if __ARM_MAX_ARCH__>=7 604 605# if defined(__thumb2__) 606# define INST(a,b,c,d) .byte c,d|0xf,a,b 607# else 608# define INST(a,b,c,d) .byte a,b,c,d|0x10 609# endif 610 611.global sha1_block_data_order_hw 612.type sha1_block_data_order_hw,%function 613.align 5 614sha1_block_data_order_hw: 615 vstmdb sp!,{d8-d15} @ ABI specification says so 616 617 veor $E,$E,$E 618 adr r3,.LK_00_19 619 vld1.32 {$ABCD},[$ctx]! 620 vld1.32 {$E\[0]},[$ctx] 621 sub $ctx,$ctx,#16 622 vld1.32 {@Kxx[0]\[]},[r3,:32]! 623 vld1.32 {@Kxx[1]\[]},[r3,:32]! 624 vld1.32 {@Kxx[2]\[]},[r3,:32]! 625 vld1.32 {@Kxx[3]\[]},[r3,:32] 626 627.Loop_v8: 628 vld1.8 {@MSG[0]-@MSG[1]},[$inp]! 629 vld1.8 {@MSG[2]-@MSG[3]},[$inp]! 630 vrev32.8 @MSG[0],@MSG[0] 631 vrev32.8 @MSG[1],@MSG[1] 632 633 vadd.i32 $W0,@Kxx[0],@MSG[0] 634 vrev32.8 @MSG[2],@MSG[2] 635 vmov $ABCD_SAVE,$ABCD @ offload 636 subs $len,$len,#1 637 638 vadd.i32 $W1,@Kxx[0],@MSG[1] 639 vrev32.8 @MSG[3],@MSG[3] 640 sha1h $E1,$ABCD @ 0 641 sha1c $ABCD,$E,$W0 642 vadd.i32 $W0,@Kxx[$j],@MSG[2] 643 sha1su0 @MSG[0],@MSG[1],@MSG[2] 644___ 645for ($j=0,$i=1;$i<20-3;$i++) { 646my $f=("c","p","m","p")[$i/5]; 647$code.=<<___; 648 sha1h $E0,$ABCD @ $i 649 sha1$f $ABCD,$E1,$W1 650 vadd.i32 $W1,@Kxx[$j],@MSG[3] 651 sha1su1 @MSG[0],@MSG[3] 652___ 653$code.=<<___ if ($i<20-4); 654 sha1su0 @MSG[1],@MSG[2],@MSG[3] 655___ 656 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0); 657 push(@MSG,shift(@MSG)); $j++ if ((($i+3)%5)==0); 658} 659$code.=<<___; 660 sha1h $E0,$ABCD @ $i 661 sha1p $ABCD,$E1,$W1 662 vadd.i32 $W1,@Kxx[$j],@MSG[3] 663 664 sha1h $E1,$ABCD @ 18 665 sha1p $ABCD,$E0,$W0 666 667 sha1h $E0,$ABCD @ 19 668 sha1p $ABCD,$E1,$W1 669 670 vadd.i32 $E,$E,$E0 671 vadd.i32 $ABCD,$ABCD,$ABCD_SAVE 672 bne .Loop_v8 673 674 vst1.32 {$ABCD},[$ctx]! 675 vst1.32 {$E\[0]},[$ctx] 676 677 vldmia sp!,{d8-d15} 678 ret @ bx lr 679.size sha1_block_data_order_hw,.-sha1_block_data_order_hw 680#endif 681___ 682}}} 683 684{ my %opcode = ( 685 "sha1c" => 0xf2000c40, "sha1p" => 0xf2100c40, 686 "sha1m" => 0xf2200c40, "sha1su0" => 0xf2300c40, 687 "sha1h" => 0xf3b902c0, "sha1su1" => 0xf3ba0380 ); 688 689 sub unsha1 { 690 my ($mnemonic,$arg)=@_; 691 692 if ($arg =~ m/q([0-9]+)(?:,\s*q([0-9]+))?,\s*q([0-9]+)/o) { 693 my $word = $opcode{$mnemonic}|(($1&7)<<13)|(($1&8)<<19) 694 |(($2&7)<<17)|(($2&8)<<4) 695 |(($3&7)<<1) |(($3&8)<<2); 696 # since ARMv7 instructions are always encoded little-endian. 697 # correct solution is to use .inst directive, but older 698 # assemblers don't implement it:-( 699 700 # this fix-up provides Thumb encoding in conjunction with INST 701 $word &= ~0x10000000 if (($word & 0x0f000000) == 0x02000000); 702 sprintf "INST(0x%02x,0x%02x,0x%02x,0x%02x)\t@ %s %s", 703 $word&0xff,($word>>8)&0xff, 704 ($word>>16)&0xff,($word>>24)&0xff, 705 $mnemonic,$arg; 706 } 707 } 708} 709 710foreach (split($/,$code)) { 711 s/{q([0-9]+)\[\]}/sprintf "{d%d[],d%d[]}",2*$1,2*$1+1/eo or 712 s/{q([0-9]+)\[0\]}/sprintf "{d%d[0]}",2*$1/eo; 713 714 s/\b(sha1\w+)\s+(q.*)/unsha1($1,$2)/geo; 715 716 s/\bret\b/bx lr/o or 717 s/\bbx\s+lr\b/.word\t0xe12fff1e/o; # make it possible to compile with -march=armv4 718 719 print $_,$/; 720} 721 722close STDOUT or die "error closing STDOUT: $!"; # enforce flush 723