1 /* Copyright (c) 2018, Google Inc.
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
14
15 #include "internal.h"
16
17 #if defined(OPENSSL_AARCH64) && defined(OPENSSL_FUCHSIA) && \
18 !defined(OPENSSL_STATIC_ARMCAP)
19
20 #include <zircon/features.h>
21 #include <zircon/syscalls.h>
22 #include <zircon/types.h>
23
24 #include <openssl/arm_arch.h>
25
26
OPENSSL_cpuid_setup(void)27 void OPENSSL_cpuid_setup(void) {
28 uint32_t hwcap;
29 zx_status_t rc = zx_system_get_features(ZX_FEATURE_KIND_CPU, &hwcap);
30 if (rc != ZX_OK || (hwcap & ZX_ARM64_FEATURE_ISA_ASIMD) == 0) {
31 // If NEON/ASIMD is missing, don't report other features either. This
32 // matches OpenSSL, and the other features depend on SIMD registers.
33 return;
34 }
35
36 OPENSSL_armcap_P |= ARMV7_NEON;
37
38 if (hwcap & ZX_ARM64_FEATURE_ISA_AES) {
39 OPENSSL_armcap_P |= ARMV8_AES;
40 }
41 if (hwcap & ZX_ARM64_FEATURE_ISA_PMULL) {
42 OPENSSL_armcap_P |= ARMV8_PMULL;
43 }
44 if (hwcap & ZX_ARM64_FEATURE_ISA_SHA1) {
45 OPENSSL_armcap_P |= ARMV8_SHA1;
46 }
47 if (hwcap & ZX_ARM64_FEATURE_ISA_SHA256) {
48 OPENSSL_armcap_P |= ARMV8_SHA256;
49 }
50 if (hwcap & ZX_ARM64_FEATURE_ISA_SHA512) {
51 OPENSSL_armcap_P |= ARMV8_SHA512;
52 }
53 }
54
55 #endif // OPENSSL_AARCH64 && OPENSSL_FUCHSIA && !OPENSSL_STATIC_ARMCAP
56