1*54fd6939SJiyong Park# 2*54fd6939SJiyong Park# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park# 4*54fd6939SJiyong Park# SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park# 6*54fd6939SJiyong Park 7*54fd6939SJiyong ParkRK_PLAT := plat/rockchip 8*54fd6939SJiyong ParkRK_PLAT_SOC := ${RK_PLAT}/${PLAT} 9*54fd6939SJiyong ParkRK_PLAT_COMMON := ${RK_PLAT}/common 10*54fd6939SJiyong Park 11*54fd6939SJiyong ParkDISABLE_BIN_GENERATION := 1 12*54fd6939SJiyong Park 13*54fd6939SJiyong ParkPLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ 14*54fd6939SJiyong Park -I${RK_PLAT_COMMON}/include/ \ 15*54fd6939SJiyong Park -I${RK_PLAT_COMMON}/aarch64/ \ 16*54fd6939SJiyong Park -I${RK_PLAT_COMMON}/drivers/pmu/ \ 17*54fd6939SJiyong Park -I${RK_PLAT_SOC}/ \ 18*54fd6939SJiyong Park -I${RK_PLAT_SOC}/drivers/pmu/ \ 19*54fd6939SJiyong Park -I${RK_PLAT_SOC}/drivers/pwm/ \ 20*54fd6939SJiyong Park -I${RK_PLAT_SOC}/drivers/secure/ \ 21*54fd6939SJiyong Park -I${RK_PLAT_SOC}/drivers/soc/ \ 22*54fd6939SJiyong Park -I${RK_PLAT_SOC}/drivers/dram/ \ 23*54fd6939SJiyong Park -I${RK_PLAT_SOC}/drivers/dp/ \ 24*54fd6939SJiyong Park -I${RK_PLAT_SOC}/include/ \ 25*54fd6939SJiyong Park -I${RK_PLAT_SOC}/include/shared/ \ 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park# Include GICv3 driver files 28*54fd6939SJiyong Parkinclude drivers/arm/gic/v3/gicv3.mk 29*54fd6939SJiyong Park 30*54fd6939SJiyong ParkRK_GIC_SOURCES := ${GICV3_SOURCES} \ 31*54fd6939SJiyong Park plat/common/plat_gicv3.c \ 32*54fd6939SJiyong Park ${RK_PLAT}/common/rockchip_gicv3.c 33*54fd6939SJiyong Park 34*54fd6939SJiyong ParkPLAT_BL_COMMON_SOURCES := lib/bl_aux_params/bl_aux_params.c \ 35*54fd6939SJiyong Park lib/xlat_tables/xlat_tables_common.c \ 36*54fd6939SJiyong Park lib/xlat_tables/aarch64/xlat_tables.c \ 37*54fd6939SJiyong Park plat/common/aarch64/crash_console_helpers.S \ 38*54fd6939SJiyong Park plat/common/plat_psci_common.c 39*54fd6939SJiyong Park 40*54fd6939SJiyong Parkifneq (${ENABLE_STACK_PROTECTOR},0) 41*54fd6939SJiyong ParkPLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c 42*54fd6939SJiyong Parkendif 43*54fd6939SJiyong Park 44*54fd6939SJiyong ParkBL31_SOURCES += ${RK_GIC_SOURCES} \ 45*54fd6939SJiyong Park drivers/arm/cci/cci.c \ 46*54fd6939SJiyong Park drivers/ti/uart/aarch64/16550_console.S \ 47*54fd6939SJiyong Park drivers/delay_timer/delay_timer.c \ 48*54fd6939SJiyong Park drivers/delay_timer/generic_delay_timer.c \ 49*54fd6939SJiyong Park drivers/gpio/gpio.c \ 50*54fd6939SJiyong Park lib/cpus/aarch64/cortex_a53.S \ 51*54fd6939SJiyong Park lib/cpus/aarch64/cortex_a72.S \ 52*54fd6939SJiyong Park ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ 53*54fd6939SJiyong Park ${RK_PLAT_COMMON}/bl31_plat_setup.c \ 54*54fd6939SJiyong Park ${RK_PLAT_COMMON}/params_setup.c \ 55*54fd6939SJiyong Park ${RK_PLAT_COMMON}/aarch64/pmu_sram_cpus_on.S \ 56*54fd6939SJiyong Park ${RK_PLAT_COMMON}/plat_pm.c \ 57*54fd6939SJiyong Park ${RK_PLAT_COMMON}/plat_topology.c \ 58*54fd6939SJiyong Park ${RK_PLAT_COMMON}/aarch64/platform_common.c \ 59*54fd6939SJiyong Park ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ 60*54fd6939SJiyong Park ${RK_PLAT_SOC}/plat_sip_calls.c \ 61*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \ 62*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ 63*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \ 64*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/pmu/m0_ctl.c \ 65*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/pwm/pwm.c \ 66*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/secure/secure.c \ 67*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/soc/soc.c \ 68*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/dram/dfs.c \ 69*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/dram/dram.c \ 70*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c \ 71*54fd6939SJiyong Park ${RK_PLAT_SOC}/drivers/dram/suspend.c 72*54fd6939SJiyong Park 73*54fd6939SJiyong Parkinclude lib/coreboot/coreboot.mk 74*54fd6939SJiyong Parkinclude lib/libfdt/libfdt.mk 75*54fd6939SJiyong Park 76*54fd6939SJiyong Park$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park# Enable workarounds for selected Cortex-A53 erratas. 79*54fd6939SJiyong ParkERRATA_A53_855873 := 1 80*54fd6939SJiyong Park 81*54fd6939SJiyong Park# M0 source build 82*54fd6939SJiyong ParkPLAT_M0 := ${PLAT}m0 83*54fd6939SJiyong ParkBUILD_M0 := ${BUILD_PLAT}/m0 84*54fd6939SJiyong Park 85*54fd6939SJiyong ParkRK3399M0FW=${BUILD_M0}/${PLAT_M0}.bin 86*54fd6939SJiyong Park$(eval $(call add_define_val,RK3399M0FW,\"$(RK3399M0FW)\")) 87*54fd6939SJiyong Park 88*54fd6939SJiyong ParkRK3399M0PMUFW=${BUILD_M0}/${PLAT_M0}pmu.bin 89*54fd6939SJiyong Park$(eval $(call add_define_val,RK3399M0PMUFW,\"$(RK3399M0PMUFW)\")) 90*54fd6939SJiyong Park 91*54fd6939SJiyong Parkifdef PLAT_RK_DP_HDCP 92*54fd6939SJiyong ParkBL31_SOURCES += ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c 93*54fd6939SJiyong Park 94*54fd6939SJiyong ParkHDCPFW=${RK_PLAT_SOC}/drivers/dp/hdcp.bin 95*54fd6939SJiyong Park$(eval $(call add_define_val,HDCPFW,\"$(HDCPFW)\")) 96*54fd6939SJiyong Park 97*54fd6939SJiyong Park${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW) 98*54fd6939SJiyong Park${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW) 99*54fd6939SJiyong Parkendif 100*54fd6939SJiyong Park 101*54fd6939SJiyong Park# CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin 102*54fd6939SJiyong Parkexport CCACHE_EXTRAFILES 103*54fd6939SJiyong Park${BUILD_PLAT}/bl31/pmu_fw.o: CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW) 104*54fd6939SJiyong Park${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c: $(RK3399M0FW) 105*54fd6939SJiyong Park 106*54fd6939SJiyong Park$(eval $(call MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT})) 107*54fd6939SJiyong Park.PHONY: $(RK3399M0FW) 108*54fd6939SJiyong Park$(RK3399M0FW): | ${BUILD_M0} 109*54fd6939SJiyong Park $(MAKE) -C ${RK_PLAT_SOC}/drivers/m0 BUILD=$(abspath ${BUILD_PLAT}/m0) 110*54fd6939SJiyong Park 111*54fd6939SJiyong Park# Do not enable SVE 112*54fd6939SJiyong ParkENABLE_SVE_FOR_NS := 0 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