1 /*
2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <drivers/console.h>
15 #include <drivers/generic_delay_timer.h>
16 #include <drivers/ti/uart/uart_16550.h>
17 #include <lib/mmio.h>
18 #include <plat_private.h>
19 #include <plat/common/platform.h>
20
21 static entry_point_info_t bl33_ep_info;
22
23 /*******************************************************************************
24 * Return a pointer to the 'entry_point_info' structure of the next image for
25 * the security state specified. BL33 corresponds to the non-secure image type.
26 * A NULL pointer is returned if the image does not exist.
27 ******************************************************************************/
sp_min_plat_get_bl33_ep_info(void)28 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
29 {
30 entry_point_info_t *next_image_info;
31
32 next_image_info = &bl33_ep_info;
33
34 if (next_image_info->pc == 0U) {
35 return NULL;
36 }
37
38 return next_image_info;
39 }
40
41 #pragma weak params_early_setup
params_early_setup(u_register_t plat_param_from_bl2)42 void params_early_setup(u_register_t plat_param_from_bl2)
43 {
44 }
45
46 unsigned int plat_is_my_cpu_primary(void);
47
48 /*******************************************************************************
49 * Perform any BL32 specific platform actions.
50 ******************************************************************************/
sp_min_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)51 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
52 u_register_t arg2, u_register_t arg3)
53 {
54 static console_t console;
55 struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
56
57 params_early_setup(arg1);
58
59 if (rockchip_get_uart_base() != 0)
60 console_16550_register(rockchip_get_uart_base(),
61 rockchip_get_uart_clock(),
62 rockchip_get_uart_baudrate(), &console);
63
64 VERBOSE("sp_min_setup\n");
65
66 /* Passing a NULL context is a critical programming error */
67 assert(arg_from_bl2);
68
69 assert(arg_from_bl2->h.type == PARAM_BL31);
70 assert(arg_from_bl2->h.version >= VERSION_1);
71
72 bl33_ep_info = *arg_from_bl2->bl33_ep_info;
73 }
74
75 /*******************************************************************************
76 * Perform any sp_min platform setup code
77 ******************************************************************************/
sp_min_platform_setup(void)78 void sp_min_platform_setup(void)
79 {
80 generic_delay_timer_init();
81 plat_rockchip_soc_init();
82
83 /* Initialize the gic cpu and distributor interfaces */
84 plat_rockchip_gic_driver_init();
85 plat_rockchip_gic_init();
86 plat_rockchip_pmu_init();
87 }
88
89 /*******************************************************************************
90 * Perform the very early platform specific architectural setup here. At the
91 * moment this is only intializes the mmu in a quick and dirty way.
92 ******************************************************************************/
sp_min_plat_arch_setup(void)93 void sp_min_plat_arch_setup(void)
94 {
95 plat_cci_init();
96 plat_cci_enable();
97
98 plat_configure_mmu_svc_mon(BL_CODE_BASE,
99 BL_COHERENT_RAM_END - BL_CODE_BASE,
100 BL_CODE_BASE,
101 BL_CODE_END,
102 BL_COHERENT_RAM_BASE,
103 BL_COHERENT_RAM_END);
104 }
105
sp_min_plat_fiq_handler(uint32_t id)106 void sp_min_plat_fiq_handler(uint32_t id)
107 {
108 VERBOSE("[sp_min] interrupt #%d\n", id);
109 }
110